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Greg Kroah-Hartmanb2441312017-11-01 15:07:57 +01001# SPDX-License-Identifier: GPL-2.0
Jonas Bonnf8c4a272011-06-04 21:52:05 +03002#
3# For a description of the syntax of this configuration file,
Paul Bolle395cf962011-08-15 02:02:26 +02004# see Documentation/kbuild/kconfig-language.txt.
Jonas Bonnf8c4a272011-06-04 21:52:05 +03005#
6
7config OPENRISC
8 def_bool y
9 select OF
10 select OF_EARLY_FLATTREE
Jonas Bonnb4c4c6e2012-04-06 12:52:54 +020011 select IRQ_DOMAIN
Marc Zyngierd1f6f282014-08-26 11:03:19 +010012 select HANDLE_DOMAIN_IRQ
Jonas Bonnf8c4a272011-06-04 21:52:05 +030013 select HAVE_MEMBLOCK
Linus Walleij8636f342016-04-19 13:15:43 +020014 select GPIOLIB
Jonas Bonnf8c4a272011-06-04 21:52:05 +030015 select HAVE_ARCH_TRACEHOOK
Jonas Bonnc0fcaf52012-05-09 23:19:44 +020016 select SPARSE_IRQ
Jonas Bonnf8c4a272011-06-04 21:52:05 +030017 select GENERIC_IRQ_CHIP
18 select GENERIC_IRQ_PROBE
19 select GENERIC_IRQ_SHOW
20 select GENERIC_IOMAP
Ben Hutchings9f13a1f2012-01-10 03:04:32 +000021 select GENERIC_CPU_DEVICES
Andrew Morton04ea1e92015-07-17 16:23:28 -070022 select HAVE_UID16
Richard Weinberger0662d332012-03-02 01:55:11 +010023 select GENERIC_ATOMIC64
Anna-Maria Gleixner5bf8f6b2012-05-18 16:45:51 +000024 select GENERIC_CLOCKEVENTS
Stefan Kristiansson8e6d08e2014-05-11 21:49:34 +030025 select GENERIC_CLOCKEVENTS_BROADCAST
Jonas Bonn603d6632012-05-25 08:24:49 +020026 select GENERIC_STRNCPY_FROM_USER
Jonas Bonnb48b2c32012-05-27 10:25:47 +020027 select GENERIC_STRNLEN_USER
Stefan Kristiansson8e6d08e2014-05-11 21:49:34 +030028 select GENERIC_SMP_IDLE_THREAD
David Howells786d35d2012-09-28 14:31:03 +093029 select MODULES_USE_ELF_RELA
Dave Hansend1a1dc02013-07-01 13:04:42 -070030 select HAVE_DEBUG_STACKOVERFLOW
Stefan Kristiansson4db8e6d2014-05-26 23:31:42 +030031 select OR1K_PIC
Zhaoxiu Zengfff7fb02016-05-20 17:03:57 -070032 select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1
Stafford Horne266c7fa2016-04-03 19:14:49 +090033 select NO_BOOTMEM
Stafford Horneb5f82172017-03-24 07:13:03 +090034 select ARCH_USE_QUEUED_SPINLOCKS
35 select ARCH_USE_QUEUED_RWLOCKS
Stafford Horne9b544702017-10-30 21:38:35 +090036 select OMPIC if SMP
Stafford Horneeecac382017-07-24 21:44:35 +090037 select ARCH_WANT_FRAME_POINTERS
Jonas Bonnf8c4a272011-06-04 21:52:05 +030038
Babu Moger4c97a0c2017-09-08 16:14:22 -070039config CPU_BIG_ENDIAN
40 def_bool y
41
Jonas Bonnf8c4a272011-06-04 21:52:05 +030042config MMU
43 def_bool y
44
Jonas Bonnf8c4a272011-06-04 21:52:05 +030045config RWSEM_GENERIC_SPINLOCK
46 def_bool y
47
48config RWSEM_XCHGADD_ALGORITHM
49 def_bool n
50
51config GENERIC_HWEIGHT
52 def_bool y
53
Uwe Kleine-Königce816fa2014-04-07 15:39:19 -070054config NO_IOPORT_MAP
Jonas Bonnf8c4a272011-06-04 21:52:05 +030055 def_bool y
56
Jonas Bonnf8c4a272011-06-04 21:52:05 +030057config TRACE_IRQFLAGS_SUPPORT
58 def_bool y
59
60# For now, use generic checksum functions
61#These can be reimplemented in assembly later if so inclined
62config GENERIC_CSUM
63 def_bool y
64
Stafford Horneeecac382017-07-24 21:44:35 +090065config STACKTRACE_SUPPORT
66 def_bool y
67
Stafford Horne78cdfb52017-07-24 21:55:16 +090068config LOCKDEP_SUPPORT
69 def_bool y
70
Jonas Bonnf8c4a272011-06-04 21:52:05 +030071source "init/Kconfig"
72
Chen Gang57a1a192013-08-13 16:01:02 -070073source "kernel/Kconfig.freezer"
Jonas Bonnf8c4a272011-06-04 21:52:05 +030074
75menu "Processor type and features"
76
77choice
78 prompt "Subarchitecture"
79 default OR1K_1200
80
81config OR1K_1200
82 bool "OR1200"
83 help
84 Generic OpenRISC 1200 architecture
85
86endchoice
87
Jan Henrik Weinstock4ee93d82015-11-04 17:26:10 +010088config DCACHE_WRITETHROUGH
89 bool "Have write through data caches"
90 default n
91 help
92 Select this if your implementation features write through data caches.
93 Selecting 'N' here will allow the kernel to force flushing of data
94 caches at relevant times. Most OpenRISC implementations support write-
95 through data caches.
96
97 If unsure say N here
98
Jonas Bonnf8c4a272011-06-04 21:52:05 +030099config OPENRISC_BUILTIN_DTB
100 string "Builtin DTB"
101 default ""
102
103menu "Class II Instructions"
104
105config OPENRISC_HAVE_INST_FF1
106 bool "Have instruction l.ff1"
107 default y
108 help
109 Select this if your implementation has the Class II instruction l.ff1
110
111config OPENRISC_HAVE_INST_FL1
112 bool "Have instruction l.fl1"
113 default y
114 help
115 Select this if your implementation has the Class II instruction l.fl1
116
117config OPENRISC_HAVE_INST_MUL
118 bool "Have instruction l.mul for hardware multiply"
119 default y
120 help
121 Select this if your implementation has a hardware multiply instruction
122
123config OPENRISC_HAVE_INST_DIV
124 bool "Have instruction l.div for hardware divide"
125 default y
126 help
127 Select this if your implementation has a hardware divide instruction
128endmenu
129
Stafford Horne34bbdcd2016-09-24 22:20:42 +0900130config NR_CPUS
Stefan Kristiansson8e6d08e2014-05-11 21:49:34 +0300131 int "Maximum number of CPUs (2-32)"
132 range 2 32
133 depends on SMP
134 default "2"
135
136config SMP
137 bool "Symmetric Multi-Processing support"
138 help
139 This enables support for systems with more than one CPU. If you have
140 a system with only one CPU, say N. If you have a system with more
141 than one CPU, say Y.
142
143 If you don't know what to do here, say N.
Jonas Bonnf8c4a272011-06-04 21:52:05 +0300144
Jonas Bonnf8c4a272011-06-04 21:52:05 +0300145source kernel/Kconfig.hz
146source kernel/Kconfig.preempt
147source "mm/Kconfig"
148
149config OPENRISC_NO_SPR_SR_DSX
150 bool "use SPR_SR_DSX software emulation" if OR1K_1200
151 default y
152 help
153 SPR_SR_DSX bit is status register bit indicating whether
154 the last exception has happened in delay slot.
155
156 OpenRISC architecture makes it optional to have it implemented
157 in hardware and the OR1200 does not have it.
158
159 Say N here if you know that your OpenRISC processor has
160 SPR_SR_DSX bit implemented. Say Y if you are unsure.
161
Stefan Kristiansson91993c82014-05-11 12:08:37 +0300162config OPENRISC_HAVE_SHADOW_GPRS
163 bool "Support for shadow gpr files" if !SMP
164 default y if SMP
165 help
166 Say Y here if your OpenRISC processor features shadowed
167 register files. They will in such case be used as a
168 scratch reg storage on exception entry.
169
170 On SMP systems, this feature is mandatory.
171 On a unicore system it's safe to say N here if you are unsure.
172
Jonas Bonnf8c4a272011-06-04 21:52:05 +0300173config CMDLINE
174 string "Default kernel command string"
175 default ""
176 help
177 On some architectures there is currently no way for the boot loader
178 to pass arguments to the kernel. For these architectures, you should
179 supply some command-line options at build time by entering them
180 here.
181
182menu "Debugging options"
183
Jonas Bonnf8c4a272011-06-04 21:52:05 +0300184config JUMP_UPON_UNHANDLED_EXCEPTION
185 bool "Try to die gracefully"
186 default y
187 help
188 Now this puts kernel into infinite loop after first oops. Till
189 your kernel crashes this doesn't have any influence.
190
191 Say Y if you are unsure.
192
Jonas Bonnf8c4a272011-06-04 21:52:05 +0300193config OPENRISC_ESR_EXCEPTION_BUG_CHECK
194 bool "Check for possible ESR exception bug"
195 default n
196 help
197 This option enables some checks that might expose some problems
198 in kernel.
199
200 Say N if you are unsure.
201
202endmenu
203
204endmenu
205
206menu "Executable file formats"
207
208source "fs/Kconfig.binfmt"
209
210endmenu
211
212source "net/Kconfig"
213
214source "drivers/Kconfig"
215
216source "fs/Kconfig"
217
218source "security/Kconfig"
219
220source "crypto/Kconfig"
221
222source "lib/Kconfig"
223
224menu "Kernel hacking"
225
226source "lib/Kconfig.debug"
227
228endmenu