Gitiles
Code Review Sign In
gerrit-public.fairphone.software / kernel / msm-4.19 / 4adb123d335ecfc0da304585b3b5a4582f9db5dd / . / arch / arm / boot / dts / tegra114-dalmore.dts
blob: a95a75145a963930fb30109455f9217e5f28f813 [file] [log] [blame]
Stephen Warren76af3462014-01-06 12:15:49 -0700[diff] [blame]1/*
2 * This dts file supports Dalmore A04.
3 * Other board revisions are not supported
4 */
5
Hiroshi Doyua71c03e2013-01-24 01:10:24 +0000[diff] [blame]6/dts-v1/;
7
Laxman Dewangane6e646e2013-09-18 18:52:32 +0530[diff] [blame]8#include <dt-bindings/input/input.h>
Stephen Warren1bd0bd42012-10-17 16:38:21 -0600[diff] [blame]9#include "tegra114.dtsi"
Hiroshi Doyua71c03e2013-01-24 01:10:24 +0000[diff] [blame]10
11/ {
12 model = "NVIDIA Tegra114 Dalmore evaluation board";
13 compatible = "nvidia,dalmore", "nvidia,tegra114";
14
Stephen Warren553c0a22013-12-09 14:43:59 -0700[diff] [blame]15 aliases {
16 rtc0 = "/i2c@7000d000/tps65913@58";
17 rtc1 = "/rtc@7000e000";
18 };
19
Hiroshi Doyua71c03e2013-01-24 01:10:24 +0000[diff] [blame]20 memory {
21 reg = <0x80000000 0x40000000>;
22 };
23
Thierry Reding48b90112013-12-19 16:59:32 +0100[diff] [blame]24 host1x@50000000 {
Mikko Perttunenf044d6f2013-12-19 16:59:33 +0100[diff] [blame]25 hdmi@54280000 {
26 status = "okay";
27
Thierry Reding4adb1232014-04-25 17:44:50 +0200[diff] [blame^]28 hdmi-supply = <&vdd_5v0_hdmi>;
Mikko Perttunenf044d6f2013-12-19 16:59:33 +0100[diff] [blame]29 vdd-supply = <&vdd_hdmi_reg>;
30 pll-supply = <&palmas_smps3_reg>;
31
32 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
33 nvidia,hpd-gpio =
34 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
35 };
36
Thierry Reding48b90112013-12-19 16:59:32 +0100[diff] [blame]37 dsi@54300000 {
38 status = "okay";
39
40 panel@0 {
41 compatible = "panasonic,vvx10f004b00",
42 "simple-panel";
43 reg = <0>;
44
45 power-supply = <&avdd_lcd_reg>;
46 backlight = <&backlight>;
47 };
48 };
49 };
50
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]51 pinmux@70000868 {
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]52 pinctrl-names = "default";
53 pinctrl-0 = <&state_default>;
54
55 state_default: pinmux {
56 clk1_out_pw4 {
57 nvidia,pins = "clk1_out_pw4";
58 nvidia,function = "extperiph1";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]59 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
60 nvidia,tristate = <TEGRA_PIN_DISABLE>;
61 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]62 };
63 dap1_din_pn1 {
64 nvidia,pins = "dap1_din_pn1";
65 nvidia,function = "i2s0";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]66 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
67 nvidia,tristate = <TEGRA_PIN_ENABLE>;
68 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]69 };
70 dap1_dout_pn2 {
71 nvidia,pins = "dap1_dout_pn2",
72 "dap1_fs_pn0",
73 "dap1_sclk_pn3";
74 nvidia,function = "i2s0";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]75 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
76 nvidia,tristate = <TEGRA_PIN_DISABLE>;
77 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]78 };
79 dap2_din_pa4 {
80 nvidia,pins = "dap2_din_pa4";
81 nvidia,function = "i2s1";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]82 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
83 nvidia,tristate = <TEGRA_PIN_ENABLE>;
84 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]85 };
86 dap2_dout_pa5 {
87 nvidia,pins = "dap2_dout_pa5",
88 "dap2_fs_pa2",
89 "dap2_sclk_pa3";
90 nvidia,function = "i2s1";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]91 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
92 nvidia,tristate = <TEGRA_PIN_DISABLE>;
93 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]94 };
95 dap4_din_pp5 {
96 nvidia,pins = "dap4_din_pp5",
97 "dap4_dout_pp6",
98 "dap4_fs_pp4",
99 "dap4_sclk_pp7";
100 nvidia,function = "i2s3";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]101 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
102 nvidia,tristate = <TEGRA_PIN_DISABLE>;
103 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]104 };
105 dvfs_pwm_px0 {
106 nvidia,pins = "dvfs_pwm_px0",
107 "dvfs_clk_px2";
108 nvidia,function = "cldvfs";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]109 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
110 nvidia,tristate = <TEGRA_PIN_DISABLE>;
111 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]112 };
113 ulpi_clk_py0 {
114 nvidia,pins = "ulpi_clk_py0",
115 "ulpi_data0_po1",
116 "ulpi_data1_po2",
117 "ulpi_data2_po3",
118 "ulpi_data3_po4",
119 "ulpi_data4_po5",
120 "ulpi_data5_po6",
121 "ulpi_data6_po7",
122 "ulpi_data7_po0";
123 nvidia,function = "ulpi";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]124 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
125 nvidia,tristate = <TEGRA_PIN_DISABLE>;
126 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]127 };
128 ulpi_dir_py1 {
129 nvidia,pins = "ulpi_dir_py1",
130 "ulpi_nxt_py2";
131 nvidia,function = "ulpi";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]132 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
133 nvidia,tristate = <TEGRA_PIN_ENABLE>;
134 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]135 };
136 ulpi_stp_py3 {
137 nvidia,pins = "ulpi_stp_py3";
138 nvidia,function = "ulpi";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]139 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
140 nvidia,tristate = <TEGRA_PIN_DISABLE>;
141 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]142 };
143 cam_i2c_scl_pbb1 {
144 nvidia,pins = "cam_i2c_scl_pbb1",
145 "cam_i2c_sda_pbb2";
146 nvidia,function = "i2c3";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]147 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
148 nvidia,tristate = <TEGRA_PIN_DISABLE>;
149 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
150 nvidia,lock = <TEGRA_PIN_DISABLE>;
151 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]152 };
153 cam_mclk_pcc0 {
154 nvidia,pins = "cam_mclk_pcc0",
155 "pbb0";
156 nvidia,function = "vi_alt3";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]157 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
158 nvidia,tristate = <TEGRA_PIN_DISABLE>;
159 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
160 nvidia,lock = <TEGRA_PIN_DISABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]161 };
162 gen2_i2c_scl_pt5 {
163 nvidia,pins = "gen2_i2c_scl_pt5",
164 "gen2_i2c_sda_pt6";
165 nvidia,function = "i2c2";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]166 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
167 nvidia,tristate = <TEGRA_PIN_DISABLE>;
168 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
169 nvidia,lock = <TEGRA_PIN_DISABLE>;
170 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]171 };
172 gmi_a16_pj7 {
173 nvidia,pins = "gmi_a16_pj7";
174 nvidia,function = "uartd";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]175 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
176 nvidia,tristate = <TEGRA_PIN_DISABLE>;
177 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]178 };
179 gmi_a17_pb0 {
180 nvidia,pins = "gmi_a17_pb0",
181 "gmi_a18_pb1";
182 nvidia,function = "uartd";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]183 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
184 nvidia,tristate = <TEGRA_PIN_ENABLE>;
185 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]186 };
187 gmi_a19_pk7 {
188 nvidia,pins = "gmi_a19_pk7";
189 nvidia,function = "uartd";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]190 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
191 nvidia,tristate = <TEGRA_PIN_DISABLE>;
192 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]193 };
194 gmi_ad5_pg5 {
195 nvidia,pins = "gmi_ad5_pg5",
196 "gmi_cs6_n_pi3",
197 "gmi_wr_n_pi0";
198 nvidia,function = "spi4";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]199 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
200 nvidia,tristate = <TEGRA_PIN_DISABLE>;
201 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]202 };
203 gmi_ad6_pg6 {
204 nvidia,pins = "gmi_ad6_pg6",
205 "gmi_ad7_pg7";
206 nvidia,function = "spi4";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]207 nvidia,pull = <TEGRA_PIN_PULL_UP>;
208 nvidia,tristate = <TEGRA_PIN_DISABLE>;
209 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]210 };
211 gmi_ad12_ph4 {
212 nvidia,pins = "gmi_ad12_ph4";
213 nvidia,function = "rsvd4";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]214 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
215 nvidia,tristate = <TEGRA_PIN_DISABLE>;
216 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]217 };
218 gmi_ad9_ph1 {
219 nvidia,pins = "gmi_ad9_ph1";
220 nvidia,function = "pwm1";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]221 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
222 nvidia,tristate = <TEGRA_PIN_DISABLE>;
223 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]224 };
225 gmi_cs1_n_pj2 {
226 nvidia,pins = "gmi_cs1_n_pj2",
227 "gmi_oe_n_pi1";
228 nvidia,function = "soc";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]229 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
230 nvidia,tristate = <TEGRA_PIN_ENABLE>;
231 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]232 };
233 clk2_out_pw5 {
234 nvidia,pins = "clk2_out_pw5";
235 nvidia,function = "extperiph2";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]236 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
237 nvidia,tristate = <TEGRA_PIN_DISABLE>;
238 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]239 };
240 sdmmc1_clk_pz0 {
241 nvidia,pins = "sdmmc1_clk_pz0";
242 nvidia,function = "sdmmc1";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]243 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
244 nvidia,tristate = <TEGRA_PIN_DISABLE>;
245 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]246 };
247 sdmmc1_cmd_pz1 {
248 nvidia,pins = "sdmmc1_cmd_pz1",
249 "sdmmc1_dat0_py7",
250 "sdmmc1_dat1_py6",
251 "sdmmc1_dat2_py5",
252 "sdmmc1_dat3_py4";
253 nvidia,function = "sdmmc1";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]254 nvidia,pull = <TEGRA_PIN_PULL_UP>;
255 nvidia,tristate = <TEGRA_PIN_DISABLE>;
256 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]257 };
258 sdmmc1_wp_n_pv3 {
259 nvidia,pins = "sdmmc1_wp_n_pv3";
260 nvidia,function = "spi4";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]261 nvidia,pull = <TEGRA_PIN_PULL_UP>;
262 nvidia,tristate = <TEGRA_PIN_DISABLE>;
263 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]264 };
265 sdmmc3_clk_pa6 {
266 nvidia,pins = "sdmmc3_clk_pa6";
267 nvidia,function = "sdmmc3";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]268 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
269 nvidia,tristate = <TEGRA_PIN_DISABLE>;
270 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]271 };
272 sdmmc3_cmd_pa7 {
273 nvidia,pins = "sdmmc3_cmd_pa7",
274 "sdmmc3_dat0_pb7",
275 "sdmmc3_dat1_pb6",
276 "sdmmc3_dat2_pb5",
277 "sdmmc3_dat3_pb4",
278 "kb_col4_pq4",
279 "sdmmc3_clk_lb_out_pee4",
280 "sdmmc3_clk_lb_in_pee5";
281 nvidia,function = "sdmmc3";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]282 nvidia,pull = <TEGRA_PIN_PULL_UP>;
283 nvidia,tristate = <TEGRA_PIN_DISABLE>;
284 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]285 };
286 sdmmc4_clk_pcc4 {
287 nvidia,pins = "sdmmc4_clk_pcc4";
288 nvidia,function = "sdmmc4";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]289 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
290 nvidia,tristate = <TEGRA_PIN_DISABLE>;
291 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]292 };
293 sdmmc4_cmd_pt7 {
294 nvidia,pins = "sdmmc4_cmd_pt7",
295 "sdmmc4_dat0_paa0",
296 "sdmmc4_dat1_paa1",
297 "sdmmc4_dat2_paa2",
298 "sdmmc4_dat3_paa3",
299 "sdmmc4_dat4_paa4",
300 "sdmmc4_dat5_paa5",
301 "sdmmc4_dat6_paa6",
302 "sdmmc4_dat7_paa7";
303 nvidia,function = "sdmmc4";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]304 nvidia,pull = <TEGRA_PIN_PULL_UP>;
305 nvidia,tristate = <TEGRA_PIN_DISABLE>;
306 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]307 };
308 clk_32k_out_pa0 {
309 nvidia,pins = "clk_32k_out_pa0";
310 nvidia,function = "blink";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]311 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
312 nvidia,tristate = <TEGRA_PIN_DISABLE>;
313 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]314 };
315 kb_col0_pq0 {
316 nvidia,pins = "kb_col0_pq0",
317 "kb_col1_pq1",
318 "kb_col2_pq2",
319 "kb_row0_pr0",
320 "kb_row1_pr1",
321 "kb_row2_pr2";
322 nvidia,function = "kbc";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]323 nvidia,pull = <TEGRA_PIN_PULL_UP>;
324 nvidia,tristate = <TEGRA_PIN_DISABLE>;
325 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]326 };
327 dap3_din_pp1 {
328 nvidia,pins = "dap3_din_pp1",
329 "dap3_sclk_pp3";
330 nvidia,function = "displayb";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]331 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
332 nvidia,tristate = <TEGRA_PIN_ENABLE>;
333 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]334 };
335 pv0 {
336 nvidia,pins = "pv0";
337 nvidia,function = "rsvd4";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]338 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
339 nvidia,tristate = <TEGRA_PIN_ENABLE>;
340 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]341 };
342 kb_row7_pr7 {
343 nvidia,pins = "kb_row7_pr7";
344 nvidia,function = "rsvd2";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]345 nvidia,pull = <TEGRA_PIN_PULL_UP>;
346 nvidia,tristate = <TEGRA_PIN_DISABLE>;
347 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]348 };
349 kb_row10_ps2 {
350 nvidia,pins = "kb_row10_ps2";
351 nvidia,function = "uarta";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]352 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
353 nvidia,tristate = <TEGRA_PIN_ENABLE>;
354 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]355 };
356 kb_row9_ps1 {
357 nvidia,pins = "kb_row9_ps1";
358 nvidia,function = "uarta";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]359 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
360 nvidia,tristate = <TEGRA_PIN_DISABLE>;
361 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]362 };
363 pwr_i2c_scl_pz6 {
364 nvidia,pins = "pwr_i2c_scl_pz6",
365 "pwr_i2c_sda_pz7";
366 nvidia,function = "i2cpwr";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]367 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
368 nvidia,tristate = <TEGRA_PIN_DISABLE>;
369 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
370 nvidia,lock = <TEGRA_PIN_DISABLE>;
371 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]372 };
373 sys_clk_req_pz5 {
374 nvidia,pins = "sys_clk_req_pz5";
375 nvidia,function = "sysclk";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]376 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
377 nvidia,tristate = <TEGRA_PIN_DISABLE>;
378 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]379 };
380 core_pwr_req {
381 nvidia,pins = "core_pwr_req";
382 nvidia,function = "pwron";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]383 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
384 nvidia,tristate = <TEGRA_PIN_DISABLE>;
385 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]386 };
387 cpu_pwr_req {
388 nvidia,pins = "cpu_pwr_req";
389 nvidia,function = "cpu";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]390 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
391 nvidia,tristate = <TEGRA_PIN_DISABLE>;
392 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]393 };
394 pwr_int_n {
395 nvidia,pins = "pwr_int_n";
396 nvidia,function = "pmi";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]397 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
398 nvidia,tristate = <TEGRA_PIN_ENABLE>;
399 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]400 };
401 reset_out_n {
402 nvidia,pins = "reset_out_n";
403 nvidia,function = "reset_out_n";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]404 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
405 nvidia,tristate = <TEGRA_PIN_DISABLE>;
406 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]407 };
408 clk3_out_pee0 {
409 nvidia,pins = "clk3_out_pee0";
410 nvidia,function = "extperiph3";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]411 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
412 nvidia,tristate = <TEGRA_PIN_DISABLE>;
413 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]414 };
415 gen1_i2c_scl_pc4 {
416 nvidia,pins = "gen1_i2c_scl_pc4",
417 "gen1_i2c_sda_pc5";
418 nvidia,function = "i2c1";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]419 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
420 nvidia,tristate = <TEGRA_PIN_DISABLE>;
421 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
422 nvidia,lock = <TEGRA_PIN_DISABLE>;
423 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]424 };
425 uart2_cts_n_pj5 {
426 nvidia,pins = "uart2_cts_n_pj5";
427 nvidia,function = "uartb";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]428 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
429 nvidia,tristate = <TEGRA_PIN_ENABLE>;
430 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]431 };
432 uart2_rts_n_pj6 {
433 nvidia,pins = "uart2_rts_n_pj6";
434 nvidia,function = "uartb";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]435 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
436 nvidia,tristate = <TEGRA_PIN_DISABLE>;
437 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]438 };
439 uart2_rxd_pc3 {
440 nvidia,pins = "uart2_rxd_pc3";
441 nvidia,function = "irda";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]442 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
443 nvidia,tristate = <TEGRA_PIN_ENABLE>;
444 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]445 };
446 uart2_txd_pc2 {
447 nvidia,pins = "uart2_txd_pc2";
448 nvidia,function = "irda";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]449 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
450 nvidia,tristate = <TEGRA_PIN_DISABLE>;
451 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]452 };
453 uart3_cts_n_pa1 {
454 nvidia,pins = "uart3_cts_n_pa1",
455 "uart3_rxd_pw7";
456 nvidia,function = "uartc";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]457 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
458 nvidia,tristate = <TEGRA_PIN_ENABLE>;
459 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]460 };
461 uart3_rts_n_pc0 {
462 nvidia,pins = "uart3_rts_n_pc0",
463 "uart3_txd_pw6";
464 nvidia,function = "uartc";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]465 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
466 nvidia,tristate = <TEGRA_PIN_DISABLE>;
467 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]468 };
469 owr {
470 nvidia,pins = "owr";
471 nvidia,function = "owr";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]472 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
473 nvidia,tristate = <TEGRA_PIN_DISABLE>;
474 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]475 };
476 hdmi_cec_pee3 {
477 nvidia,pins = "hdmi_cec_pee3";
478 nvidia,function = "cec";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]479 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
480 nvidia,tristate = <TEGRA_PIN_DISABLE>;
481 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
482 nvidia,lock = <TEGRA_PIN_DISABLE>;
483 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]484 };
485 ddc_scl_pv4 {
486 nvidia,pins = "ddc_scl_pv4",
487 "ddc_sda_pv5";
488 nvidia,function = "i2c4";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]489 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
490 nvidia,tristate = <TEGRA_PIN_DISABLE>;
491 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
492 nvidia,lock = <TEGRA_PIN_DISABLE>;
493 nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]494 };
495 spdif_in_pk6 {
496 nvidia,pins = "spdif_in_pk6";
497 nvidia,function = "usb";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]498 nvidia,pull = <TEGRA_PIN_PULL_UP>;
499 nvidia,tristate = <TEGRA_PIN_DISABLE>;
500 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
501 nvidia,lock = <TEGRA_PIN_DISABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]502 };
503 usb_vbus_en0_pn4 {
504 nvidia,pins = "usb_vbus_en0_pn4";
505 nvidia,function = "usb";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]506 nvidia,pull = <TEGRA_PIN_PULL_UP>;
507 nvidia,tristate = <TEGRA_PIN_DISABLE>;
508 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
509 nvidia,lock = <TEGRA_PIN_DISABLE>;
510 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]511 };
512 gpio_x6_aud_px6 {
513 nvidia,pins = "gpio_x6_aud_px6";
514 nvidia,function = "spi6";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]515 nvidia,pull = <TEGRA_PIN_PULL_UP>;
516 nvidia,tristate = <TEGRA_PIN_ENABLE>;
517 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]518 };
519 gpio_x4_aud_px4 {
520 nvidia,pins = "gpio_x4_aud_px4",
521 "gpio_x7_aud_px7";
522 nvidia,function = "rsvd1";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]523 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
524 nvidia,tristate = <TEGRA_PIN_DISABLE>;
525 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]526 };
527 gpio_x5_aud_px5 {
528 nvidia,pins = "gpio_x5_aud_px5";
529 nvidia,function = "rsvd1";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]530 nvidia,pull = <TEGRA_PIN_PULL_UP>;
531 nvidia,tristate = <TEGRA_PIN_DISABLE>;
532 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]533 };
534 gpio_w2_aud_pw2 {
535 nvidia,pins = "gpio_w2_aud_pw2";
536 nvidia,function = "rsvd2";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]537 nvidia,pull = <TEGRA_PIN_PULL_UP>;
538 nvidia,tristate = <TEGRA_PIN_DISABLE>;
539 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]540 };
541 gpio_w3_aud_pw3 {
542 nvidia,pins = "gpio_w3_aud_pw3";
543 nvidia,function = "spi6";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]544 nvidia,pull = <TEGRA_PIN_PULL_UP>;
545 nvidia,tristate = <TEGRA_PIN_DISABLE>;
546 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]547 };
548 gpio_x1_aud_px1 {
549 nvidia,pins = "gpio_x1_aud_px1";
550 nvidia,function = "rsvd4";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]551 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
552 nvidia,tristate = <TEGRA_PIN_DISABLE>;
553 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]554 };
555 gpio_x3_aud_px3 {
556 nvidia,pins = "gpio_x3_aud_px3";
557 nvidia,function = "rsvd4";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]558 nvidia,pull = <TEGRA_PIN_PULL_UP>;
559 nvidia,tristate = <TEGRA_PIN_DISABLE>;
560 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]561 };
562 dap3_fs_pp0 {
563 nvidia,pins = "dap3_fs_pp0";
564 nvidia,function = "i2s2";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]565 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
566 nvidia,tristate = <TEGRA_PIN_DISABLE>;
567 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]568 };
569 dap3_dout_pp2 {
570 nvidia,pins = "dap3_dout_pp2";
571 nvidia,function = "i2s2";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]572 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
573 nvidia,tristate = <TEGRA_PIN_DISABLE>;
574 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]575 };
576 pv1 {
577 nvidia,pins = "pv1";
578 nvidia,function = "rsvd1";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]579 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
580 nvidia,tristate = <TEGRA_PIN_DISABLE>;
581 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]582 };
583 pbb3 {
584 nvidia,pins = "pbb3",
585 "pbb5",
586 "pbb6",
587 "pbb7";
588 nvidia,function = "rsvd4";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]589 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
590 nvidia,tristate = <TEGRA_PIN_DISABLE>;
591 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]592 };
593 pcc1 {
594 nvidia,pins = "pcc1",
595 "pcc2";
596 nvidia,function = "rsvd4";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]597 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
598 nvidia,tristate = <TEGRA_PIN_DISABLE>;
599 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]600 };
601 gmi_ad0_pg0 {
602 nvidia,pins = "gmi_ad0_pg0",
603 "gmi_ad1_pg1";
604 nvidia,function = "gmi";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]605 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
606 nvidia,tristate = <TEGRA_PIN_DISABLE>;
607 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]608 };
609 gmi_ad10_ph2 {
610 nvidia,pins = "gmi_ad10_ph2",
611 "gmi_ad11_ph3",
612 "gmi_ad13_ph5",
613 "gmi_ad8_ph0",
614 "gmi_clk_pk1";
615 nvidia,function = "gmi";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]616 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
617 nvidia,tristate = <TEGRA_PIN_DISABLE>;
618 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]619 };
620 gmi_ad2_pg2 {
621 nvidia,pins = "gmi_ad2_pg2",
622 "gmi_ad3_pg3";
623 nvidia,function = "gmi";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]624 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
625 nvidia,tristate = <TEGRA_PIN_DISABLE>;
626 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]627 };
628 gmi_adv_n_pk0 {
629 nvidia,pins = "gmi_adv_n_pk0",
630 "gmi_cs0_n_pj0",
631 "gmi_cs2_n_pk3",
632 "gmi_cs4_n_pk2",
633 "gmi_cs7_n_pi6",
634 "gmi_dqs_p_pj3",
635 "gmi_iordy_pi5",
636 "gmi_wp_n_pc7";
637 nvidia,function = "gmi";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]638 nvidia,pull = <TEGRA_PIN_PULL_UP>;
639 nvidia,tristate = <TEGRA_PIN_DISABLE>;
640 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]641 };
642 gmi_cs3_n_pk4 {
643 nvidia,pins = "gmi_cs3_n_pk4";
644 nvidia,function = "gmi";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]645 nvidia,pull = <TEGRA_PIN_PULL_UP>;
646 nvidia,tristate = <TEGRA_PIN_DISABLE>;
647 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]648 };
649 clk2_req_pcc5 {
650 nvidia,pins = "clk2_req_pcc5";
651 nvidia,function = "rsvd4";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]652 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
653 nvidia,tristate = <TEGRA_PIN_DISABLE>;
654 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]655 };
656 kb_col3_pq3 {
657 nvidia,pins = "kb_col3_pq3",
658 "kb_col6_pq6",
659 "kb_col7_pq7";
660 nvidia,function = "kbc";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]661 nvidia,pull = <TEGRA_PIN_PULL_UP>;
662 nvidia,tristate = <TEGRA_PIN_DISABLE>;
663 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]664 };
665 kb_col5_pq5 {
666 nvidia,pins = "kb_col5_pq5";
667 nvidia,function = "kbc";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]668 nvidia,pull = <TEGRA_PIN_PULL_UP>;
669 nvidia,tristate = <TEGRA_PIN_DISABLE>;
670 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]671 };
672 kb_row3_pr3 {
673 nvidia,pins = "kb_row3_pr3",
674 "kb_row4_pr4",
675 "kb_row6_pr6",
676 "kb_row8_ps0";
677 nvidia,function = "kbc";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]678 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
679 nvidia,tristate = <TEGRA_PIN_DISABLE>;
680 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]681 };
682 clk3_req_pee1 {
683 nvidia,pins = "clk3_req_pee1";
684 nvidia,function = "rsvd4";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]685 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
686 nvidia,tristate = <TEGRA_PIN_DISABLE>;
687 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]688 };
689 pu4 {
690 nvidia,pins = "pu4";
691 nvidia,function = "displayb";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]692 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
693 nvidia,tristate = <TEGRA_PIN_DISABLE>;
694 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]695 };
696 pu5 {
697 nvidia,pins = "pu5",
698 "pu6";
699 nvidia,function = "displayb";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]700 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
701 nvidia,tristate = <TEGRA_PIN_DISABLE>;
702 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]703 };
704 hdmi_int_pn7 {
705 nvidia,pins = "hdmi_int_pn7";
706 nvidia,function = "rsvd1";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]707 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
708 nvidia,tristate = <TEGRA_PIN_DISABLE>;
709 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]710 };
711 clk1_req_pee2 {
712 nvidia,pins = "clk1_req_pee2",
713 "usb_vbus_en1_pn5";
714 nvidia,function = "rsvd4";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]715 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
716 nvidia,tristate = <TEGRA_PIN_ENABLE>;
717 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]718 };
719
720 drive_sdio1 {
721 nvidia,pins = "drive_sdio1";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]722 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
723 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]724 nvidia,pull-down-strength = <36>;
725 nvidia,pull-up-strength = <20>;
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]726 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>;
727 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]728 };
729 drive_sdio3 {
730 nvidia,pins = "drive_sdio3";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]731 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
732 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]733 nvidia,pull-down-strength = <22>;
734 nvidia,pull-up-strength = <36>;
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]735 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
736 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]737 };
738 drive_gma {
739 nvidia,pins = "drive_gma";
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]740 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
741 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]742 nvidia,pull-down-strength = <2>;
743 nvidia,pull-up-strength = <1>;
Laxman Dewangan5fc6b0d2013-12-05 16:14:07 +0530[diff] [blame]744 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
745 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
Pritesh Raithatha2c314d52013-02-11 12:25:13 +0000[diff] [blame]746 };
747 };
748 };
749
Hiroshi Doyua71c03e2013-01-24 01:10:24 +0000[diff] [blame]750 serial@70006300 {
751 status = "okay";
Hiroshi Doyua71c03e2013-01-24 01:10:24 +0000[diff] [blame]752 };
753
Thierry Reding48b90112013-12-19 16:59:32 +0100[diff] [blame]754 pwm@7000a000 {
755 status = "okay";
756 };
757
Rhyland Klein33eb2712013-03-20 11:31:32 -0400[diff] [blame]758 i2c@7000c000 {
759 status = "okay";
760 clock-frequency = <100000>;
761
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]762 battery: smart-battery@b {
Rhyland Klein33eb2712013-03-20 11:31:32 -0400[diff] [blame]763 compatible = "ti,bq20z45", "sbs,sbs-battery";
764 reg = <0xb>;
765 battery-name = "battery";
766 sbs,i2c-retry-count = <2>;
767 sbs,poll-retry-count = <100>;
Rhyland Kleind5284a62013-06-10 17:26:42 -0400[diff] [blame]768 power-supplies = <&charger>;
Rhyland Klein33eb2712013-03-20 11:31:32 -0400[diff] [blame]769 };
Stephen Warrenaa5ae422013-03-12 17:03:42 -0600[diff] [blame]770
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]771 rt5640: rt5640@1c {
Stephen Warrenaa5ae422013-03-12 17:03:42 -0600[diff] [blame]772 compatible = "realtek,rt5640";
773 reg = <0x1c>;
774 interrupt-parent = <&gpio>;
775 interrupts = <TEGRA_GPIO(W, 3) GPIO_ACTIVE_HIGH>;
776 realtek,ldo1-en-gpios =
777 <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
778 };
Wei Ni99bda7b2013-10-07 17:28:28 +0800[diff] [blame]779
780 temperature-sensor@4c {
781 compatible = "onnn,nct1008";
782 reg = <0x4c>;
783 vcc-supply = <&palmas_ldo6_reg>;
784 interrupt-parent = <&gpio>;
785 interrupts = <TEGRA_GPIO(O, 4) IRQ_TYPE_LEVEL_LOW>;
786 };
Rhyland Klein33eb2712013-03-20 11:31:32 -0400[diff] [blame]787 };
788
Mikko Perttunenf044d6f2013-12-19 16:59:33 +0100[diff] [blame]789 hdmi_ddc: i2c@7000c700 {
790 status = "okay";
791 };
792
Laxman Dewanganda204ee2013-03-21 19:17:40 +0530[diff] [blame]793 i2c@7000d000 {
794 status = "okay";
795 clock-frequency = <400000>;
796
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]797 tps51632@43 {
Laxman Dewanganda204ee2013-03-21 19:17:40 +0530[diff] [blame]798 compatible = "ti,tps51632";
799 reg = <0x43>;
800 regulator-name = "vdd-cpu";
801 regulator-min-microvolt = <500000>;
802 regulator-max-microvolt = <1520000>;
803 regulator-boot-on;
804 regulator-always-on;
805 };
Laxman Dewangan81c6c562013-03-21 19:17:41 +0530[diff] [blame]806
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]807 tps65090@48 {
Laxman Dewangan81c6c562013-03-21 19:17:41 +0530[diff] [blame]808 compatible = "ti,tps65090";
809 reg = <0x48>;
810 interrupt-parent = <&gpio>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700[diff] [blame]811 interrupts = <TEGRA_GPIO(J, 0) IRQ_TYPE_LEVEL_HIGH>;
Laxman Dewangan81c6c562013-03-21 19:17:41 +0530[diff] [blame]812
813 vsys1-supply = <&vdd_ac_bat_reg>;
814 vsys2-supply = <&vdd_ac_bat_reg>;
815 vsys3-supply = <&vdd_ac_bat_reg>;
816 infet1-supply = <&vdd_ac_bat_reg>;
817 infet2-supply = <&vdd_ac_bat_reg>;
818 infet3-supply = <&tps65090_dcdc2_reg>;
819 infet4-supply = <&tps65090_dcdc2_reg>;
820 infet5-supply = <&tps65090_dcdc2_reg>;
821 infet6-supply = <&tps65090_dcdc2_reg>;
822 infet7-supply = <&tps65090_dcdc2_reg>;
823 vsys-l1-supply = <&vdd_ac_bat_reg>;
824 vsys-l2-supply = <&vdd_ac_bat_reg>;
825
Rhyland Kleind5284a62013-06-10 17:26:42 -0400[diff] [blame]826 charger: charger {
Rhyland Klein1a99ece2013-04-10 09:51:45 +0000[diff] [blame]827 compatible = "ti,tps65090-charger";
828 ti,enable-low-current-chrg;
829 };
830
Laxman Dewangan81c6c562013-03-21 19:17:41 +0530[diff] [blame]831 regulators {
Laxman Dewanganfcf0b3a2013-03-21 19:17:42 +0530[diff] [blame]832 tps65090_dcdc1_reg: dcdc1 {
Laxman Dewangan81c6c562013-03-21 19:17:41 +0530[diff] [blame]833 regulator-name = "vdd-sys-5v0";
834 regulator-always-on;
835 regulator-boot-on;
836 };
837
838 tps65090_dcdc2_reg: dcdc2 {
839 regulator-name = "vdd-sys-3v3";
840 regulator-always-on;
841 regulator-boot-on;
842 };
843
Laxman Dewanganc321d962013-07-19 07:43:11 +0530[diff] [blame]844 tps65090_dcdc3_reg: dcdc3 {
Laxman Dewangan81c6c562013-03-21 19:17:41 +0530[diff] [blame]845 regulator-name = "vdd-ao";
846 regulator-always-on;
847 regulator-boot-on;
848 };
849
Thierry Reding48b90112013-12-19 16:59:32 +0100[diff] [blame]850 vdd_bl_reg: fet1 {
Laxman Dewangan81c6c562013-03-21 19:17:41 +0530[diff] [blame]851 regulator-name = "vdd-lcd-bl";
852 };
853
854 fet3 {
855 regulator-name = "vdd-modem-3v3";
856 };
857
Thierry Reding48b90112013-12-19 16:59:32 +0100[diff] [blame]858 avdd_lcd_reg: fet4 {
Laxman Dewangan81c6c562013-03-21 19:17:41 +0530[diff] [blame]859 regulator-name = "avdd-lcd";
860 };
861
862 fet5 {
863 regulator-name = "vdd-lvds";
864 };
865
866 fet6 {
867 regulator-name = "vdd-sd-slot";
Stephen Warren15d5ef42013-03-28 13:22:30 -0600[diff] [blame]868 regulator-always-on;
Laxman Dewangan81c6c562013-03-21 19:17:41 +0530[diff] [blame]869 regulator-boot-on;
870 };
871
872 fet7 {
873 regulator-name = "vdd-com-3v3";
874 };
875
876 ldo1 {
877 regulator-name = "vdd-sby-5v0";
878 regulator-always-on;
879 regulator-boot-on;
880 };
881
882 ldo2 {
883 regulator-name = "vdd-sby-3v3";
884 regulator-always-on;
885 regulator-boot-on;
886 };
887 };
888 };
Laxman Dewanganc321d962013-07-19 07:43:11 +0530[diff] [blame]889
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]890 palmas: tps65913@58 {
Laxman Dewanganc321d962013-07-19 07:43:11 +0530[diff] [blame]891 compatible = "ti,palmas";
892 reg = <0x58>;
Joseph Loeca8f982013-08-01 17:37:45 +0800[diff] [blame]893 interrupts = <0 86 IRQ_TYPE_LEVEL_LOW>;
Laxman Dewanganc321d962013-07-19 07:43:11 +0530[diff] [blame]894
895 #interrupt-cells = <2>;
896 interrupt-controller;
897
Bill Huang27cf5d12013-08-19 10:44:10 -0600[diff] [blame]898 ti,system-power-controller;
899
Laxman Dewanganc321d962013-07-19 07:43:11 +0530[diff] [blame]900 palmas_gpio: gpio {
901 compatible = "ti,palmas-gpio";
902 gpio-controller;
903 #gpio-cells = <2>;
904 };
905
906 pmic {
907 compatible = "ti,tps65913-pmic", "ti,palmas-pmic";
908 smps1-in-supply = <&tps65090_dcdc3_reg>;
909 smps3-in-supply = <&tps65090_dcdc3_reg>;
910 smps4-in-supply = <&tps65090_dcdc2_reg>;
911 smps7-in-supply = <&tps65090_dcdc2_reg>;
912 smps8-in-supply = <&tps65090_dcdc2_reg>;
913 smps9-in-supply = <&tps65090_dcdc2_reg>;
914 ldo1-in-supply = <&tps65090_dcdc2_reg>;
915 ldo2-in-supply = <&tps65090_dcdc2_reg>;
916 ldo3-in-supply = <&palmas_smps3_reg>;
917 ldo4-in-supply = <&tps65090_dcdc2_reg>;
918 ldo5-in-supply = <&vdd_ac_bat_reg>;
919 ldo6-in-supply = <&tps65090_dcdc2_reg>;
920 ldo7-in-supply = <&tps65090_dcdc2_reg>;
921 ldo8-in-supply = <&tps65090_dcdc3_reg>;
922 ldo9-in-supply = <&palmas_smps9_reg>;
923 ldoln-in-supply = <&tps65090_dcdc1_reg>;
924 ldousb-in-supply = <&tps65090_dcdc1_reg>;
925
926 regulators {
927 smps12 {
928 regulator-name = "vddio-ddr";
929 regulator-min-microvolt = <1350000>;
930 regulator-max-microvolt = <1350000>;
931 regulator-always-on;
932 regulator-boot-on;
933 };
934
935 palmas_smps3_reg: smps3 {
936 regulator-name = "vddio-1v8";
937 regulator-min-microvolt = <1800000>;
938 regulator-max-microvolt = <1800000>;
939 regulator-always-on;
940 regulator-boot-on;
941 };
942
943 smps45 {
944 regulator-name = "vdd-core";
945 regulator-min-microvolt = <900000>;
946 regulator-max-microvolt = <1400000>;
947 regulator-always-on;
948 regulator-boot-on;
949 };
950
951 smps457 {
952 regulator-name = "vdd-core";
953 regulator-min-microvolt = <900000>;
954 regulator-max-microvolt = <1400000>;
955 regulator-always-on;
956 regulator-boot-on;
957 };
958
959 smps8 {
960 regulator-name = "avdd-pll";
961 regulator-min-microvolt = <1050000>;
962 regulator-max-microvolt = <1050000>;
963 regulator-always-on;
964 regulator-boot-on;
965 };
966
967 palmas_smps9_reg: smps9 {
968 regulator-name = "sdhci-vdd-sd-slot";
969 regulator-min-microvolt = <2800000>;
970 regulator-max-microvolt = <2800000>;
971 regulator-always-on;
972 };
973
974 ldo1 {
975 regulator-name = "avdd-cam1";
976 regulator-min-microvolt = <2800000>;
977 regulator-max-microvolt = <2800000>;
978 };
979
980 ldo2 {
981 regulator-name = "avdd-cam2";
982 regulator-min-microvolt = <2800000>;
983 regulator-max-microvolt = <2800000>;
984 };
985
986 ldo3 {
987 regulator-name = "avdd-dsi-csi";
988 regulator-min-microvolt = <1200000>;
989 regulator-max-microvolt = <1200000>;
990 regulator-always-on;
991 regulator-boot-on;
992 };
993
994 ldo4 {
995 regulator-name = "vpp-fuse";
996 regulator-min-microvolt = <1800000>;
997 regulator-max-microvolt = <1800000>;
998 };
999
Wei Ni99bda7b2013-10-07 17:28:28 +0800[diff] [blame]1000 palmas_ldo6_reg: ldo6 {
Laxman Dewanganc321d962013-07-19 07:43:11 +0530[diff] [blame]1001 regulator-name = "vdd-sensor-2v85";
1002 regulator-min-microvolt = <2850000>;
1003 regulator-max-microvolt = <2850000>;
1004 };
1005
1006 ldo7 {
1007 regulator-name = "vdd-af-cam1";
1008 regulator-min-microvolt = <2800000>;
1009 regulator-max-microvolt = <2800000>;
1010 };
1011
1012 ldo8 {
1013 regulator-name = "vdd-rtc";
1014 regulator-min-microvolt = <900000>;
1015 regulator-max-microvolt = <900000>;
1016 regulator-always-on;
1017 regulator-boot-on;
1018 ti,enable-ldo8-tracking;
1019 };
1020
1021 ldo9 {
1022 regulator-name = "vddio-sdmmc-2";
1023 regulator-min-microvolt = <1800000>;
1024 regulator-max-microvolt = <3300000>;
1025 regulator-always-on;
1026 regulator-boot-on;
1027 };
1028
1029 ldoln {
1030 regulator-name = "hvdd-usb";
1031 regulator-min-microvolt = <3300000>;
1032 regulator-max-microvolt = <3300000>;
1033 };
1034
1035 ldousb {
1036 regulator-name = "avdd-usb";
1037 regulator-min-microvolt = <3300000>;
1038 regulator-max-microvolt = <3300000>;
1039 regulator-always-on;
1040 regulator-boot-on;
1041 };
1042
1043 regen1 {
1044 regulator-name = "rail-3v3";
1045 regulator-max-microvolt = <3300000>;
1046 regulator-always-on;
1047 regulator-boot-on;
1048 };
1049
1050 regen2 {
1051 regulator-name = "rail-5v0";
1052 regulator-max-microvolt = <5000000>;
1053 regulator-always-on;
1054 regulator-boot-on;
1055 };
1056 };
1057 };
1058
1059 rtc {
1060 compatible = "ti,palmas-rtc";
1061 interrupt-parent = <&palmas>;
1062 interrupts = <8 0>;
1063 };
Laxman Dewangan6be3cf72013-09-18 18:37:22 +0530[diff] [blame]1064
1065 pinmux {
1066 compatible = "ti,tps65913-pinctrl";
1067 pinctrl-names = "default";
1068 pinctrl-0 = <&palmas_default>;
1069
1070 palmas_default: pinmux {
1071 pin_gpio6 {
1072 pins = "gpio6";
1073 function = "gpio";
1074 };
1075 };
1076 };
Laxman Dewanganc321d962013-07-19 07:43:11 +0530[diff] [blame]1077 };
Laxman Dewanganda204ee2013-03-21 19:17:40 +0530[diff] [blame]1078 };
1079
Laxman Dewangan5cc75fc2013-05-17 17:03:28 -0600[diff] [blame]1080 spi@7000da00 {
1081 status = "okay";
1082 spi-max-frequency = <25000000>;
1083 spi-flash@0 {
1084 compatible = "winbond,w25q32dw";
1085 reg = <0>;
1086 spi-max-frequency = <20000000>;
1087 };
1088 };
1089
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]1090 pmc@7000e400 {
Hiroshi Doyua71c03e2013-01-24 01:10:24 +0000[diff] [blame]1091 nvidia,invert-interrupt;
Joseph Lo47d2d632013-08-12 17:40:07 +0800[diff] [blame]1092 nvidia,suspend-mode = <1>;
Joseph Lo4a7658f2013-07-03 17:50:47 +0800[diff] [blame]1093 nvidia,cpu-pwr-good-time = <500>;
1094 nvidia,cpu-pwr-off-time = <300>;
1095 nvidia,core-pwr-good-time = <641 3845>;
1096 nvidia,core-pwr-off-time = <61036>;
1097 nvidia,core-power-req-active-high;
1098 nvidia,sys-clock-req-active-high;
Hiroshi Doyua71c03e2013-01-24 01:10:24 +0000[diff] [blame]1099 };
Joseph Lo7021d122013-04-03 19:31:27 +0800[diff] [blame]1100
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]1101 ahub@70080000 {
Stephen Warrenaa5ae422013-03-12 17:03:42 -0600[diff] [blame]1102 i2s@70080400 {
1103 status = "okay";
1104 };
1105 };
1106
Rhyland Klein8d3207c2013-02-20 13:35:15 -0500[diff] [blame]1107 sdhci@78000400 {
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]1108 cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
Rhyland Klein8d3207c2013-02-20 13:35:15 -0500[diff] [blame]1109 bus-width = <4>;
1110 status = "okay";
1111 };
1112
1113 sdhci@78000600 {
1114 bus-width = <8>;
1115 status = "okay";
Joseph Lo7a2617a2013-04-03 14:34:39 -0600[diff] [blame]1116 non-removable;
Rhyland Klein8d3207c2013-02-20 13:35:15 -0500[diff] [blame]1117 };
1118
Mikko Perttunen328dc0e2013-08-01 18:00:18 +0300[diff] [blame]1119 usb@7d008000 {
1120 status = "okay";
1121 };
1122
1123 usb-phy@7d008000 {
1124 status = "okay";
1125 vbus-supply = <&usb3_vbus_reg>;
1126 };
1127
Thierry Reding48b90112013-12-19 16:59:32 +0100[diff] [blame]1128 backlight: backlight {
1129 compatible = "pwm-backlight";
1130
1131 enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
1132 power-supply = <&vdd_bl_reg>;
1133 pwms = <&pwm 1 1000000>;
1134
1135 brightness-levels = <0 4 8 16 32 64 128 255>;
1136 default-brightness-level = <6>;
1137 };
1138
Joseph Lo7021d122013-04-03 19:31:27 +0800[diff] [blame]1139 clocks {
1140 compatible = "simple-bus";
1141 #address-cells = <1>;
1142 #size-cells = <0>;
1143
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]1144 clk32k_in: clock@0 {
Joseph Lo7021d122013-04-03 19:31:27 +0800[diff] [blame]1145 compatible = "fixed-clock";
1146 reg=<0>;
1147 #clock-cells = <0>;
1148 clock-frequency = <32768>;
1149 };
1150 };
Laxman Dewangan81c6c562013-03-21 19:17:41 +0530[diff] [blame]1151
Laxman Dewangan21b341c2013-07-10 12:30:43 +0530[diff] [blame]1152 gpio-keys {
1153 compatible = "gpio-keys";
1154
1155 home {
1156 label = "Home";
1157 gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
Laxman Dewangane6e646e2013-09-18 18:52:32 +0530[diff] [blame]1158 linux,code = <KEY_HOME>;
Laxman Dewangan21b341c2013-07-10 12:30:43 +0530[diff] [blame]1159 };
1160
1161 power {
1162 label = "Power";
1163 gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
Laxman Dewangane6e646e2013-09-18 18:52:32 +0530[diff] [blame]1164 linux,code = <KEY_POWER>;
Laxman Dewangan21b341c2013-07-10 12:30:43 +0530[diff] [blame]1165 gpio-key,wakeup;
1166 };
1167
1168 volume_down {
1169 label = "Volume Down";
1170 gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>;
Laxman Dewangane6e646e2013-09-18 18:52:32 +0530[diff] [blame]1171 linux,code = <KEY_VOLUMEDOWN>;
Laxman Dewangan21b341c2013-07-10 12:30:43 +0530[diff] [blame]1172 };
1173
1174 volume_up {
1175 label = "Volume Up";
1176 gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>;
Laxman Dewangane6e646e2013-09-18 18:52:32 +0530[diff] [blame]1177 linux,code = <KEY_VOLUMEUP>;
Laxman Dewangan21b341c2013-07-10 12:30:43 +0530[diff] [blame]1178 };
1179 };
1180
Laxman Dewangan81c6c562013-03-21 19:17:41 +0530[diff] [blame]1181 regulators {
1182 compatible = "simple-bus";
1183 #address-cells = <1>;
1184 #size-cells = <0>;
1185
1186 vdd_ac_bat_reg: regulator@0 {
1187 compatible = "regulator-fixed";
1188 reg = <0>;
1189 regulator-name = "vdd_ac_bat";
1190 regulator-min-microvolt = <5000000>;
1191 regulator-max-microvolt = <5000000>;
1192 regulator-always-on;
1193 };
Laxman Dewanganfcf0b3a2013-03-21 19:17:42 +0530[diff] [blame]1194
1195 dvdd_ts_reg: regulator@1 {
1196 compatible = "regulator-fixed";
1197 reg = <1>;
1198 regulator-name = "dvdd_ts";
1199 regulator-min-microvolt = <1800000>;
1200 regulator-max-microvolt = <1800000>;
1201 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]1202 gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfcf0b3a2013-03-21 19:17:42 +0530[diff] [blame]1203 };
1204
Laxman Dewanganfcf0b3a2013-03-21 19:17:42 +0530[diff] [blame]1205 usb1_vbus_reg: regulator@3 {
1206 compatible = "regulator-fixed";
1207 reg = <3>;
1208 regulator-name = "usb1_vbus";
1209 regulator-min-microvolt = <5000000>;
1210 regulator-max-microvolt = <5000000>;
1211 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]1212 gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfcf0b3a2013-03-21 19:17:42 +0530[diff] [blame]1213 gpio-open-drain;
1214 vin-supply = <&tps65090_dcdc1_reg>;
1215 };
1216
1217 usb3_vbus_reg: regulator@4 {
1218 compatible = "regulator-fixed";
1219 reg = <4>;
1220 regulator-name = "usb2_vbus";
1221 regulator-min-microvolt = <5000000>;
1222 regulator-max-microvolt = <5000000>;
1223 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]1224 gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfcf0b3a2013-03-21 19:17:42 +0530[diff] [blame]1225 gpio-open-drain;
1226 vin-supply = <&tps65090_dcdc1_reg>;
1227 };
1228
1229 vdd_hdmi_reg: regulator@5 {
1230 compatible = "regulator-fixed";
1231 reg = <5>;
1232 regulator-name = "vdd_hdmi_5v0";
1233 regulator-min-microvolt = <5000000>;
1234 regulator-max-microvolt = <5000000>;
Laxman Dewanganfcf0b3a2013-03-21 19:17:42 +0530[diff] [blame]1235 vin-supply = <&tps65090_dcdc1_reg>;
1236 };
Laxman Dewanganc321d962013-07-19 07:43:11 +0530[diff] [blame]1237
1238 vdd_cam_1v8_reg: regulator@6 {
1239 compatible = "regulator-fixed";
1240 reg = <6>;
1241 regulator-name = "vdd_cam_1v8_reg";
1242 regulator-min-microvolt = <1800000>;
1243 regulator-max-microvolt = <1800000>;
1244 enable-active-high;
1245 gpio = <&palmas_gpio 6 0>;
1246 };
Thierry Reding4adb1232014-04-25 17:44:50 +0200[diff] [blame^]1247
1248 vdd_5v0_hdmi: regulator@7 {
1249 compatible = "regulator-fixed";
1250 reg = <7>;
1251 regulator-name = "VDD_5V0_HDMI_CON";
1252 regulator-min-microvolt = <5000000>;
1253 regulator-max-microvolt = <5000000>;
1254 gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
1255 enable-active-high;
1256 vin-supply = <&tps65090_dcdc1_reg>;
1257 };
Laxman Dewangan81c6c562013-03-21 19:17:41 +0530[diff] [blame]1258 };
Stephen Warrenaa5ae422013-03-12 17:03:42 -0600[diff] [blame]1259
1260 sound {
1261 compatible = "nvidia,tegra-audio-rt5640-dalmore",
1262 "nvidia,tegra-audio-rt5640";
1263 nvidia,model = "NVIDIA Tegra Dalmore";
1264
1265 nvidia,audio-routing =
1266 "Headphones", "HPOR",
1267 "Headphones", "HPOL",
1268 "Speakers", "SPORP",
1269 "Speakers", "SPORN",
1270 "Speakers", "SPOLP",
Stephen Warren8af3bbe2013-08-14 14:22:19 -0600[diff] [blame]1271 "Speakers", "SPOLN",
1272 "Mic Jack", "MICBIAS1",
1273 "IN2P", "Mic Jack";
Stephen Warrenaa5ae422013-03-12 17:03:42 -0600[diff] [blame]1274
1275 nvidia,i2s-controller = <&tegra_i2s1>;
1276 nvidia,audio-codec = <&rt5640>;
1277
1278 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
1279
1280 clocks = <&tegra_car TEGRA114_CLK_PLL_A>,
1281 <&tegra_car TEGRA114_CLK_PLL_A_OUT0>,
1282 <&tegra_car TEGRA114_CLK_EXTERN1>;
1283 clock-names = "pll_a", "pll_a_out0", "mclk";
1284 };
Hiroshi Doyua71c03e2013-01-24 01:10:24 +0000[diff] [blame]1285};