| Nicolin Chen | 3117bb3 | 2014-07-29 18:08:53 +0800 | [diff] [blame] | 1 | Freescale Asynchronous Sample Rate Converter (ASRC) Controller |
| 2 | |
| 3 | The Asynchronous Sample Rate Converter (ASRC) converts the sampling rate of a |
| 4 | signal associated with an input clock into a signal associated with a different |
| 5 | output clock. The driver currently works as a Front End of DPCM with other Back |
| 6 | Ends Audio controller such as ESAI, SSI and SAI. It has three pairs to support |
| 7 | three substreams within totally 10 channels. |
| 8 | |
| 9 | Required properties: |
| 10 | |
| 11 | - compatible : Contains "fsl,imx35-asrc" or "fsl,imx53-asrc". |
| 12 | |
| 13 | - reg : Offset and length of the register set for the device. |
| 14 | |
| 15 | - interrupts : Contains the spdif interrupt. |
| 16 | |
| 17 | - dmas : Generic dma devicetree binding as described in |
| 18 | Documentation/devicetree/bindings/dma/dma.txt. |
| 19 | |
| 20 | - dma-names : Contains "rxa", "rxb", "rxc", "txa", "txb" and "txc". |
| 21 | |
| 22 | - clocks : Contains an entry for each entry in clock-names. |
| 23 | |
| 24 | - clock-names : Contains the following entries |
| 25 | "mem" Peripheral access clock to access registers. |
| 26 | "ipg" Peripheral clock to driver module. |
| 27 | "asrck_<0-f>" Clock sources for input and output clock. |
| Shengjiu Wang | 13b8a97 | 2015-11-24 17:19:34 +0800 | [diff] [blame] | 28 | "spba" The spba clock is required when ASRC is placed as a |
| 29 | bus slave of the Shared Peripheral Bus and when two |
| 30 | or more bus masters (CPU, DMA or DSP) try to access |
| 31 | it. This property is optional depending on the SoC |
| 32 | design. |
| Nicolin Chen | 3117bb3 | 2014-07-29 18:08:53 +0800 | [diff] [blame] | 33 | |
| 34 | - big-endian : If this property is absent, the little endian mode |
| 35 | will be in use as default. Otherwise, the big endian |
| 36 | mode will be in use for all the device registers. |
| 37 | |
| 38 | - fsl,asrc-rate : Defines a mutual sample rate used by DPCM Back Ends. |
| 39 | |
| 40 | - fsl,asrc-width : Defines a mutual sample width used by DPCM Back Ends. |
| 41 | |
| 42 | Example: |
| 43 | |
| 44 | asrc: asrc@02034000 { |
| 45 | compatible = "fsl,imx53-asrc"; |
| 46 | reg = <0x02034000 0x4000>; |
| 47 | interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>; |
| 48 | clocks = <&clks 107>, <&clks 107>, <&clks 0>, |
| 49 | <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, |
| 50 | <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, |
| 51 | <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, |
| 52 | <&clks 107>, <&clks 0>, <&clks 0>; |
| 53 | clock-names = "mem", "ipg", "asrck0", |
| 54 | "asrck_1", "asrck_2", "asrck_3", "asrck_4", |
| 55 | "asrck_5", "asrck_6", "asrck_7", "asrck_8", |
| 56 | "asrck_9", "asrck_a", "asrck_b", "asrck_c", |
| 57 | "asrck_d", "asrck_e", "asrck_f"; |
| 58 | dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>, |
| 59 | <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>; |
| 60 | dma-names = "rxa", "rxb", "rxc", |
| 61 | "txa", "txb", "txc"; |
| 62 | fsl,asrc-rate = <48000>; |
| 63 | fsl,asrc-width = <16>; |
| 64 | status = "okay"; |
| 65 | }; |