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Seungwon Jeon53b3d9c2013-08-31 21:40:22 +05301/*
2 * drivers/scsi/ufs/unipro.h
3 *
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#ifndef _UNIPRO_H_
13#define _UNIPRO_H_
14
15/*
Dolev Ravive7850602014-09-25 15:32:36 +030016 * M-TX Configuration Attributes
17 */
Yaniv Gardi37113102016-03-10 17:37:16 +020018#define TX_HIBERN8TIME_CAPABILITY 0x000F
Dolev Ravive7850602014-09-25 15:32:36 +030019#define TX_MODE 0x0021
20#define TX_HSRATE_SERIES 0x0022
21#define TX_HSGEAR 0x0023
22#define TX_PWMGEAR 0x0024
23#define TX_AMPLITUDE 0x0025
24#define TX_HS_SLEWRATE 0x0026
25#define TX_SYNC_SOURCE 0x0027
26#define TX_HS_SYNC_LENGTH 0x0028
27#define TX_HS_PREPARE_LENGTH 0x0029
28#define TX_LS_PREPARE_LENGTH 0x002A
29#define TX_HIBERN8_CONTROL 0x002B
30#define TX_LCC_ENABLE 0x002C
31#define TX_PWM_BURST_CLOSURE_EXTENSION 0x002D
32#define TX_BYPASS_8B10B_ENABLE 0x002E
33#define TX_DRIVER_POLARITY 0x002F
34#define TX_HS_UNTERMINATED_LINE_DRIVE_ENABLE 0x0030
35#define TX_LS_TERMINATED_LINE_DRIVE_ENABLE 0x0031
36#define TX_LCC_SEQUENCER 0x0032
37#define TX_MIN_ACTIVATETIME 0x0033
38#define TX_PWM_G6_G7_SYNC_LENGTH 0x0034
39
40/*
41 * M-RX Configuration Attributes
42 */
43#define RX_MODE 0x00A1
44#define RX_HSRATE_SERIES 0x00A2
45#define RX_HSGEAR 0x00A3
46#define RX_PWMGEAR 0x00A4
47#define RX_LS_TERMINATED_ENABLE 0x00A5
48#define RX_HS_UNTERMINATED_ENABLE 0x00A6
49#define RX_ENTER_HIBERN8 0x00A7
50#define RX_BYPASS_8B10B_ENABLE 0x00A8
51#define RX_TERMINATION_FORCE_ENABLE 0x0089
Yaniv Gardi37113102016-03-10 17:37:16 +020052#define RX_MIN_ACTIVATETIME_CAPABILITY 0x008F
53#define RX_HIBERN8TIME_CAPABILITY 0x0092
Dolev Ravive7850602014-09-25 15:32:36 +030054
55#define is_mphy_tx_attr(attr) (attr < RX_MODE)
Yaniv Gardi37113102016-03-10 17:37:16 +020056#define RX_MIN_ACTIVATETIME_UNIT_US 100
57#define HIBERN8TIME_UNIT_US 100
Dolev Ravive7850602014-09-25 15:32:36 +030058/*
Seungwon Jeon53b3d9c2013-08-31 21:40:22 +053059 * PHY Adpater attributes
60 */
61#define PA_ACTIVETXDATALANES 0x1560
62#define PA_ACTIVERXDATALANES 0x1580
63#define PA_TXTRAILINGCLOCKS 0x1564
64#define PA_PHY_TYPE 0x1500
65#define PA_AVAILTXDATALANES 0x1520
66#define PA_AVAILRXDATALANES 0x1540
67#define PA_MINRXTRAILINGCLOCKS 0x1543
68#define PA_TXPWRSTATUS 0x1567
69#define PA_RXPWRSTATUS 0x1582
70#define PA_TXFORCECLOCK 0x1562
71#define PA_TXPWRMODE 0x1563
72#define PA_LEGACYDPHYESCDL 0x1570
73#define PA_MAXTXSPEEDFAST 0x1521
74#define PA_MAXTXSPEEDSLOW 0x1522
75#define PA_MAXRXSPEEDFAST 0x1541
76#define PA_MAXRXSPEEDSLOW 0x1542
77#define PA_TXLINKSTARTUPHS 0x1544
Yaniv Gardi4b9ad0b2016-03-10 17:37:19 +020078#define PA_LOCAL_TX_LCC_ENABLE 0x155E
Seungwon Jeon53b3d9c2013-08-31 21:40:22 +053079#define PA_TXSPEEDFAST 0x1565
80#define PA_TXSPEEDSLOW 0x1566
81#define PA_REMOTEVERINFO 0x15A0
82#define PA_TXGEAR 0x1568
83#define PA_TXTERMINATION 0x1569
84#define PA_HSSERIES 0x156A
85#define PA_PWRMODE 0x1571
86#define PA_RXGEAR 0x1583
87#define PA_RXTERMINATION 0x1584
88#define PA_MAXRXPWMGEAR 0x1586
89#define PA_MAXRXHSGEAR 0x1587
90#define PA_RXHSUNTERMCAP 0x15A5
91#define PA_RXLSTERMCAP 0x15A6
92#define PA_PACPREQTIMEOUT 0x1590
93#define PA_PACPREQEOBTIMEOUT 0x1591
94#define PA_HIBERN8TIME 0x15A7
95#define PA_LOCALVERINFO 0x15A9
96#define PA_TACTIVATE 0x15A8
97#define PA_PACPFRAMECOUNT 0x15C0
98#define PA_PACPERRORCOUNT 0x15C1
99#define PA_PHYTESTCONTROL 0x15C2
100#define PA_PWRMODEUSERDATA0 0x15B0
101#define PA_PWRMODEUSERDATA1 0x15B1
102#define PA_PWRMODEUSERDATA2 0x15B2
103#define PA_PWRMODEUSERDATA3 0x15B3
104#define PA_PWRMODEUSERDATA4 0x15B4
105#define PA_PWRMODEUSERDATA5 0x15B5
106#define PA_PWRMODEUSERDATA6 0x15B6
107#define PA_PWRMODEUSERDATA7 0x15B7
108#define PA_PWRMODEUSERDATA8 0x15B8
109#define PA_PWRMODEUSERDATA9 0x15B9
110#define PA_PWRMODEUSERDATA10 0x15BA
111#define PA_PWRMODEUSERDATA11 0x15BB
112#define PA_CONNECTEDTXDATALANES 0x1561
113#define PA_CONNECTEDRXDATALANES 0x1581
114#define PA_LOGICALLANEMAP 0x15A1
115#define PA_SLEEPNOCONFIGTIME 0x15A2
116#define PA_STALLNOCONFIGTIME 0x15A3
117#define PA_SAVECONFIGTIME 0x15A4
118
Yaniv Gardi37113102016-03-10 17:37:16 +0200119#define PA_TACTIVATE_TIME_UNIT_US 10
120#define PA_HIBERN8_TIME_UNIT_US 100
121
122/* PHY Adapter Protocol Constants */
123#define PA_MAXDATALANES 4
124
Seungwon Jeond3e89ba2013-08-31 21:40:24 +0530125/* PA power modes */
126enum {
127 FAST_MODE = 1,
128 SLOW_MODE = 2,
129 FASTAUTO_MODE = 4,
130 SLOWAUTO_MODE = 5,
131 UNCHANGED = 7,
132};
133
134/* PA TX/RX Frequency Series */
135enum {
136 PA_HS_MODE_A = 1,
137 PA_HS_MODE_B = 2,
138};
139
Dolev Ravive7850602014-09-25 15:32:36 +0300140enum ufs_pwm_gear_tag {
141 UFS_PWM_DONT_CHANGE, /* Don't change Gear */
142 UFS_PWM_G1, /* PWM Gear 1 (default for reset) */
143 UFS_PWM_G2, /* PWM Gear 2 */
144 UFS_PWM_G3, /* PWM Gear 3 */
145 UFS_PWM_G4, /* PWM Gear 4 */
146 UFS_PWM_G5, /* PWM Gear 5 */
147 UFS_PWM_G6, /* PWM Gear 6 */
148 UFS_PWM_G7, /* PWM Gear 7 */
149};
150
151enum ufs_hs_gear_tag {
152 UFS_HS_DONT_CHANGE, /* Don't change Gear */
153 UFS_HS_G1, /* HS Gear 1 (default for reset) */
154 UFS_HS_G2, /* HS Gear 2 */
155 UFS_HS_G3, /* HS Gear 3 */
156};
157
Yaniv Gardi37113102016-03-10 17:37:16 +0200158enum ufs_unipro_ver {
159 UFS_UNIPRO_VER_RESERVED = 0,
160 UFS_UNIPRO_VER_1_40 = 1, /* UniPro version 1.40 */
161 UFS_UNIPRO_VER_1_41 = 2, /* UniPro version 1.41 */
162 UFS_UNIPRO_VER_1_6 = 3, /* UniPro version 1.6 */
163 UFS_UNIPRO_VER_MAX = 4, /* UniPro unsupported version */
164 /* UniPro version field mask in PA_LOCALVERINFO */
165 UFS_UNIPRO_VER_MASK = 0xF,
166};
167
Seungwon Jeon53b3d9c2013-08-31 21:40:22 +0530168/*
169 * Data Link Layer Attributes
170 */
171#define DL_TC0TXFCTHRESHOLD 0x2040
172#define DL_FC0PROTTIMEOUTVAL 0x2041
173#define DL_TC0REPLAYTIMEOUTVAL 0x2042
174#define DL_AFC0REQTIMEOUTVAL 0x2043
175#define DL_AFC0CREDITTHRESHOLD 0x2044
176#define DL_TC0OUTACKTHRESHOLD 0x2045
177#define DL_TC1TXFCTHRESHOLD 0x2060
178#define DL_FC1PROTTIMEOUTVAL 0x2061
179#define DL_TC1REPLAYTIMEOUTVAL 0x2062
180#define DL_AFC1REQTIMEOUTVAL 0x2063
181#define DL_AFC1CREDITTHRESHOLD 0x2064
182#define DL_TC1OUTACKTHRESHOLD 0x2065
183#define DL_TXPREEMPTIONCAP 0x2000
184#define DL_TC0TXMAXSDUSIZE 0x2001
185#define DL_TC0RXINITCREDITVAL 0x2002
186#define DL_TC0TXBUFFERSIZE 0x2005
187#define DL_PEERTC0PRESENT 0x2046
188#define DL_PEERTC0RXINITCREVAL 0x2047
189#define DL_TC1TXMAXSDUSIZE 0x2003
190#define DL_TC1RXINITCREDITVAL 0x2004
191#define DL_TC1TXBUFFERSIZE 0x2006
192#define DL_PEERTC1PRESENT 0x2066
193#define DL_PEERTC1RXINITCREVAL 0x2067
194
195/*
196 * Network Layer Attributes
197 */
198#define N_DEVICEID 0x3000
199#define N_DEVICEID_VALID 0x3001
200#define N_TC0TXMAXSDUSIZE 0x3020
201#define N_TC1TXMAXSDUSIZE 0x3021
202
203/*
204 * Transport Layer Attributes
205 */
206#define T_NUMCPORTS 0x4000
207#define T_NUMTESTFEATURES 0x4001
208#define T_CONNECTIONSTATE 0x4020
209#define T_PEERDEVICEID 0x4021
210#define T_PEERCPORTID 0x4022
211#define T_TRAFFICCLASS 0x4023
212#define T_PROTOCOLID 0x4024
213#define T_CPORTFLAGS 0x4025
214#define T_TXTOKENVALUE 0x4026
215#define T_RXTOKENVALUE 0x4027
216#define T_LOCALBUFFERSPACE 0x4028
217#define T_PEERBUFFERSPACE 0x4029
218#define T_CREDITSTOSEND 0x402A
219#define T_CPORTMODE 0x402B
220#define T_TC0TXMAXSDUSIZE 0x4060
221#define T_TC1TXMAXSDUSIZE 0x4061
222
Suthikulpanit, Suraveee144cd02015-06-10 11:08:58 -0500223#ifdef FALSE
224#undef FALSE
225#endif
226
227#ifdef TRUE
228#undef TRUE
229#endif
230
Seungwon Jeond3e89ba2013-08-31 21:40:24 +0530231/* Boolean attribute values */
232enum {
233 FALSE = 0,
234 TRUE,
235};
236
Seungwon Jeon53b3d9c2013-08-31 21:40:22 +0530237#endif /* _UNIPRO_H_ */