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gerrit-public.fairphone.software / kernel / msm-4.19 / 4d8915234165fc85873121f228011b93f9e242d7 / . / arch / arm / mach-omap2 / prm44xx.h
blob: ee72ae6bd8c961350be2ebb343a027f6d1f4fddf [file] [log] [blame]
Rajendra Nayakc1294042009-12-08 18:24:51 -0700[diff] [blame]1/*
2 * OMAP44xx PRM instance offset macros
3 *
Paul Walmsley26c98c52011-12-16 14:36:58 -0700[diff] [blame]4 * Copyright (C) 2009-2011 Texas Instruments, Inc.
Benoit Cousson79328702010-05-20 12:31:11 -0600[diff] [blame]5 * Copyright (C) 2009-2010 Nokia Corporation
Rajendra Nayakc1294042009-12-08 18:24:51 -0700[diff] [blame]6 *
7 * Paul Walmsley (paul@pwsan.com)
8 * Rajendra Nayak (rnayak@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
10 *
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]20 *
21 * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX",
22 * or "OMAP4430".
Rajendra Nayakc1294042009-12-08 18:24:51 -0700[diff] [blame]23 */
24
25#ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_H
26#define __ARCH_ARM_MACH_OMAP2_PRM44XX_H
27
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]28#include "prcm-common.h"
Paul Walmsley59fb6592010-12-21 15:30:55 -0700[diff] [blame]29#include "prm.h"
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]30
31#define OMAP4430_PRM_BASE 0x4a306000
32
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]33#define OMAP44XX_PRM_REGADDR(inst, reg) \
Benoit Coussonad98a182011-07-09 19:15:04 -0600[diff] [blame]34 OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (inst) + (reg))
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]35
36
37/* PRM instances */
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]38#define OMAP4430_PRM_OCP_SOCKET_INST 0x0000
39#define OMAP4430_PRM_CKGEN_INST 0x0100
40#define OMAP4430_PRM_MPU_INST 0x0300
41#define OMAP4430_PRM_TESLA_INST 0x0400
42#define OMAP4430_PRM_ABE_INST 0x0500
43#define OMAP4430_PRM_ALWAYS_ON_INST 0x0600
44#define OMAP4430_PRM_CORE_INST 0x0700
45#define OMAP4430_PRM_IVAHD_INST 0x0f00
46#define OMAP4430_PRM_CAM_INST 0x1000
47#define OMAP4430_PRM_DSS_INST 0x1100
48#define OMAP4430_PRM_GFX_INST 0x1200
Benoit Coussonad98a182011-07-09 19:15:04 -0600[diff] [blame]49#define OMAP4430_PRM_L3INIT_INST 0x1300
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]50#define OMAP4430_PRM_L4PER_INST 0x1400
Benoit Coussonad98a182011-07-09 19:15:04 -0600[diff] [blame]51#define OMAP4430_PRM_CEFUSE_INST 0x1600
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]52#define OMAP4430_PRM_WKUP_INST 0x1700
53#define OMAP4430_PRM_WKUP_CM_INST 0x1800
54#define OMAP4430_PRM_EMU_INST 0x1900
Benoit Coussonad98a182011-07-09 19:15:04 -0600[diff] [blame]55#define OMAP4430_PRM_EMU_CM_INST 0x1a00
56#define OMAP4430_PRM_DEVICE_INST 0x1b00
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]57#define OMAP4430_PRM_INSTR_INST 0x1f00
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]58
Paul Walmsleye4156ee2010-12-21 21:05:15 -0700[diff] [blame]59/* PRM clockdomain register offsets (from instance start) */
Paul Walmsleye4156ee2010-12-21 21:05:15 -0700[diff] [blame]60#define OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS 0x0000
Paul Walmsleye4156ee2010-12-21 21:05:15 -0700[diff] [blame]61#define OMAP4430_PRM_EMU_CM_EMU_CDOFFS 0x0000
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]62
63/* OMAP4 specific register offsets */
64#define OMAP4_RM_RSTCTRL 0x0000
65#define OMAP4_RM_RSTTIME 0x0004
66#define OMAP4_RM_RSTST 0x0008
67#define OMAP4_PM_PWSTCTRL 0x0000
68#define OMAP4_PM_PWSTST 0x0004
69
Rajendra Nayakc1294042009-12-08 18:24:51 -0700[diff] [blame]70
71/* PRM */
72
Rajendra Nayakc1294042009-12-08 18:24:51 -0700[diff] [blame]73/* PRM.OCP_SOCKET_PRM register offsets */
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]74#define OMAP4_REVISION_PRM_OFFSET 0x0000
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]75#define OMAP4430_REVISION_PRM OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0000)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]76#define OMAP4_PRM_IRQSTATUS_MPU_OFFSET 0x0010
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]77#define OMAP4430_PRM_IRQSTATUS_MPU OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0010)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]78#define OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET 0x0014
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]79#define OMAP4430_PRM_IRQSTATUS_MPU_2 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0014)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]80#define OMAP4_PRM_IRQENABLE_MPU_OFFSET 0x0018
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]81#define OMAP4430_PRM_IRQENABLE_MPU OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0018)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]82#define OMAP4_PRM_IRQENABLE_MPU_2_OFFSET 0x001c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]83#define OMAP4430_PRM_IRQENABLE_MPU_2 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x001c)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]84#define OMAP4_PRM_IRQSTATUS_DUCATI_OFFSET 0x0020
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]85#define OMAP4430_PRM_IRQSTATUS_DUCATI OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0020)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]86#define OMAP4_PRM_IRQENABLE_DUCATI_OFFSET 0x0028
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]87#define OMAP4430_PRM_IRQENABLE_DUCATI OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0028)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]88#define OMAP4_PRM_IRQSTATUS_TESLA_OFFSET 0x0030
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]89#define OMAP4430_PRM_IRQSTATUS_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0030)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]90#define OMAP4_PRM_IRQENABLE_TESLA_OFFSET 0x0038
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]91#define OMAP4430_PRM_IRQENABLE_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0038)
Rajendra Nayakfdd4f402010-09-27 14:02:56 -0600[diff] [blame]92#define OMAP4_CM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]93#define OMAP4430_CM_PRM_PROFILING_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0040)
Rajendra Nayakc1294042009-12-08 18:24:51 -0700[diff] [blame]94
95/* PRM.CKGEN_PRM register offsets */
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]96#define OMAP4_CM_ABE_DSS_SYS_CLKSEL_OFFSET 0x0000
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]97#define OMAP4430_CM_ABE_DSS_SYS_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x0000)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]98#define OMAP4_CM_L4_WKUP_CLKSEL_OFFSET 0x0008
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]99#define OMAP4430_CM_L4_WKUP_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x0008)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]100#define OMAP4_CM_ABE_PLL_REF_CLKSEL_OFFSET 0x000c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]101#define OMAP4430_CM_ABE_PLL_REF_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x000c)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]102#define OMAP4_CM_SYS_CLKSEL_OFFSET 0x0010
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]103#define OMAP4430_CM_SYS_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x0010)
Rajendra Nayakc1294042009-12-08 18:24:51 -0700[diff] [blame]104
105/* PRM.MPU_PRM register offsets */
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]106#define OMAP4_PM_MPU_PWRSTCTRL_OFFSET 0x0000
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]107#define OMAP4430_PM_MPU_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0000)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]108#define OMAP4_PM_MPU_PWRSTST_OFFSET 0x0004
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]109#define OMAP4430_PM_MPU_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0004)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]110#define OMAP4_RM_MPU_RSTST_OFFSET 0x0014
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]111#define OMAP4430_RM_MPU_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0014)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]112#define OMAP4_RM_MPU_MPU_CONTEXT_OFFSET 0x0024
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]113#define OMAP4430_RM_MPU_MPU_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0024)
Rajendra Nayakc1294042009-12-08 18:24:51 -0700[diff] [blame]114
115/* PRM.TESLA_PRM register offsets */
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]116#define OMAP4_PM_TESLA_PWRSTCTRL_OFFSET 0x0000
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]117#define OMAP4430_PM_TESLA_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0000)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]118#define OMAP4_PM_TESLA_PWRSTST_OFFSET 0x0004
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]119#define OMAP4430_PM_TESLA_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0004)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]120#define OMAP4_RM_TESLA_RSTCTRL_OFFSET 0x0010
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]121#define OMAP4430_RM_TESLA_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0010)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]122#define OMAP4_RM_TESLA_RSTST_OFFSET 0x0014
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]123#define OMAP4430_RM_TESLA_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0014)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]124#define OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET 0x0024
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]125#define OMAP4430_RM_TESLA_TESLA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0024)
Rajendra Nayakc1294042009-12-08 18:24:51 -0700[diff] [blame]126
127/* PRM.ABE_PRM register offsets */
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]128#define OMAP4_PM_ABE_PWRSTCTRL_OFFSET 0x0000
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]129#define OMAP4430_PM_ABE_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0000)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]130#define OMAP4_PM_ABE_PWRSTST_OFFSET 0x0004
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]131#define OMAP4430_PM_ABE_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0004)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]132#define OMAP4_RM_ABE_AESS_CONTEXT_OFFSET 0x002c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]133#define OMAP4430_RM_ABE_AESS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x002c)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]134#define OMAP4_PM_ABE_PDM_WKDEP_OFFSET 0x0030
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]135#define OMAP4430_PM_ABE_PDM_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0030)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]136#define OMAP4_RM_ABE_PDM_CONTEXT_OFFSET 0x0034
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]137#define OMAP4430_RM_ABE_PDM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0034)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]138#define OMAP4_PM_ABE_DMIC_WKDEP_OFFSET 0x0038
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]139#define OMAP4430_PM_ABE_DMIC_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0038)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]140#define OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET 0x003c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]141#define OMAP4430_RM_ABE_DMIC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x003c)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]142#define OMAP4_PM_ABE_MCASP_WKDEP_OFFSET 0x0040
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]143#define OMAP4430_PM_ABE_MCASP_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0040)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]144#define OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET 0x0044
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]145#define OMAP4430_RM_ABE_MCASP_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0044)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]146#define OMAP4_PM_ABE_MCBSP1_WKDEP_OFFSET 0x0048
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]147#define OMAP4430_PM_ABE_MCBSP1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0048)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]148#define OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET 0x004c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]149#define OMAP4430_RM_ABE_MCBSP1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x004c)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]150#define OMAP4_PM_ABE_MCBSP2_WKDEP_OFFSET 0x0050
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]151#define OMAP4430_PM_ABE_MCBSP2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0050)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]152#define OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET 0x0054
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]153#define OMAP4430_RM_ABE_MCBSP2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0054)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]154#define OMAP4_PM_ABE_MCBSP3_WKDEP_OFFSET 0x0058
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]155#define OMAP4430_PM_ABE_MCBSP3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0058)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]156#define OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET 0x005c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]157#define OMAP4430_RM_ABE_MCBSP3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x005c)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]158#define OMAP4_PM_ABE_SLIMBUS_WKDEP_OFFSET 0x0060
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]159#define OMAP4430_PM_ABE_SLIMBUS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0060)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]160#define OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET 0x0064
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]161#define OMAP4430_RM_ABE_SLIMBUS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0064)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]162#define OMAP4_PM_ABE_TIMER5_WKDEP_OFFSET 0x0068
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]163#define OMAP4430_PM_ABE_TIMER5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0068)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]164#define OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET 0x006c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]165#define OMAP4430_RM_ABE_TIMER5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x006c)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]166#define OMAP4_PM_ABE_TIMER6_WKDEP_OFFSET 0x0070
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]167#define OMAP4430_PM_ABE_TIMER6_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0070)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]168#define OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET 0x0074
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]169#define OMAP4430_RM_ABE_TIMER6_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0074)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]170#define OMAP4_PM_ABE_TIMER7_WKDEP_OFFSET 0x0078
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]171#define OMAP4430_PM_ABE_TIMER7_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0078)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]172#define OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET 0x007c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]173#define OMAP4430_RM_ABE_TIMER7_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x007c)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]174#define OMAP4_PM_ABE_TIMER8_WKDEP_OFFSET 0x0080
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]175#define OMAP4430_PM_ABE_TIMER8_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0080)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]176#define OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET 0x0084
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]177#define OMAP4430_RM_ABE_TIMER8_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0084)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]178#define OMAP4_PM_ABE_WDT3_WKDEP_OFFSET 0x0088
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]179#define OMAP4430_PM_ABE_WDT3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0088)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]180#define OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET 0x008c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]181#define OMAP4430_RM_ABE_WDT3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x008c)
Rajendra Nayakc1294042009-12-08 18:24:51 -0700[diff] [blame]182
183/* PRM.ALWAYS_ON_PRM register offsets */
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]184#define OMAP4_RM_ALWON_MDMINTC_CONTEXT_OFFSET 0x0024
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]185#define OMAP4430_RM_ALWON_MDMINTC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0024)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]186#define OMAP4_PM_ALWON_SR_MPU_WKDEP_OFFSET 0x0028
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]187#define OMAP4430_PM_ALWON_SR_MPU_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0028)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]188#define OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET 0x002c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]189#define OMAP4430_RM_ALWON_SR_MPU_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x002c)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]190#define OMAP4_PM_ALWON_SR_IVA_WKDEP_OFFSET 0x0030
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]191#define OMAP4430_PM_ALWON_SR_IVA_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0030)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]192#define OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET 0x0034
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]193#define OMAP4430_RM_ALWON_SR_IVA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0034)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]194#define OMAP4_PM_ALWON_SR_CORE_WKDEP_OFFSET 0x0038
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]195#define OMAP4430_PM_ALWON_SR_CORE_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0038)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]196#define OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET 0x003c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]197#define OMAP4430_RM_ALWON_SR_CORE_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x003c)
Rajendra Nayakc1294042009-12-08 18:24:51 -0700[diff] [blame]198
199/* PRM.CORE_PRM register offsets */
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]200#define OMAP4_PM_CORE_PWRSTCTRL_OFFSET 0x0000
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]201#define OMAP4430_PM_CORE_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0000)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]202#define OMAP4_PM_CORE_PWRSTST_OFFSET 0x0004
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]203#define OMAP4430_PM_CORE_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0004)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]204#define OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET 0x0024
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]205#define OMAP4430_RM_L3_1_L3_1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0024)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]206#define OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET 0x0124
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]207#define OMAP4430_RM_L3_2_L3_2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0124)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]208#define OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET 0x012c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]209#define OMAP4430_RM_L3_2_GPMC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x012c)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]210#define OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET 0x0134
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]211#define OMAP4430_RM_L3_2_OCMC_RAM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0134)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]212#define OMAP4_RM_DUCATI_RSTCTRL_OFFSET 0x0210
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]213#define OMAP4430_RM_DUCATI_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0210)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]214#define OMAP4_RM_DUCATI_RSTST_OFFSET 0x0214
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]215#define OMAP4430_RM_DUCATI_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0214)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]216#define OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET 0x0224
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]217#define OMAP4430_RM_DUCATI_DUCATI_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0224)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]218#define OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET 0x0324
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]219#define OMAP4430_RM_SDMA_SDMA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0324)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]220#define OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET 0x0424
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]221#define OMAP4430_RM_MEMIF_DMM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0424)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]222#define OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET 0x042c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]223#define OMAP4430_RM_MEMIF_EMIF_FW_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x042c)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]224#define OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET 0x0434
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]225#define OMAP4430_RM_MEMIF_EMIF_1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0434)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]226#define OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET 0x043c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]227#define OMAP4430_RM_MEMIF_EMIF_2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x043c)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]228#define OMAP4_RM_MEMIF_DLL_CONTEXT_OFFSET 0x0444
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]229#define OMAP4430_RM_MEMIF_DLL_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0444)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]230#define OMAP4_RM_MEMIF_EMIF_H1_CONTEXT_OFFSET 0x0454
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]231#define OMAP4430_RM_MEMIF_EMIF_H1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0454)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]232#define OMAP4_RM_MEMIF_EMIF_H2_CONTEXT_OFFSET 0x045c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]233#define OMAP4430_RM_MEMIF_EMIF_H2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x045c)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]234#define OMAP4_RM_MEMIF_DLL_H_CONTEXT_OFFSET 0x0464
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]235#define OMAP4430_RM_MEMIF_DLL_H_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0464)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]236#define OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET 0x0524
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]237#define OMAP4430_RM_D2D_SAD2D_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0524)
Benoit Coussonad98a182011-07-09 19:15:04 -0600[diff] [blame]238#define OMAP4_RM_D2D_MODEM_ICR_CONTEXT_OFFSET 0x052c
239#define OMAP4430_RM_D2D_MODEM_ICR_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x052c)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]240#define OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET 0x0534
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]241#define OMAP4430_RM_D2D_SAD2D_FW_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0534)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]242#define OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET 0x0624
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]243#define OMAP4430_RM_L4CFG_L4_CFG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0624)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]244#define OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET 0x062c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]245#define OMAP4430_RM_L4CFG_HW_SEM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x062c)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]246#define OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET 0x0634
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]247#define OMAP4430_RM_L4CFG_MAILBOX_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0634)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]248#define OMAP4_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET 0x063c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]249#define OMAP4430_RM_L4CFG_SAR_ROM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x063c)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]250#define OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET 0x0724
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]251#define OMAP4430_RM_L3INSTR_L3_3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0724)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]252#define OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET 0x072c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]253#define OMAP4430_RM_L3INSTR_L3_INSTR_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x072c)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]254#define OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET 0x0744
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]255#define OMAP4430_RM_L3INSTR_OCP_WP1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0744)
Rajendra Nayakc1294042009-12-08 18:24:51 -0700[diff] [blame]256
257/* PRM.IVAHD_PRM register offsets */
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]258#define OMAP4_PM_IVAHD_PWRSTCTRL_OFFSET 0x0000
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]259#define OMAP4430_PM_IVAHD_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0000)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]260#define OMAP4_PM_IVAHD_PWRSTST_OFFSET 0x0004
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]261#define OMAP4430_PM_IVAHD_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0004)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]262#define OMAP4_RM_IVAHD_RSTCTRL_OFFSET 0x0010
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]263#define OMAP4430_RM_IVAHD_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0010)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]264#define OMAP4_RM_IVAHD_RSTST_OFFSET 0x0014
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]265#define OMAP4430_RM_IVAHD_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0014)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]266#define OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET 0x0024
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]267#define OMAP4430_RM_IVAHD_IVAHD_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0024)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]268#define OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET 0x002c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]269#define OMAP4430_RM_IVAHD_SL2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x002c)
Rajendra Nayakc1294042009-12-08 18:24:51 -0700[diff] [blame]270
271/* PRM.CAM_PRM register offsets */
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]272#define OMAP4_PM_CAM_PWRSTCTRL_OFFSET 0x0000
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]273#define OMAP4430_PM_CAM_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x0000)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]274#define OMAP4_PM_CAM_PWRSTST_OFFSET 0x0004
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]275#define OMAP4430_PM_CAM_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x0004)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]276#define OMAP4_RM_CAM_ISS_CONTEXT_OFFSET 0x0024
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]277#define OMAP4430_RM_CAM_ISS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x0024)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]278#define OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET 0x002c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]279#define OMAP4430_RM_CAM_FDIF_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x002c)
Rajendra Nayakc1294042009-12-08 18:24:51 -0700[diff] [blame]280
281/* PRM.DSS_PRM register offsets */
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]282#define OMAP4_PM_DSS_PWRSTCTRL_OFFSET 0x0000
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]283#define OMAP4430_PM_DSS_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0000)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]284#define OMAP4_PM_DSS_PWRSTST_OFFSET 0x0004
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]285#define OMAP4430_PM_DSS_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0004)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]286#define OMAP4_PM_DSS_DSS_WKDEP_OFFSET 0x0020
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]287#define OMAP4430_PM_DSS_DSS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0020)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]288#define OMAP4_RM_DSS_DSS_CONTEXT_OFFSET 0x0024
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]289#define OMAP4430_RM_DSS_DSS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0024)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]290#define OMAP4_RM_DSS_DEISS_CONTEXT_OFFSET 0x002c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]291#define OMAP4430_RM_DSS_DEISS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x002c)
Rajendra Nayakc1294042009-12-08 18:24:51 -0700[diff] [blame]292
293/* PRM.GFX_PRM register offsets */
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]294#define OMAP4_PM_GFX_PWRSTCTRL_OFFSET 0x0000
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]295#define OMAP4430_PM_GFX_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_INST, 0x0000)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]296#define OMAP4_PM_GFX_PWRSTST_OFFSET 0x0004
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]297#define OMAP4430_PM_GFX_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_INST, 0x0004)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]298#define OMAP4_RM_GFX_GFX_CONTEXT_OFFSET 0x0024
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]299#define OMAP4430_RM_GFX_GFX_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_INST, 0x0024)
Rajendra Nayakc1294042009-12-08 18:24:51 -0700[diff] [blame]300
301/* PRM.L3INIT_PRM register offsets */
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]302#define OMAP4_PM_L3INIT_PWRSTCTRL_OFFSET 0x0000
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]303#define OMAP4430_PM_L3INIT_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0000)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]304#define OMAP4_PM_L3INIT_PWRSTST_OFFSET 0x0004
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]305#define OMAP4430_PM_L3INIT_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0004)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]306#define OMAP4_PM_L3INIT_MMC1_WKDEP_OFFSET 0x0028
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]307#define OMAP4430_PM_L3INIT_MMC1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0028)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]308#define OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET 0x002c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]309#define OMAP4430_RM_L3INIT_MMC1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x002c)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]310#define OMAP4_PM_L3INIT_MMC2_WKDEP_OFFSET 0x0030
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]311#define OMAP4430_PM_L3INIT_MMC2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0030)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]312#define OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET 0x0034
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]313#define OMAP4430_RM_L3INIT_MMC2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0034)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]314#define OMAP4_PM_L3INIT_HSI_WKDEP_OFFSET 0x0038
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]315#define OMAP4430_PM_L3INIT_HSI_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0038)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]316#define OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET 0x003c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]317#define OMAP4430_RM_L3INIT_HSI_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x003c)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]318#define OMAP4_PM_L3INIT_UNIPRO1_WKDEP_OFFSET 0x0040
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]319#define OMAP4430_PM_L3INIT_UNIPRO1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0040)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]320#define OMAP4_RM_L3INIT_UNIPRO1_CONTEXT_OFFSET 0x0044
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]321#define OMAP4430_RM_L3INIT_UNIPRO1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0044)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]322#define OMAP4_PM_L3INIT_USB_HOST_WKDEP_OFFSET 0x0058
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]323#define OMAP4430_PM_L3INIT_USB_HOST_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0058)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]324#define OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET 0x005c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]325#define OMAP4430_RM_L3INIT_USB_HOST_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x005c)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]326#define OMAP4_PM_L3INIT_USB_OTG_WKDEP_OFFSET 0x0060
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]327#define OMAP4430_PM_L3INIT_USB_OTG_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0060)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]328#define OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET 0x0064
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]329#define OMAP4430_RM_L3INIT_USB_OTG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0064)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]330#define OMAP4_PM_L3INIT_USB_TLL_WKDEP_OFFSET 0x0068
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]331#define OMAP4430_PM_L3INIT_USB_TLL_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0068)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]332#define OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET 0x006c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]333#define OMAP4430_RM_L3INIT_USB_TLL_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x006c)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]334#define OMAP4_RM_L3INIT_P1500_CONTEXT_OFFSET 0x007c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]335#define OMAP4430_RM_L3INIT_P1500_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x007c)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]336#define OMAP4_RM_L3INIT_EMAC_CONTEXT_OFFSET 0x0084
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]337#define OMAP4430_RM_L3INIT_EMAC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0084)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]338#define OMAP4_PM_L3INIT_SATA_WKDEP_OFFSET 0x0088
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]339#define OMAP4430_PM_L3INIT_SATA_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0088)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]340#define OMAP4_RM_L3INIT_SATA_CONTEXT_OFFSET 0x008c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]341#define OMAP4430_RM_L3INIT_SATA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x008c)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]342#define OMAP4_RM_L3INIT_TPPSS_CONTEXT_OFFSET 0x0094
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]343#define OMAP4430_RM_L3INIT_TPPSS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0094)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]344#define OMAP4_PM_L3INIT_PCIESS_WKDEP_OFFSET 0x0098
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]345#define OMAP4430_PM_L3INIT_PCIESS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0098)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]346#define OMAP4_RM_L3INIT_PCIESS_CONTEXT_OFFSET 0x009c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]347#define OMAP4430_RM_L3INIT_PCIESS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x009c)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]348#define OMAP4_RM_L3INIT_CCPTX_CONTEXT_OFFSET 0x00ac
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]349#define OMAP4430_RM_L3INIT_CCPTX_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00ac)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]350#define OMAP4_PM_L3INIT_XHPI_WKDEP_OFFSET 0x00c0
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]351#define OMAP4430_PM_L3INIT_XHPI_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00c0)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]352#define OMAP4_RM_L3INIT_XHPI_CONTEXT_OFFSET 0x00c4
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]353#define OMAP4430_RM_L3INIT_XHPI_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00c4)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]354#define OMAP4_PM_L3INIT_MMC6_WKDEP_OFFSET 0x00c8
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]355#define OMAP4430_PM_L3INIT_MMC6_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00c8)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]356#define OMAP4_RM_L3INIT_MMC6_CONTEXT_OFFSET 0x00cc
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]357#define OMAP4430_RM_L3INIT_MMC6_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00cc)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]358#define OMAP4_PM_L3INIT_USB_HOST_FS_WKDEP_OFFSET 0x00d0
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]359#define OMAP4430_PM_L3INIT_USB_HOST_FS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00d0)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]360#define OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET 0x00d4
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]361#define OMAP4430_RM_L3INIT_USB_HOST_FS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00d4)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]362#define OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET 0x00e4
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]363#define OMAP4430_RM_L3INIT_USBPHYOCP2SCP_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00e4)
Rajendra Nayakc1294042009-12-08 18:24:51 -0700[diff] [blame]364
365/* PRM.L4PER_PRM register offsets */
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]366#define OMAP4_PM_L4PER_PWRSTCTRL_OFFSET 0x0000
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]367#define OMAP4430_PM_L4PER_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0000)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]368#define OMAP4_PM_L4PER_PWRSTST_OFFSET 0x0004
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]369#define OMAP4430_PM_L4PER_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0004)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]370#define OMAP4_RM_L4PER_ADC_CONTEXT_OFFSET 0x0024
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]371#define OMAP4430_RM_L4PER_ADC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0024)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]372#define OMAP4_PM_L4PER_DMTIMER10_WKDEP_OFFSET 0x0028
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]373#define OMAP4430_PM_L4PER_DMTIMER10_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0028)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]374#define OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET 0x002c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]375#define OMAP4430_RM_L4PER_DMTIMER10_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x002c)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]376#define OMAP4_PM_L4PER_DMTIMER11_WKDEP_OFFSET 0x0030
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]377#define OMAP4430_PM_L4PER_DMTIMER11_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0030)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]378#define OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET 0x0034
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]379#define OMAP4430_RM_L4PER_DMTIMER11_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0034)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]380#define OMAP4_PM_L4PER_DMTIMER2_WKDEP_OFFSET 0x0038
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]381#define OMAP4430_PM_L4PER_DMTIMER2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0038)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]382#define OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET 0x003c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]383#define OMAP4430_RM_L4PER_DMTIMER2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x003c)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]384#define OMAP4_PM_L4PER_DMTIMER3_WKDEP_OFFSET 0x0040
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]385#define OMAP4430_PM_L4PER_DMTIMER3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0040)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]386#define OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET 0x0044
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]387#define OMAP4430_RM_L4PER_DMTIMER3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0044)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]388#define OMAP4_PM_L4PER_DMTIMER4_WKDEP_OFFSET 0x0048
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]389#define OMAP4430_PM_L4PER_DMTIMER4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0048)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]390#define OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET 0x004c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]391#define OMAP4430_RM_L4PER_DMTIMER4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x004c)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]392#define OMAP4_PM_L4PER_DMTIMER9_WKDEP_OFFSET 0x0050
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]393#define OMAP4430_PM_L4PER_DMTIMER9_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0050)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]394#define OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET 0x0054
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]395#define OMAP4430_RM_L4PER_DMTIMER9_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0054)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]396#define OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET 0x005c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]397#define OMAP4430_RM_L4PER_ELM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x005c)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]398#define OMAP4_PM_L4PER_GPIO2_WKDEP_OFFSET 0x0060
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]399#define OMAP4430_PM_L4PER_GPIO2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0060)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]400#define OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET 0x0064
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]401#define OMAP4430_RM_L4PER_GPIO2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0064)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]402#define OMAP4_PM_L4PER_GPIO3_WKDEP_OFFSET 0x0068
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]403#define OMAP4430_PM_L4PER_GPIO3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0068)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]404#define OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET 0x006c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]405#define OMAP4430_RM_L4PER_GPIO3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x006c)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]406#define OMAP4_PM_L4PER_GPIO4_WKDEP_OFFSET 0x0070
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]407#define OMAP4430_PM_L4PER_GPIO4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0070)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]408#define OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET 0x0074
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]409#define OMAP4430_RM_L4PER_GPIO4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0074)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]410#define OMAP4_PM_L4PER_GPIO5_WKDEP_OFFSET 0x0078
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]411#define OMAP4430_PM_L4PER_GPIO5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0078)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]412#define OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET 0x007c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]413#define OMAP4430_RM_L4PER_GPIO5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x007c)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]414#define OMAP4_PM_L4PER_GPIO6_WKDEP_OFFSET 0x0080
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]415#define OMAP4430_PM_L4PER_GPIO6_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0080)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]416#define OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET 0x0084
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]417#define OMAP4430_RM_L4PER_GPIO6_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0084)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]418#define OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET 0x008c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]419#define OMAP4430_RM_L4PER_HDQ1W_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x008c)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]420#define OMAP4_PM_L4PER_HECC1_WKDEP_OFFSET 0x0090
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]421#define OMAP4430_PM_L4PER_HECC1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0090)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]422#define OMAP4_RM_L4PER_HECC1_CONTEXT_OFFSET 0x0094
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]423#define OMAP4430_RM_L4PER_HECC1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0094)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]424#define OMAP4_PM_L4PER_HECC2_WKDEP_OFFSET 0x0098
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]425#define OMAP4430_PM_L4PER_HECC2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0098)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]426#define OMAP4_RM_L4PER_HECC2_CONTEXT_OFFSET 0x009c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]427#define OMAP4430_RM_L4PER_HECC2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x009c)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]428#define OMAP4_PM_L4PER_I2C1_WKDEP_OFFSET 0x00a0
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]429#define OMAP4430_PM_L4PER_I2C1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00a0)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]430#define OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET 0x00a4
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]431#define OMAP4430_RM_L4PER_I2C1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00a4)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]432#define OMAP4_PM_L4PER_I2C2_WKDEP_OFFSET 0x00a8
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]433#define OMAP4430_PM_L4PER_I2C2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00a8)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]434#define OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET 0x00ac
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]435#define OMAP4430_RM_L4PER_I2C2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00ac)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]436#define OMAP4_PM_L4PER_I2C3_WKDEP_OFFSET 0x00b0
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]437#define OMAP4430_PM_L4PER_I2C3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00b0)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]438#define OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET 0x00b4
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]439#define OMAP4430_RM_L4PER_I2C3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00b4)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]440#define OMAP4_PM_L4PER_I2C4_WKDEP_OFFSET 0x00b8
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]441#define OMAP4430_PM_L4PER_I2C4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00b8)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]442#define OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET 0x00bc
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]443#define OMAP4430_RM_L4PER_I2C4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00bc)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]444#define OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET 0x00c0
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]445#define OMAP4430_RM_L4PER_L4_PER_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00c0)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]446#define OMAP4_PM_L4PER_MCASP2_WKDEP_OFFSET 0x00d0
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]447#define OMAP4430_PM_L4PER_MCASP2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00d0)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]448#define OMAP4_RM_L4PER_MCASP2_CONTEXT_OFFSET 0x00d4
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]449#define OMAP4430_RM_L4PER_MCASP2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00d4)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]450#define OMAP4_PM_L4PER_MCASP3_WKDEP_OFFSET 0x00d8
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]451#define OMAP4430_PM_L4PER_MCASP3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00d8)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]452#define OMAP4_RM_L4PER_MCASP3_CONTEXT_OFFSET 0x00dc
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]453#define OMAP4430_RM_L4PER_MCASP3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00dc)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]454#define OMAP4_PM_L4PER_MCBSP4_WKDEP_OFFSET 0x00e0
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]455#define OMAP4430_PM_L4PER_MCBSP4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00e0)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]456#define OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET 0x00e4
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]457#define OMAP4430_RM_L4PER_MCBSP4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00e4)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]458#define OMAP4_RM_L4PER_MGATE_CONTEXT_OFFSET 0x00ec
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]459#define OMAP4430_RM_L4PER_MGATE_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00ec)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]460#define OMAP4_PM_L4PER_MCSPI1_WKDEP_OFFSET 0x00f0
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]461#define OMAP4430_PM_L4PER_MCSPI1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00f0)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]462#define OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET 0x00f4
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]463#define OMAP4430_RM_L4PER_MCSPI1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00f4)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]464#define OMAP4_PM_L4PER_MCSPI2_WKDEP_OFFSET 0x00f8
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]465#define OMAP4430_PM_L4PER_MCSPI2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00f8)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]466#define OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET 0x00fc
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]467#define OMAP4430_RM_L4PER_MCSPI2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00fc)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]468#define OMAP4_PM_L4PER_MCSPI3_WKDEP_OFFSET 0x0100
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]469#define OMAP4430_PM_L4PER_MCSPI3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0100)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]470#define OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET 0x0104
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]471#define OMAP4430_RM_L4PER_MCSPI3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0104)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]472#define OMAP4_PM_L4PER_MCSPI4_WKDEP_OFFSET 0x0108
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]473#define OMAP4430_PM_L4PER_MCSPI4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0108)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]474#define OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET 0x010c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]475#define OMAP4430_RM_L4PER_MCSPI4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x010c)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]476#define OMAP4_PM_L4PER_MMCSD3_WKDEP_OFFSET 0x0120
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]477#define OMAP4430_PM_L4PER_MMCSD3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0120)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]478#define OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET 0x0124
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]479#define OMAP4430_RM_L4PER_MMCSD3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0124)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]480#define OMAP4_PM_L4PER_MMCSD4_WKDEP_OFFSET 0x0128
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]481#define OMAP4430_PM_L4PER_MMCSD4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0128)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]482#define OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET 0x012c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]483#define OMAP4430_RM_L4PER_MMCSD4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x012c)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]484#define OMAP4_RM_L4PER_MSPROHG_CONTEXT_OFFSET 0x0134
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]485#define OMAP4430_RM_L4PER_MSPROHG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0134)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]486#define OMAP4_PM_L4PER_SLIMBUS2_WKDEP_OFFSET 0x0138
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]487#define OMAP4430_PM_L4PER_SLIMBUS2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0138)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]488#define OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET 0x013c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]489#define OMAP4430_RM_L4PER_SLIMBUS2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x013c)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]490#define OMAP4_PM_L4PER_UART1_WKDEP_OFFSET 0x0140
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]491#define OMAP4430_PM_L4PER_UART1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0140)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]492#define OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET 0x0144
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]493#define OMAP4430_RM_L4PER_UART1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0144)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]494#define OMAP4_PM_L4PER_UART2_WKDEP_OFFSET 0x0148
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]495#define OMAP4430_PM_L4PER_UART2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0148)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]496#define OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET 0x014c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]497#define OMAP4430_RM_L4PER_UART2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x014c)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]498#define OMAP4_PM_L4PER_UART3_WKDEP_OFFSET 0x0150
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]499#define OMAP4430_PM_L4PER_UART3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0150)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]500#define OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET 0x0154
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]501#define OMAP4430_RM_L4PER_UART3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0154)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]502#define OMAP4_PM_L4PER_UART4_WKDEP_OFFSET 0x0158
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]503#define OMAP4430_PM_L4PER_UART4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0158)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]504#define OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET 0x015c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]505#define OMAP4430_RM_L4PER_UART4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x015c)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]506#define OMAP4_PM_L4PER_MMCSD5_WKDEP_OFFSET 0x0160
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]507#define OMAP4430_PM_L4PER_MMCSD5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0160)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]508#define OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET 0x0164
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]509#define OMAP4430_RM_L4PER_MMCSD5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0164)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]510#define OMAP4_PM_L4PER_I2C5_WKDEP_OFFSET 0x0168
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]511#define OMAP4430_PM_L4PER_I2C5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0168)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]512#define OMAP4_RM_L4PER_I2C5_CONTEXT_OFFSET 0x016c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]513#define OMAP4430_RM_L4PER_I2C5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x016c)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]514#define OMAP4_RM_L4SEC_AES1_CONTEXT_OFFSET 0x01a4
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]515#define OMAP4430_RM_L4SEC_AES1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01a4)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]516#define OMAP4_RM_L4SEC_AES2_CONTEXT_OFFSET 0x01ac
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]517#define OMAP4430_RM_L4SEC_AES2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01ac)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]518#define OMAP4_RM_L4SEC_DES3DES_CONTEXT_OFFSET 0x01b4
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]519#define OMAP4430_RM_L4SEC_DES3DES_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01b4)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]520#define OMAP4_RM_L4SEC_PKAEIP29_CONTEXT_OFFSET 0x01bc
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]521#define OMAP4430_RM_L4SEC_PKAEIP29_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01bc)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]522#define OMAP4_RM_L4SEC_RNG_CONTEXT_OFFSET 0x01c4
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]523#define OMAP4430_RM_L4SEC_RNG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01c4)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]524#define OMAP4_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET 0x01cc
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]525#define OMAP4430_RM_L4SEC_SHA2MD51_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01cc)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]526#define OMAP4_RM_L4SEC_CRYPTODMA_CONTEXT_OFFSET 0x01dc
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]527#define OMAP4430_RM_L4SEC_CRYPTODMA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01dc)
Rajendra Nayakc1294042009-12-08 18:24:51 -0700[diff] [blame]528
529/* PRM.CEFUSE_PRM register offsets */
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]530#define OMAP4_PM_CEFUSE_PWRSTCTRL_OFFSET 0x0000
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]531#define OMAP4430_PM_CEFUSE_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_INST, 0x0000)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]532#define OMAP4_PM_CEFUSE_PWRSTST_OFFSET 0x0004
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]533#define OMAP4430_PM_CEFUSE_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_INST, 0x0004)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]534#define OMAP4_RM_CEFUSE_CEFUSE_CONTEXT_OFFSET 0x0024
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]535#define OMAP4430_RM_CEFUSE_CEFUSE_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_INST, 0x0024)
Rajendra Nayakc1294042009-12-08 18:24:51 -0700[diff] [blame]536
537/* PRM.WKUP_PRM register offsets */
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]538#define OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET 0x0024
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]539#define OMAP4430_RM_WKUP_L4WKUP_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0024)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]540#define OMAP4_RM_WKUP_WDT1_CONTEXT_OFFSET 0x002c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]541#define OMAP4430_RM_WKUP_WDT1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x002c)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]542#define OMAP4_PM_WKUP_WDT2_WKDEP_OFFSET 0x0030
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]543#define OMAP4430_PM_WKUP_WDT2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0030)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]544#define OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET 0x0034
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]545#define OMAP4430_RM_WKUP_WDT2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0034)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]546#define OMAP4_PM_WKUP_GPIO1_WKDEP_OFFSET 0x0038
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]547#define OMAP4430_PM_WKUP_GPIO1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0038)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]548#define OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET 0x003c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]549#define OMAP4430_RM_WKUP_GPIO1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x003c)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]550#define OMAP4_PM_WKUP_TIMER1_WKDEP_OFFSET 0x0040
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]551#define OMAP4430_PM_WKUP_TIMER1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0040)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]552#define OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET 0x0044
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]553#define OMAP4430_RM_WKUP_TIMER1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0044)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]554#define OMAP4_PM_WKUP_TIMER12_WKDEP_OFFSET 0x0048
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]555#define OMAP4430_PM_WKUP_TIMER12_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0048)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]556#define OMAP4_RM_WKUP_TIMER12_CONTEXT_OFFSET 0x004c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]557#define OMAP4430_RM_WKUP_TIMER12_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x004c)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]558#define OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET 0x0054
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]559#define OMAP4430_RM_WKUP_SYNCTIMER_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0054)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]560#define OMAP4_PM_WKUP_USIM_WKDEP_OFFSET 0x0058
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]561#define OMAP4430_PM_WKUP_USIM_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0058)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]562#define OMAP4_RM_WKUP_USIM_CONTEXT_OFFSET 0x005c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]563#define OMAP4430_RM_WKUP_USIM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x005c)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]564#define OMAP4_RM_WKUP_SARRAM_CONTEXT_OFFSET 0x0064
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]565#define OMAP4430_RM_WKUP_SARRAM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0064)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]566#define OMAP4_PM_WKUP_KEYBOARD_WKDEP_OFFSET 0x0078
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]567#define OMAP4430_PM_WKUP_KEYBOARD_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0078)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]568#define OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET 0x007c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]569#define OMAP4430_RM_WKUP_KEYBOARD_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x007c)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]570#define OMAP4_PM_WKUP_RTC_WKDEP_OFFSET 0x0080
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]571#define OMAP4430_PM_WKUP_RTC_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0080)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]572#define OMAP4_RM_WKUP_RTC_CONTEXT_OFFSET 0x0084
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]573#define OMAP4430_RM_WKUP_RTC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0084)
Rajendra Nayakc1294042009-12-08 18:24:51 -0700[diff] [blame]574
575/* PRM.WKUP_CM register offsets */
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]576#define OMAP4_CM_WKUP_CLKSTCTRL_OFFSET 0x0000
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]577#define OMAP4430_CM_WKUP_CLKSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0000)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]578#define OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET 0x0020
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]579#define OMAP4430_CM_WKUP_L4WKUP_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0020)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]580#define OMAP4_CM_WKUP_WDT1_CLKCTRL_OFFSET 0x0028
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]581#define OMAP4430_CM_WKUP_WDT1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0028)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]582#define OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET 0x0030
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]583#define OMAP4430_CM_WKUP_WDT2_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0030)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]584#define OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET 0x0038
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]585#define OMAP4430_CM_WKUP_GPIO1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0038)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]586#define OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET 0x0040
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]587#define OMAP4430_CM_WKUP_TIMER1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0040)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]588#define OMAP4_CM_WKUP_TIMER12_CLKCTRL_OFFSET 0x0048
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]589#define OMAP4430_CM_WKUP_TIMER12_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0048)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]590#define OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET 0x0050
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]591#define OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0050)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]592#define OMAP4_CM_WKUP_USIM_CLKCTRL_OFFSET 0x0058
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]593#define OMAP4430_CM_WKUP_USIM_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0058)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]594#define OMAP4_CM_WKUP_SARRAM_CLKCTRL_OFFSET 0x0060
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]595#define OMAP4430_CM_WKUP_SARRAM_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0060)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]596#define OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET 0x0078
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]597#define OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0078)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]598#define OMAP4_CM_WKUP_RTC_CLKCTRL_OFFSET 0x0080
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]599#define OMAP4430_CM_WKUP_RTC_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0080)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]600#define OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET 0x0088
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]601#define OMAP4430_CM_WKUP_BANDGAP_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0088)
Rajendra Nayakc1294042009-12-08 18:24:51 -0700[diff] [blame]602
603/* PRM.EMU_PRM register offsets */
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]604#define OMAP4_PM_EMU_PWRSTCTRL_OFFSET 0x0000
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]605#define OMAP4430_PM_EMU_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_INST, 0x0000)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]606#define OMAP4_PM_EMU_PWRSTST_OFFSET 0x0004
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]607#define OMAP4430_PM_EMU_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_INST, 0x0004)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]608#define OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET 0x0024
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]609#define OMAP4430_RM_EMU_DEBUGSS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_INST, 0x0024)
Rajendra Nayakc1294042009-12-08 18:24:51 -0700[diff] [blame]610
611/* PRM.EMU_CM register offsets */
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]612#define OMAP4_CM_EMU_CLKSTCTRL_OFFSET 0x0000
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]613#define OMAP4430_CM_EMU_CLKSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_INST, 0x0000)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]614#define OMAP4_CM_EMU_DYNAMICDEP_OFFSET 0x0008
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]615#define OMAP4430_CM_EMU_DYNAMICDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_INST, 0x0008)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]616#define OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET 0x0020
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]617#define OMAP4430_CM_EMU_DEBUGSS_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_INST, 0x0020)
Rajendra Nayakc1294042009-12-08 18:24:51 -0700[diff] [blame]618
619/* PRM.DEVICE_PRM register offsets */
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]620#define OMAP4_PRM_RSTCTRL_OFFSET 0x0000
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]621#define OMAP4430_PRM_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0000)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]622#define OMAP4_PRM_RSTST_OFFSET 0x0004
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]623#define OMAP4430_PRM_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0004)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]624#define OMAP4_PRM_RSTTIME_OFFSET 0x0008
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]625#define OMAP4430_PRM_RSTTIME OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0008)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]626#define OMAP4_PRM_CLKREQCTRL_OFFSET 0x000c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]627#define OMAP4430_PRM_CLKREQCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x000c)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]628#define OMAP4_PRM_VOLTCTRL_OFFSET 0x0010
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]629#define OMAP4430_PRM_VOLTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0010)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]630#define OMAP4_PRM_PWRREQCTRL_OFFSET 0x0014
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]631#define OMAP4430_PRM_PWRREQCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0014)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]632#define OMAP4_PRM_PSCON_COUNT_OFFSET 0x0018
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]633#define OMAP4430_PRM_PSCON_COUNT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0018)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]634#define OMAP4_PRM_IO_COUNT_OFFSET 0x001c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]635#define OMAP4430_PRM_IO_COUNT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x001c)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]636#define OMAP4_PRM_IO_PMCTRL_OFFSET 0x0020
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]637#define OMAP4430_PRM_IO_PMCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0020)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]638#define OMAP4_PRM_VOLTSETUP_WARMRESET_OFFSET 0x0024
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]639#define OMAP4430_PRM_VOLTSETUP_WARMRESET OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0024)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]640#define OMAP4_PRM_VOLTSETUP_CORE_OFF_OFFSET 0x0028
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]641#define OMAP4430_PRM_VOLTSETUP_CORE_OFF OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0028)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]642#define OMAP4_PRM_VOLTSETUP_MPU_OFF_OFFSET 0x002c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]643#define OMAP4430_PRM_VOLTSETUP_MPU_OFF OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x002c)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]644#define OMAP4_PRM_VOLTSETUP_IVA_OFF_OFFSET 0x0030
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]645#define OMAP4430_PRM_VOLTSETUP_IVA_OFF OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0030)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]646#define OMAP4_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET 0x0034
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]647#define OMAP4430_PRM_VOLTSETUP_CORE_RET_SLEEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0034)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]648#define OMAP4_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET 0x0038
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]649#define OMAP4430_PRM_VOLTSETUP_MPU_RET_SLEEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0038)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]650#define OMAP4_PRM_VOLTSETUP_IVA_RET_SLEEP_OFFSET 0x003c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]651#define OMAP4430_PRM_VOLTSETUP_IVA_RET_SLEEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x003c)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]652#define OMAP4_PRM_VP_CORE_CONFIG_OFFSET 0x0040
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]653#define OMAP4430_PRM_VP_CORE_CONFIG OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0040)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]654#define OMAP4_PRM_VP_CORE_STATUS_OFFSET 0x0044
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]655#define OMAP4430_PRM_VP_CORE_STATUS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0044)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]656#define OMAP4_PRM_VP_CORE_VLIMITTO_OFFSET 0x0048
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]657#define OMAP4430_PRM_VP_CORE_VLIMITTO OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0048)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]658#define OMAP4_PRM_VP_CORE_VOLTAGE_OFFSET 0x004c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]659#define OMAP4430_PRM_VP_CORE_VOLTAGE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x004c)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]660#define OMAP4_PRM_VP_CORE_VSTEPMAX_OFFSET 0x0050
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]661#define OMAP4430_PRM_VP_CORE_VSTEPMAX OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0050)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]662#define OMAP4_PRM_VP_CORE_VSTEPMIN_OFFSET 0x0054
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]663#define OMAP4430_PRM_VP_CORE_VSTEPMIN OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0054)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]664#define OMAP4_PRM_VP_MPU_CONFIG_OFFSET 0x0058
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]665#define OMAP4430_PRM_VP_MPU_CONFIG OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0058)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]666#define OMAP4_PRM_VP_MPU_STATUS_OFFSET 0x005c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]667#define OMAP4430_PRM_VP_MPU_STATUS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x005c)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]668#define OMAP4_PRM_VP_MPU_VLIMITTO_OFFSET 0x0060
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]669#define OMAP4430_PRM_VP_MPU_VLIMITTO OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0060)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]670#define OMAP4_PRM_VP_MPU_VOLTAGE_OFFSET 0x0064
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]671#define OMAP4430_PRM_VP_MPU_VOLTAGE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0064)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]672#define OMAP4_PRM_VP_MPU_VSTEPMAX_OFFSET 0x0068
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]673#define OMAP4430_PRM_VP_MPU_VSTEPMAX OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0068)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]674#define OMAP4_PRM_VP_MPU_VSTEPMIN_OFFSET 0x006c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]675#define OMAP4430_PRM_VP_MPU_VSTEPMIN OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x006c)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]676#define OMAP4_PRM_VP_IVA_CONFIG_OFFSET 0x0070
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]677#define OMAP4430_PRM_VP_IVA_CONFIG OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0070)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]678#define OMAP4_PRM_VP_IVA_STATUS_OFFSET 0x0074
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]679#define OMAP4430_PRM_VP_IVA_STATUS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0074)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]680#define OMAP4_PRM_VP_IVA_VLIMITTO_OFFSET 0x0078
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]681#define OMAP4430_PRM_VP_IVA_VLIMITTO OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0078)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]682#define OMAP4_PRM_VP_IVA_VOLTAGE_OFFSET 0x007c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]683#define OMAP4430_PRM_VP_IVA_VOLTAGE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x007c)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]684#define OMAP4_PRM_VP_IVA_VSTEPMAX_OFFSET 0x0080
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]685#define OMAP4430_PRM_VP_IVA_VSTEPMAX OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0080)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]686#define OMAP4_PRM_VP_IVA_VSTEPMIN_OFFSET 0x0084
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]687#define OMAP4430_PRM_VP_IVA_VSTEPMIN OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0084)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]688#define OMAP4_PRM_VC_SMPS_SA_OFFSET 0x0088
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]689#define OMAP4430_PRM_VC_SMPS_SA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0088)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]690#define OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET 0x008c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]691#define OMAP4430_PRM_VC_VAL_SMPS_RA_VOL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x008c)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]692#define OMAP4_PRM_VC_VAL_SMPS_RA_CMD_OFFSET 0x0090
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]693#define OMAP4430_PRM_VC_VAL_SMPS_RA_CMD OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0090)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]694#define OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET 0x0094
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]695#define OMAP4430_PRM_VC_VAL_CMD_VDD_CORE_L OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0094)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]696#define OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET 0x0098
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]697#define OMAP4430_PRM_VC_VAL_CMD_VDD_MPU_L OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0098)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]698#define OMAP4_PRM_VC_VAL_CMD_VDD_IVA_L_OFFSET 0x009c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]699#define OMAP4430_PRM_VC_VAL_CMD_VDD_IVA_L OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x009c)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]700#define OMAP4_PRM_VC_VAL_BYPASS_OFFSET 0x00a0
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]701#define OMAP4430_PRM_VC_VAL_BYPASS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a0)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]702#define OMAP4_PRM_VC_CFG_CHANNEL_OFFSET 0x00a4
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]703#define OMAP4430_PRM_VC_CFG_CHANNEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a4)
Benoit Coussonad98a182011-07-09 19:15:04 -0600[diff] [blame]704#define OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET 0x00a8
705#define OMAP4430_PRM_VC_CFG_I2C_MODE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a8)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]706#define OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET 0x00ac
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]707#define OMAP4430_PRM_VC_CFG_I2C_CLK OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ac)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]708#define OMAP4_PRM_SRAM_COUNT_OFFSET 0x00b0
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]709#define OMAP4430_PRM_SRAM_COUNT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00b0)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]710#define OMAP4_PRM_SRAM_WKUP_SETUP_OFFSET 0x00b4
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]711#define OMAP4430_PRM_SRAM_WKUP_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00b4)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]712#define OMAP4_PRM_LDO_SRAM_CORE_SETUP_OFFSET 0x00b8
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]713#define OMAP4430_PRM_LDO_SRAM_CORE_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00b8)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]714#define OMAP4_PRM_LDO_SRAM_CORE_CTRL_OFFSET 0x00bc
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]715#define OMAP4430_PRM_LDO_SRAM_CORE_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00bc)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]716#define OMAP4_PRM_LDO_SRAM_MPU_SETUP_OFFSET 0x00c0
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]717#define OMAP4430_PRM_LDO_SRAM_MPU_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00c0)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]718#define OMAP4_PRM_LDO_SRAM_MPU_CTRL_OFFSET 0x00c4
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]719#define OMAP4430_PRM_LDO_SRAM_MPU_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00c4)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]720#define OMAP4_PRM_LDO_SRAM_IVA_SETUP_OFFSET 0x00c8
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]721#define OMAP4430_PRM_LDO_SRAM_IVA_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00c8)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]722#define OMAP4_PRM_LDO_SRAM_IVA_CTRL_OFFSET 0x00cc
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]723#define OMAP4430_PRM_LDO_SRAM_IVA_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00cc)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]724#define OMAP4_PRM_LDO_ABB_MPU_SETUP_OFFSET 0x00d0
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]725#define OMAP4430_PRM_LDO_ABB_MPU_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00d0)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]726#define OMAP4_PRM_LDO_ABB_MPU_CTRL_OFFSET 0x00d4
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]727#define OMAP4430_PRM_LDO_ABB_MPU_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00d4)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]728#define OMAP4_PRM_LDO_ABB_IVA_SETUP_OFFSET 0x00d8
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]729#define OMAP4430_PRM_LDO_ABB_IVA_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00d8)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]730#define OMAP4_PRM_LDO_ABB_IVA_CTRL_OFFSET 0x00dc
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]731#define OMAP4430_PRM_LDO_ABB_IVA_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00dc)
Rajendra Nayakfdd4f402010-09-27 14:02:56 -0600[diff] [blame]732#define OMAP4_PRM_LDO_BANDGAP_SETUP_OFFSET 0x00e0
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]733#define OMAP4430_PRM_LDO_BANDGAP_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00e0)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]734#define OMAP4_PRM_DEVICE_OFF_CTRL_OFFSET 0x00e4
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]735#define OMAP4430_PRM_DEVICE_OFF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00e4)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]736#define OMAP4_PRM_PHASE1_CNDP_OFFSET 0x00e8
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]737#define OMAP4430_PRM_PHASE1_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00e8)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]738#define OMAP4_PRM_PHASE2A_CNDP_OFFSET 0x00ec
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]739#define OMAP4430_PRM_PHASE2A_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ec)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]740#define OMAP4_PRM_PHASE2B_CNDP_OFFSET 0x00f0
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]741#define OMAP4430_PRM_PHASE2B_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f0)
Benoit Coussonad98a182011-07-09 19:15:04 -0600[diff] [blame]742#define OMAP4_PRM_MODEM_IF_CTRL_OFFSET 0x00f4
743#define OMAP4430_PRM_MODEM_IF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f4)
Rajendra Nayakfdd4f402010-09-27 14:02:56 -0600[diff] [blame]744#define OMAP4_PRM_VC_ERRST_OFFSET 0x00f8
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]745#define OMAP4430_PRM_VC_ERRST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f8)
Rajendra Nayakc1294042009-12-08 18:24:51 -0700[diff] [blame]746
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]747/* Function prototypes */
748# ifndef __ASSEMBLER__
Rajendra Nayakc1294042009-12-08 18:24:51 -0700[diff] [blame]749
Paul Walmsley2ace8312010-12-21 21:05:14 -0700[diff] [blame]750extern u32 omap4_prm_read_inst_reg(s16 inst, u16 idx);
751extern void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 idx);
752extern u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
Rajendra Nayakc1294042009-12-08 18:24:51 -0700[diff] [blame]753
Kevin Hilman58aaa592011-03-28 10:52:04 -0700[diff] [blame]754/* OMAP4-specific VP functions */
755u32 omap4_prm_vp_check_txdone(u8 vp_id);
756void omap4_prm_vp_clear_txdone(u8 vp_id);
757
Kevin Hilman4bb73ad2011-03-28 10:25:12 -0700[diff] [blame]758/*
759 * OMAP4 access functions for voltage controller (VC) and
760 * voltage proccessor (VP) in the PRM.
761 */
762extern u32 omap4_prm_vcvp_read(u8 offset);
763extern void omap4_prm_vcvp_write(u32 val, u8 offset);
764extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
765
Rajendra Nayakdea62002012-06-22 08:40:03 -0600[diff] [blame]766extern void omap44xx_prm_reconfigure_io_chain(void);
767
Paul Walmsley26c98c52011-12-16 14:36:58 -0700[diff] [blame]768/* PRM interrupt-related functions */
769extern void omap44xx_prm_read_pending_irqs(unsigned long *events);
770extern void omap44xx_prm_ocp_barrier(void);
Tero Kristo91285b62011-12-16 14:36:58 -0700[diff] [blame]771extern void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask);
772extern void omap44xx_prm_restore_irqen(u32 *saved_mask);
Paul Walmsley26c98c52011-12-16 14:36:58 -0700[diff] [blame]773
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]774# endif
Rajendra Nayakc1294042009-12-08 18:24:51 -0700[diff] [blame]775
Rajendra Nayakc1294042009-12-08 18:24:51 -0700[diff] [blame]776#endif