Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is subject to the terms and conditions of the GNU General Public |
| 3 | * License. See the file "COPYING" in the main directory of this archive |
| 4 | * for more details. |
| 5 | * |
| 6 | * Copyright (C) 1994, 1995 Waldorf GmbH |
Ralf Baechle | 966f440 | 2006-03-15 11:36:31 +0000 | [diff] [blame] | 7 | * Copyright (C) 1994 - 2000, 06 Ralf Baechle |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8 | * Copyright (C) 1999, 2000 Silicon Graphics, Inc. |
| 9 | * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved. |
| 10 | * Author: Maciej W. Rozycki <macro@mips.com> |
| 11 | */ |
| 12 | #ifndef _ASM_IO_H |
| 13 | #define _ASM_IO_H |
| 14 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15 | #include <linux/compiler.h> |
| 16 | #include <linux/kernel.h> |
| 17 | #include <linux/types.h> |
| 18 | |
| 19 | #include <asm/addrspace.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 20 | #include <asm/byteorder.h> |
| 21 | #include <asm/cpu.h> |
| 22 | #include <asm/cpu-features.h> |
Ralf Baechle | 140c172 | 2006-12-07 15:35:43 +0100 | [diff] [blame] | 23 | #include <asm-generic/iomap.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 24 | #include <asm/page.h> |
| 25 | #include <asm/pgtable-bits.h> |
| 26 | #include <asm/processor.h> |
Ralf Baechle | fe00f94 | 2005-03-01 19:22:29 +0000 | [diff] [blame] | 27 | #include <asm/string.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 28 | |
Maciej W. Rozycki | c3455b0 | 2005-06-30 10:48:40 +0000 | [diff] [blame] | 29 | #include <ioremap.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 30 | #include <mangle-port.h> |
| 31 | |
| 32 | /* |
| 33 | * Slowdown I/O port space accesses for antique hardware. |
| 34 | */ |
| 35 | #undef CONF_SLOWDOWN_IO |
| 36 | |
| 37 | /* |
Maciej W. Rozycki | 4912ba7 | 2005-02-22 21:49:17 +0000 | [diff] [blame] | 38 | * Raw operations are never swapped in software. OTOH values that raw |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 39 | * operations are working on may or may not have been swapped by the bus |
| 40 | * hardware. An example use would be for flash memory that's used for |
| 41 | * execute in place. |
| 42 | */ |
Atsushi Nemoto | a843313 | 2006-02-17 01:36:24 +0900 | [diff] [blame] | 43 | # define __raw_ioswabb(a,x) (x) |
| 44 | # define __raw_ioswabw(a,x) (x) |
| 45 | # define __raw_ioswabl(a,x) (x) |
| 46 | # define __raw_ioswabq(a,x) (x) |
| 47 | # define ____raw_ioswabq(a,x) (x) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 48 | |
Atsushi Nemoto | a843313 | 2006-02-17 01:36:24 +0900 | [diff] [blame] | 49 | /* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 50 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 51 | #define IO_SPACE_LIMIT 0xffff |
| 52 | |
| 53 | /* |
| 54 | * On MIPS I/O ports are memory mapped, so we access them using normal |
| 55 | * load/store instructions. mips_io_port_base is the virtual address to |
| 56 | * which all ports are being mapped. For sake of efficiency some code |
| 57 | * assumes that this is an address that can be loaded with a single lui |
| 58 | * instruction, so the lower 16 bits must be zero. Should be true on |
| 59 | * on any sane architecture; generic code does not use this assumption. |
| 60 | */ |
| 61 | extern const unsigned long mips_io_port_base; |
| 62 | |
Ralf Baechle | 966f440 | 2006-03-15 11:36:31 +0000 | [diff] [blame] | 63 | /* |
| 64 | * Gcc will generate code to load the value of mips_io_port_base after each |
| 65 | * function call which may be fairly wasteful in some cases. So we don't |
| 66 | * play quite by the book. We tell gcc mips_io_port_base is a long variable |
| 67 | * which solves the code generation issue. Now we need to violate the |
| 68 | * aliasing rules a little to make initialization possible and finally we |
| 69 | * will need the barrier() to fight side effects of the aliasing chat. |
| 70 | * This trickery will eventually collapse under gcc's optimizer. Oh well. |
| 71 | */ |
| 72 | static inline void set_io_port_base(unsigned long base) |
| 73 | { |
| 74 | * (unsigned long *) &mips_io_port_base = base; |
| 75 | barrier(); |
| 76 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 77 | |
| 78 | /* |
| 79 | * Thanks to James van Artsdalen for a better timing-fix than |
| 80 | * the two short jumps: using outb's to a nonexistent port seems |
| 81 | * to guarantee better timings even on fast machines. |
| 82 | * |
| 83 | * On the other hand, I'd like to be sure of a non-existent port: |
| 84 | * I feel a bit unsafe about using 0x80 (should be safe, though) |
| 85 | * |
| 86 | * Linus |
| 87 | * |
| 88 | */ |
| 89 | |
| 90 | #define __SLOW_DOWN_IO \ |
| 91 | __asm__ __volatile__( \ |
| 92 | "sb\t$0,0x80(%0)" \ |
| 93 | : : "r" (mips_io_port_base)); |
| 94 | |
| 95 | #ifdef CONF_SLOWDOWN_IO |
| 96 | #ifdef REALLY_SLOW_IO |
| 97 | #define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; } |
| 98 | #else |
| 99 | #define SLOW_DOWN_IO __SLOW_DOWN_IO |
| 100 | #endif |
| 101 | #else |
| 102 | #define SLOW_DOWN_IO |
| 103 | #endif |
| 104 | |
| 105 | /* |
| 106 | * virt_to_phys - map virtual addresses to physical |
| 107 | * @address: address to remap |
| 108 | * |
| 109 | * The returned physical address is the physical (CPU) mapping for |
| 110 | * the memory address given. It is only valid to use this function on |
| 111 | * addresses directly mapped or allocated via kmalloc. |
| 112 | * |
| 113 | * This function does not give bus mappings for DMA transfers. In |
| 114 | * almost all conceivable cases a device driver should not be using |
| 115 | * this function |
| 116 | */ |
Franck Bui-Huu | 99e3b94 | 2006-10-19 13:19:59 +0200 | [diff] [blame] | 117 | static inline unsigned long virt_to_phys(volatile const void *address) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 118 | { |
Franck Bui-Huu | 6f284a2 | 2007-01-10 09:44:05 +0100 | [diff] [blame] | 119 | return (unsigned long)address - PAGE_OFFSET + PHYS_OFFSET; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 120 | } |
| 121 | |
| 122 | /* |
| 123 | * phys_to_virt - map physical address to virtual |
| 124 | * @address: address to remap |
| 125 | * |
| 126 | * The returned virtual address is a current CPU mapping for |
| 127 | * the memory address given. It is only valid to use this function on |
| 128 | * addresses that have a kernel mapping |
| 129 | * |
| 130 | * This function does not handle bus mappings for DMA transfers. In |
| 131 | * almost all conceivable cases a device driver should not be using |
| 132 | * this function |
| 133 | */ |
| 134 | static inline void * phys_to_virt(unsigned long address) |
| 135 | { |
Franck Bui-Huu | 6f284a2 | 2007-01-10 09:44:05 +0100 | [diff] [blame] | 136 | return (void *)(address + PAGE_OFFSET - PHYS_OFFSET); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 137 | } |
| 138 | |
| 139 | /* |
| 140 | * ISA I/O bus memory addresses are 1:1 with the physical address. |
| 141 | */ |
| 142 | static inline unsigned long isa_virt_to_bus(volatile void * address) |
| 143 | { |
| 144 | return (unsigned long)address - PAGE_OFFSET; |
| 145 | } |
| 146 | |
| 147 | static inline void * isa_bus_to_virt(unsigned long address) |
| 148 | { |
| 149 | return (void *)(address + PAGE_OFFSET); |
| 150 | } |
| 151 | |
| 152 | #define isa_page_to_bus page_to_phys |
| 153 | |
| 154 | /* |
| 155 | * However PCI ones are not necessarily 1:1 and therefore these interfaces |
| 156 | * are forbidden in portable PCI drivers. |
| 157 | * |
| 158 | * Allow them for x86 for legacy drivers, though. |
| 159 | */ |
| 160 | #define virt_to_bus virt_to_phys |
| 161 | #define bus_to_virt phys_to_virt |
| 162 | |
| 163 | /* |
| 164 | * isa_slot_offset is the address where E(ISA) busaddress 0 is mapped |
| 165 | * for the processor. This implies the assumption that there is only |
| 166 | * one of these busses. |
| 167 | */ |
| 168 | extern unsigned long isa_slot_offset; |
| 169 | |
| 170 | /* |
| 171 | * Change "struct page" to physical address. |
| 172 | */ |
| 173 | #define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT) |
| 174 | |
Ralf Baechle | 0f04afb | 2005-03-01 10:38:58 +0000 | [diff] [blame] | 175 | extern void __iomem * __ioremap(phys_t offset, phys_t size, unsigned long flags); |
Ralf Baechle | d89e36d | 2006-10-19 14:21:47 +0100 | [diff] [blame] | 176 | extern void __iounmap(const volatile void __iomem *addr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 177 | |
Ralf Baechle | 0f04afb | 2005-03-01 10:38:58 +0000 | [diff] [blame] | 178 | static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 179 | unsigned long flags) |
| 180 | { |
Atsushi Nemoto | 5ddcb3c | 2007-06-26 01:14:01 +0900 | [diff] [blame] | 181 | void __iomem *addr = plat_ioremap(offset, size, flags); |
| 182 | |
| 183 | if (addr) |
| 184 | return addr; |
| 185 | |
Maciej W. Rozycki | c3455b0 | 2005-06-30 10:48:40 +0000 | [diff] [blame] | 186 | #define __IS_LOW512(addr) (!((phys_t)(addr) & (phys_t) ~0x1fffffffULL)) |
| 187 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 188 | if (cpu_has_64bit_addresses) { |
| 189 | u64 base = UNCAC_BASE; |
| 190 | |
| 191 | /* |
| 192 | * R10000 supports a 2 bit uncached attribute therefore |
| 193 | * UNCAC_BASE may not equal IO_BASE. |
| 194 | */ |
| 195 | if (flags == _CACHE_UNCACHED) |
| 196 | base = (u64) IO_BASE; |
Ralf Baechle | fe00f94 | 2005-03-01 19:22:29 +0000 | [diff] [blame] | 197 | return (void __iomem *) (unsigned long) (base + offset); |
Maciej W. Rozycki | c3455b0 | 2005-06-30 10:48:40 +0000 | [diff] [blame] | 198 | } else if (__builtin_constant_p(offset) && |
| 199 | __builtin_constant_p(size) && __builtin_constant_p(flags)) { |
| 200 | phys_t phys_addr, last_addr; |
| 201 | |
| 202 | phys_addr = fixup_bigphys_addr(offset, size); |
| 203 | |
| 204 | /* Don't allow wraparound or zero size. */ |
| 205 | last_addr = phys_addr + size - 1; |
| 206 | if (!size || last_addr < phys_addr) |
| 207 | return NULL; |
| 208 | |
| 209 | /* |
| 210 | * Map uncached objects in the low 512MB of address |
| 211 | * space using KSEG1. |
| 212 | */ |
| 213 | if (__IS_LOW512(phys_addr) && __IS_LOW512(last_addr) && |
| 214 | flags == _CACHE_UNCACHED) |
Atsushi Nemoto | c0cf500 | 2007-07-11 23:12:00 +0900 | [diff] [blame] | 215 | return (void __iomem *) |
| 216 | (unsigned long)CKSEG1ADDR(phys_addr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 217 | } |
| 218 | |
| 219 | return __ioremap(offset, size, flags); |
Maciej W. Rozycki | c3455b0 | 2005-06-30 10:48:40 +0000 | [diff] [blame] | 220 | |
| 221 | #undef __IS_LOW512 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 222 | } |
| 223 | |
| 224 | /* |
| 225 | * ioremap - map bus memory into CPU space |
| 226 | * @offset: bus address of the memory |
| 227 | * @size: size of the resource to map |
| 228 | * |
| 229 | * ioremap performs a platform specific sequence of operations to |
| 230 | * make bus memory CPU accessible via the readb/readw/readl/writeb/ |
| 231 | * writew/writel functions and the other mmio helpers. The returned |
| 232 | * address is not guaranteed to be usable directly as a virtual |
| 233 | * address. |
| 234 | */ |
| 235 | #define ioremap(offset, size) \ |
| 236 | __ioremap_mode((offset), (size), _CACHE_UNCACHED) |
| 237 | |
| 238 | /* |
| 239 | * ioremap_nocache - map bus memory into CPU space |
| 240 | * @offset: bus address of the memory |
| 241 | * @size: size of the resource to map |
| 242 | * |
| 243 | * ioremap_nocache performs a platform specific sequence of operations to |
| 244 | * make bus memory CPU accessible via the readb/readw/readl/writeb/ |
| 245 | * writew/writel functions and the other mmio helpers. The returned |
| 246 | * address is not guaranteed to be usable directly as a virtual |
| 247 | * address. |
| 248 | * |
| 249 | * This version of ioremap ensures that the memory is marked uncachable |
| 250 | * on the CPU as well as honouring existing caching rules from things like |
| 251 | * the PCI bus. Note that there are other caches and buffers on many |
| 252 | * busses. In paticular driver authors should read up on PCI writes |
| 253 | * |
| 254 | * It's useful if some control registers are in such an area and |
| 255 | * write combining or read caching is not desirable: |
| 256 | */ |
| 257 | #define ioremap_nocache(offset, size) \ |
| 258 | __ioremap_mode((offset), (size), _CACHE_UNCACHED) |
| 259 | |
| 260 | /* |
Ralf Baechle | 778e2ac | 2006-02-28 17:04:20 +0000 | [diff] [blame] | 261 | * ioremap_cachable - map bus memory into CPU space |
| 262 | * @offset: bus address of the memory |
| 263 | * @size: size of the resource to map |
| 264 | * |
| 265 | * ioremap_nocache performs a platform specific sequence of operations to |
| 266 | * make bus memory CPU accessible via the readb/readw/readl/writeb/ |
| 267 | * writew/writel functions and the other mmio helpers. The returned |
| 268 | * address is not guaranteed to be usable directly as a virtual |
| 269 | * address. |
| 270 | * |
| 271 | * This version of ioremap ensures that the memory is marked cachable by |
| 272 | * the CPU. Also enables full write-combining. Useful for some |
| 273 | * memory-like regions on I/O busses. |
| 274 | */ |
| 275 | #define ioremap_cachable(offset, size) \ |
| 276 | __ioremap_mode((offset), (size), PAGE_CACHABLE_DEFAULT) |
| 277 | |
| 278 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 279 | * These two are MIPS specific ioremap variant. ioremap_cacheable_cow |
| 280 | * requests a cachable mapping, ioremap_uncached_accelerated requests a |
| 281 | * mapping using the uncached accelerated mode which isn't supported on |
| 282 | * all processors. |
| 283 | */ |
| 284 | #define ioremap_cacheable_cow(offset, size) \ |
| 285 | __ioremap_mode((offset), (size), _CACHE_CACHABLE_COW) |
| 286 | #define ioremap_uncached_accelerated(offset, size) \ |
| 287 | __ioremap_mode((offset), (size), _CACHE_UNCACHED_ACCELERATED) |
| 288 | |
Ralf Baechle | d89e36d | 2006-10-19 14:21:47 +0100 | [diff] [blame] | 289 | static inline void iounmap(const volatile void __iomem *addr) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 290 | { |
Atsushi Nemoto | 5ddcb3c | 2007-06-26 01:14:01 +0900 | [diff] [blame] | 291 | if (plat_iounmap(addr)) |
| 292 | return; |
| 293 | |
Maciej W. Rozycki | c3455b0 | 2005-06-30 10:48:40 +0000 | [diff] [blame] | 294 | #define __IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1) |
| 295 | |
| 296 | if (cpu_has_64bit_addresses || |
| 297 | (__builtin_constant_p(addr) && __IS_KSEG1(addr))) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 298 | return; |
| 299 | |
| 300 | __iounmap(addr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 301 | |
Maciej W. Rozycki | c3455b0 | 2005-06-30 10:48:40 +0000 | [diff] [blame] | 302 | #undef __IS_KSEG1 |
| 303 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 304 | |
| 305 | #define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq) \ |
| 306 | \ |
| 307 | static inline void pfx##write##bwlq(type val, \ |
| 308 | volatile void __iomem *mem) \ |
| 309 | { \ |
| 310 | volatile type *__mem; \ |
| 311 | type __val; \ |
| 312 | \ |
| 313 | __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \ |
| 314 | \ |
Atsushi Nemoto | a843313 | 2006-02-17 01:36:24 +0900 | [diff] [blame] | 315 | __val = pfx##ioswab##bwlq(__mem, val); \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 316 | \ |
| 317 | if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \ |
| 318 | *__mem = __val; \ |
| 319 | else if (cpu_has_64bits) { \ |
| 320 | unsigned long __flags; \ |
| 321 | type __tmp; \ |
| 322 | \ |
| 323 | if (irq) \ |
| 324 | local_irq_save(__flags); \ |
| 325 | __asm__ __volatile__( \ |
| 326 | ".set mips3" "\t\t# __writeq""\n\t" \ |
| 327 | "dsll32 %L0, %L0, 0" "\n\t" \ |
| 328 | "dsrl32 %L0, %L0, 0" "\n\t" \ |
| 329 | "dsll32 %M0, %M0, 0" "\n\t" \ |
| 330 | "or %L0, %L0, %M0" "\n\t" \ |
| 331 | "sd %L0, %2" "\n\t" \ |
| 332 | ".set mips0" "\n" \ |
| 333 | : "=r" (__tmp) \ |
| 334 | : "0" (__val), "m" (*__mem)); \ |
| 335 | if (irq) \ |
| 336 | local_irq_restore(__flags); \ |
| 337 | } else \ |
| 338 | BUG(); \ |
| 339 | } \ |
| 340 | \ |
Atsushi Nemoto | b887d3f | 2006-02-09 00:57:44 +0900 | [diff] [blame] | 341 | static inline type pfx##read##bwlq(const volatile void __iomem *mem) \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 342 | { \ |
| 343 | volatile type *__mem; \ |
| 344 | type __val; \ |
| 345 | \ |
| 346 | __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \ |
| 347 | \ |
| 348 | if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \ |
| 349 | __val = *__mem; \ |
| 350 | else if (cpu_has_64bits) { \ |
| 351 | unsigned long __flags; \ |
| 352 | \ |
Thiemo Seufer | 049b13c | 2005-02-21 11:44:31 +0000 | [diff] [blame] | 353 | if (irq) \ |
| 354 | local_irq_save(__flags); \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 355 | __asm__ __volatile__( \ |
| 356 | ".set mips3" "\t\t# __readq" "\n\t" \ |
| 357 | "ld %L0, %1" "\n\t" \ |
| 358 | "dsra32 %M0, %L0, 0" "\n\t" \ |
| 359 | "sll %L0, %L0, 0" "\n\t" \ |
| 360 | ".set mips0" "\n" \ |
| 361 | : "=r" (__val) \ |
| 362 | : "m" (*__mem)); \ |
Thiemo Seufer | 049b13c | 2005-02-21 11:44:31 +0000 | [diff] [blame] | 363 | if (irq) \ |
| 364 | local_irq_restore(__flags); \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 365 | } else { \ |
| 366 | __val = 0; \ |
| 367 | BUG(); \ |
| 368 | } \ |
| 369 | \ |
Atsushi Nemoto | a843313 | 2006-02-17 01:36:24 +0900 | [diff] [blame] | 370 | return pfx##ioswab##bwlq(__mem, __val); \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 371 | } |
| 372 | |
| 373 | #define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow) \ |
| 374 | \ |
| 375 | static inline void pfx##out##bwlq##p(type val, unsigned long port) \ |
| 376 | { \ |
| 377 | volatile type *__addr; \ |
| 378 | type __val; \ |
| 379 | \ |
Atsushi Nemoto | a843313 | 2006-02-17 01:36:24 +0900 | [diff] [blame] | 380 | __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 381 | \ |
Atsushi Nemoto | a843313 | 2006-02-17 01:36:24 +0900 | [diff] [blame] | 382 | __val = pfx##ioswab##bwlq(__addr, val); \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 383 | \ |
Ralf Baechle | 9d58f30 | 2005-09-23 20:02:38 +0000 | [diff] [blame] | 384 | /* Really, we want this to be atomic */ \ |
| 385 | BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \ |
| 386 | \ |
| 387 | *__addr = __val; \ |
| 388 | slow; \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 389 | } \ |
| 390 | \ |
| 391 | static inline type pfx##in##bwlq##p(unsigned long port) \ |
| 392 | { \ |
| 393 | volatile type *__addr; \ |
| 394 | type __val; \ |
| 395 | \ |
Atsushi Nemoto | a843313 | 2006-02-17 01:36:24 +0900 | [diff] [blame] | 396 | __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 397 | \ |
Ralf Baechle | 9d58f30 | 2005-09-23 20:02:38 +0000 | [diff] [blame] | 398 | BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \ |
| 399 | \ |
| 400 | __val = *__addr; \ |
| 401 | slow; \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 402 | \ |
Atsushi Nemoto | a843313 | 2006-02-17 01:36:24 +0900 | [diff] [blame] | 403 | return pfx##ioswab##bwlq(__addr, __val); \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 404 | } |
| 405 | |
| 406 | #define __BUILD_MEMORY_PFX(bus, bwlq, type) \ |
| 407 | \ |
| 408 | __BUILD_MEMORY_SINGLE(bus, bwlq, type, 1) |
| 409 | |
Ralf Baechle | 9d58f30 | 2005-09-23 20:02:38 +0000 | [diff] [blame] | 410 | #define BUILDIO_MEM(bwlq, type) \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 411 | \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 412 | __BUILD_MEMORY_PFX(__raw_, bwlq, type) \ |
Maciej W. Rozycki | 4912ba7 | 2005-02-22 21:49:17 +0000 | [diff] [blame] | 413 | __BUILD_MEMORY_PFX(, bwlq, type) \ |
Al Viro | 290f10a | 2005-12-07 23:12:54 -0500 | [diff] [blame] | 414 | __BUILD_MEMORY_PFX(__mem_, bwlq, type) \ |
Ralf Baechle | 9d58f30 | 2005-09-23 20:02:38 +0000 | [diff] [blame] | 415 | |
| 416 | BUILDIO_MEM(b, u8) |
| 417 | BUILDIO_MEM(w, u16) |
| 418 | BUILDIO_MEM(l, u32) |
| 419 | BUILDIO_MEM(q, u64) |
| 420 | |
| 421 | #define __BUILD_IOPORT_PFX(bus, bwlq, type) \ |
| 422 | __BUILD_IOPORT_SINGLE(bus, bwlq, type, ,) \ |
| 423 | __BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO) |
| 424 | |
| 425 | #define BUILDIO_IOPORT(bwlq, type) \ |
| 426 | __BUILD_IOPORT_PFX(, bwlq, type) \ |
Al Viro | 290f10a | 2005-12-07 23:12:54 -0500 | [diff] [blame] | 427 | __BUILD_IOPORT_PFX(__mem_, bwlq, type) |
Ralf Baechle | 9d58f30 | 2005-09-23 20:02:38 +0000 | [diff] [blame] | 428 | |
| 429 | BUILDIO_IOPORT(b, u8) |
| 430 | BUILDIO_IOPORT(w, u16) |
| 431 | BUILDIO_IOPORT(l, u32) |
| 432 | #ifdef CONFIG_64BIT |
| 433 | BUILDIO_IOPORT(q, u64) |
| 434 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 435 | |
| 436 | #define __BUILDIO(bwlq, type) \ |
| 437 | \ |
Maciej W. Rozycki | 4912ba7 | 2005-02-22 21:49:17 +0000 | [diff] [blame] | 438 | __BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 0) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 439 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 440 | __BUILDIO(q, u64) |
| 441 | |
| 442 | #define readb_relaxed readb |
| 443 | #define readw_relaxed readw |
| 444 | #define readl_relaxed readl |
| 445 | #define readq_relaxed readq |
| 446 | |
| 447 | /* |
| 448 | * Some code tests for these symbols |
| 449 | */ |
| 450 | #define readq readq |
| 451 | #define writeq writeq |
| 452 | |
| 453 | #define __BUILD_MEMORY_STRING(bwlq, type) \ |
| 454 | \ |
Arnaud Giersch | 99289a4 | 2005-11-13 00:38:18 +0100 | [diff] [blame] | 455 | static inline void writes##bwlq(volatile void __iomem *mem, \ |
| 456 | const void *addr, unsigned int count) \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 457 | { \ |
Arnaud Giersch | 99289a4 | 2005-11-13 00:38:18 +0100 | [diff] [blame] | 458 | const volatile type *__addr = addr; \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 459 | \ |
| 460 | while (count--) { \ |
Al Viro | 290f10a | 2005-12-07 23:12:54 -0500 | [diff] [blame] | 461 | __mem_write##bwlq(*__addr, mem); \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 462 | __addr++; \ |
| 463 | } \ |
| 464 | } \ |
| 465 | \ |
| 466 | static inline void reads##bwlq(volatile void __iomem *mem, void *addr, \ |
| 467 | unsigned int count) \ |
| 468 | { \ |
| 469 | volatile type *__addr = addr; \ |
| 470 | \ |
| 471 | while (count--) { \ |
Al Viro | 290f10a | 2005-12-07 23:12:54 -0500 | [diff] [blame] | 472 | *__addr = __mem_read##bwlq(mem); \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 473 | __addr++; \ |
| 474 | } \ |
| 475 | } |
| 476 | |
| 477 | #define __BUILD_IOPORT_STRING(bwlq, type) \ |
| 478 | \ |
Ralf Baechle | ecba36d | 2005-04-18 14:54:43 +0000 | [diff] [blame] | 479 | static inline void outs##bwlq(unsigned long port, const void *addr, \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 480 | unsigned int count) \ |
| 481 | { \ |
Ralf Baechle | ecba36d | 2005-04-18 14:54:43 +0000 | [diff] [blame] | 482 | const volatile type *__addr = addr; \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 483 | \ |
| 484 | while (count--) { \ |
Al Viro | 290f10a | 2005-12-07 23:12:54 -0500 | [diff] [blame] | 485 | __mem_out##bwlq(*__addr, port); \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 486 | __addr++; \ |
| 487 | } \ |
| 488 | } \ |
| 489 | \ |
| 490 | static inline void ins##bwlq(unsigned long port, void *addr, \ |
| 491 | unsigned int count) \ |
| 492 | { \ |
| 493 | volatile type *__addr = addr; \ |
| 494 | \ |
| 495 | while (count--) { \ |
Al Viro | 290f10a | 2005-12-07 23:12:54 -0500 | [diff] [blame] | 496 | *__addr = __mem_in##bwlq(port); \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 497 | __addr++; \ |
| 498 | } \ |
| 499 | } |
| 500 | |
| 501 | #define BUILDSTRING(bwlq, type) \ |
| 502 | \ |
| 503 | __BUILD_MEMORY_STRING(bwlq, type) \ |
| 504 | __BUILD_IOPORT_STRING(bwlq, type) |
| 505 | |
| 506 | BUILDSTRING(b, u8) |
| 507 | BUILDSTRING(w, u16) |
| 508 | BUILDSTRING(l, u32) |
Ralf Baechle | 9d58f30 | 2005-09-23 20:02:38 +0000 | [diff] [blame] | 509 | #ifdef CONFIG_64BIT |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 510 | BUILDSTRING(q, u64) |
Ralf Baechle | 9d58f30 | 2005-09-23 20:02:38 +0000 | [diff] [blame] | 511 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 512 | |
| 513 | |
| 514 | /* Depends on MIPS II instruction set */ |
| 515 | #define mmiowb() asm volatile ("sync" ::: "memory") |
| 516 | |
Ralf Baechle | fe00f94 | 2005-03-01 19:22:29 +0000 | [diff] [blame] | 517 | static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count) |
| 518 | { |
| 519 | memset((void __force *) addr, val, count); |
| 520 | } |
| 521 | static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count) |
| 522 | { |
| 523 | memcpy(dst, (void __force *) src, count); |
| 524 | } |
| 525 | static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count) |
| 526 | { |
| 527 | memcpy((void __force *) dst, src, count); |
| 528 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 529 | |
| 530 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 531 | * ISA space is 'always mapped' on currently supported MIPS systems, no need |
| 532 | * to explicitly ioremap() it. The fact that the ISA IO space is mapped |
| 533 | * to PAGE_OFFSET is pure coincidence - it does not mean ISA values |
| 534 | * are physical addresses. The following constant pointer can be |
| 535 | * used as the IO-area pointer (it can be iounmapped as well, so the |
| 536 | * analogy with PCI is quite large): |
| 537 | */ |
| 538 | #define __ISA_IO_base ((char *)(isa_slot_offset)) |
| 539 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 540 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 541 | * The caches on some architectures aren't dma-coherent and have need to |
| 542 | * handle this in software. There are three types of operations that |
| 543 | * can be applied to dma buffers. |
| 544 | * |
| 545 | * - dma_cache_wback_inv(start, size) makes caches and coherent by |
| 546 | * writing the content of the caches back to memory, if necessary. |
| 547 | * The function also invalidates the affected part of the caches as |
| 548 | * necessary before DMA transfers from outside to memory. |
| 549 | * - dma_cache_wback(start, size) makes caches and coherent by |
| 550 | * writing the content of the caches back to memory, if necessary. |
| 551 | * The function also invalidates the affected part of the caches as |
| 552 | * necessary before DMA transfers from outside to memory. |
| 553 | * - dma_cache_inv(start, size) invalidates the affected parts of the |
| 554 | * caches. Dirty lines of the caches may be written back or simply |
| 555 | * be discarded. This operation is necessary before dma operations |
| 556 | * to the memory. |
| 557 | */ |
| 558 | #ifdef CONFIG_DMA_NONCOHERENT |
| 559 | |
| 560 | extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size); |
| 561 | extern void (*_dma_cache_wback)(unsigned long start, unsigned long size); |
| 562 | extern void (*_dma_cache_inv)(unsigned long start, unsigned long size); |
| 563 | |
| 564 | #define dma_cache_wback_inv(start, size) _dma_cache_wback_inv(start,size) |
| 565 | #define dma_cache_wback(start, size) _dma_cache_wback(start,size) |
| 566 | #define dma_cache_inv(start, size) _dma_cache_inv(start,size) |
| 567 | |
| 568 | #else /* Sane hardware */ |
| 569 | |
| 570 | #define dma_cache_wback_inv(start,size) \ |
| 571 | do { (void) (start); (void) (size); } while (0) |
| 572 | #define dma_cache_wback(start,size) \ |
| 573 | do { (void) (start); (void) (size); } while (0) |
| 574 | #define dma_cache_inv(start,size) \ |
| 575 | do { (void) (start); (void) (size); } while (0) |
| 576 | |
| 577 | #endif /* CONFIG_DMA_NONCOHERENT */ |
| 578 | |
| 579 | /* |
| 580 | * Read a 32-bit register that requires a 64-bit read cycle on the bus. |
| 581 | * Avoid interrupt mucking, just adjust the address for 4-byte access. |
| 582 | * Assume the addresses are 8-byte aligned. |
| 583 | */ |
| 584 | #ifdef __MIPSEB__ |
| 585 | #define __CSR_32_ADJUST 4 |
| 586 | #else |
| 587 | #define __CSR_32_ADJUST 0 |
| 588 | #endif |
| 589 | |
| 590 | #define csr_out32(v,a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v)) |
| 591 | #define csr_in32(a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST)) |
| 592 | |
| 593 | /* |
| 594 | * Convert a physical pointer to a virtual kernel pointer for /dev/mem |
| 595 | * access |
| 596 | */ |
| 597 | #define xlate_dev_mem_ptr(p) __va(p) |
| 598 | |
| 599 | /* |
| 600 | * Convert a virtual cached pointer to an uncached pointer |
| 601 | */ |
| 602 | #define xlate_dev_kmem_ptr(p) p |
| 603 | |
| 604 | #endif /* _ASM_IO_H */ |