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gerrit-public.fairphone.software / kernel / msm-4.19 / 4f25eb85d64640bc656e72917113a84701521b99 / . / arch / blackfin / mach-bf548 / Kconfig
blob: d8bd3b49f150275cf5e32ccbd0c0cfbf648d4e65 [file] [log] [blame]
Roy Huang24a07a12007-07-12 22:41:45 +0800[diff] [blame]1if (BF54x)
2
Mike Frysinger4f25eb82007-11-15 20:49:44 +0800[diff] [blame^]3source "arch/blackfin/mach-bf548/boards/Kconfig"
4
Roy Huang24a07a12007-07-12 22:41:45 +0800[diff] [blame]5menu "BF548 Specific Configuration"
6
Michael Hennericha924db72007-08-03 17:43:29 +0800[diff] [blame]7config DEB_DMA_URGENT
8 bool "DMA has priority over core for ext. accesses"
9 depends on BF54x
10 default n
11 help
12 Treat any DEB1, DEB2 and DEB3 request as Urgent
13
Roy Huang24a07a12007-07-12 22:41:45 +0800[diff] [blame]14comment "Interrupt Priority Assignment"
15menu "Priority"
16
17config IRQ_PLL_WAKEUP
18 int "IRQ_PLL_WAKEUP"
19 default 7
20config IRQ_DMAC0_ERR
21 int "IRQ_DMAC0_ERR"
22 default 7
23config IRQ_EPPI0_ERR
24 int "IRQ_EPPI0_ERR"
25 default 7
26config IRQ_SPORT0_ERR
27 int "IRQ_SPORT0_ERR"
28 default 7
29config IRQ_SPORT1_ERR
30 int "IRQ_SPORT1_ERR"
31 default 7
32config IRQ_SPI0_ERR
33 int "IRQ_SPI0_ERR"
34 default 7
35config IRQ_UART0_ERR
36 int "IRQ_UART0_ERR"
37 default 7
38config IRQ_RTC
39 int "IRQ_RTC"
40 default 8
41config IRQ_EPPI0
42 int "IRQ_EPPI0"
43 default 8
44config IRQ_SPORT0_RX
45 int "IRQ_SPORT0_RX"
46 default 9
47config IRQ_SPORT0_TX
48 int "IRQ_SPORT0_TX"
49 default 9
50config IRQ_SPORT1_RX
51 int "IRQ_SPORT1_RX"
52 default 9
53config IRQ_SPORT1_TX
54 int "IRQ_SPORT1_TX"
55 default 9
56config IRQ_SPI0
57 int "IRQ_SPI0"
58 default 10
59config IRQ_UART0_RX
60 int "IRQ_UART0_RX"
61 default 10
62config IRQ_UART0_TX
63 int "IRQ_UART0_TX"
64 default 10
65config IRQ_TIMER8
66 int "IRQ_TIMER8"
67 default 11
68config IRQ_TIMER9
69 int "IRQ_TIMER9"
70 default 11
71config IRQ_TIMER10
72 int "IRQ_TIMER10"
73 default 11
74config IRQ_PINT0
75 int "IRQ_PINT0"
76 default 12
77config IRQ_PINT1
78 int "IRQ_PINT0"
79 default 12
80config IRQ_MDMAS0
81 int "IRQ_MDMAS0"
82 default 13
83config IRQ_MDMAS1
84 int "IRQ_DMDMAS1"
85 default 13
86config IRQ_WATCHDOG
87 int "IRQ_WATCHDOG"
88 default 13
89config IRQ_DMAC1_ERR
90 int "IRQ_DMAC1_ERR"
91 default 7
92config IRQ_SPORT2_ERR
93 int "IRQ_SPORT2_ERR"
94 default 7
95config IRQ_SPORT3_ERR
96 int "IRQ_SPORT3_ERR"
97 default 7
98config IRQ_MXVR_DATA
99 int "IRQ MXVR Data"
100 default 7
101config IRQ_SPI1_ERR
102 int "IRQ_SPI1_ERR"
103 default 7
104config IRQ_SPI2_ERR
105 int "IRQ_SPI2_ERR"
106 default 7
107config IRQ_UART1_ERR
108 int "IRQ_UART1_ERR"
109 default 7
110config IRQ_UART2_ERR
111 int "IRQ_UART2_ERR"
112 default 7
113config IRQ_CAN0_ERR
114 int "IRQ_CAN0_ERR"
115 default 7
116config IRQ_SPORT2_RX
117 int "IRQ_SPORT2_RX"
118 default 9
119config IRQ_SPORT2_TX
120 int "IRQ_SPORT2_TX"
121 default 9
122config IRQ_SPORT3_RX
123 int "IRQ_SPORT3_RX"
124 default 9
125config IRQ_SPORT3_TX
126 int "IRQ_SPORT3_TX"
127 default 9
128config IRQ_EPPI1
129 int "IRQ_EPPI1"
130 default 9
131config IRQ_EPPI2
132 int "IRQ_EPPI2"
133 default 9
134config IRQ_SPI1
135 int "IRQ_SPI1"
136 default 10
137config IRQ_SPI2
138 int "IRQ_SPI2"
139 default 10
140config IRQ_UART1_RX
141 int "IRQ_UART1_RX"
142 default 10
143config IRQ_UART1_TX
144 int "IRQ_UART1_TX"
145 default 10
146config IRQ_ATAPI_RX
147 int "IRQ_ATAPI_RX"
148 default 10
149config IRQ_ATAPI_TX
150 int "IRQ_ATAPI_TX"
151 default 10
152config IRQ_TWI0
153 int "IRQ_TWI0"
154 default 11
155config IRQ_TWI1
156 int "IRQ_TWI1"
157 default 11
158config IRQ_CAN0_RX
159 int "IRQ_CAN_RX"
160 default 11
161config IRQ_CAN0_TX
162 int "IRQ_CAN_TX"
163 default 11
164config IRQ_MDMAS2
165 int "IRQ_MDMAS2"
166 default 13
167config IRQ_MDMAS3
168 int "IRQ_DMMAS3"
169 default 13
170config IRQ_MXVR_ERR
171 int "IRQ_MXVR_ERR"
172 default 11
173config IRQ_MXVR_MSG
174 int "IRQ_MXVR_MSG"
175 default 11
176config IRQ_MXVR_PKT
177 int "IRQ_MXVR_PKT"
178 default 11
179config IRQ_EPPI1_ERR
180 int "IRQ_EPPI1_ERR"
181 default 7
182config IRQ_EPPI2_ERR
183 int "IRQ_EPPI2_ERR"
184 default 7
185config IRQ_UART3_ERR
186 int "IRQ_UART3_ERR"
187 default 7
188config IRQ_HOST_ERR
189 int "IRQ_HOST_ERR"
190 default 7
191config IRQ_PIXC_ERR
192 int "IRQ_PIXC_ERR"
193 default 7
194config IRQ_NFC_ERR
195 int "IRQ_NFC_ERR"
196 default 7
197config IRQ_ATAPI_ERR
198 int "IRQ_ATAPI_ERR"
199 default 7
200config IRQ_CAN1_ERR
201 int "IRQ_CAN1_ERR"
202 default 7
203config IRQ_HS_DMA_ERR
204 int "IRQ Handshake DMA Status"
205 default 7
206config IRQ_PIXC_IN0
207 int "IRQ PIXC IN0"
208 default 8
209config IRQ_PIXC_IN1
210 int "IRQ PIXC IN1"
211 default 8
212config IRQ_PIXC_OUT
213 int "IRQ PIXC OUT"
214 default 8
215config IRQ_SDH
216 int "IRQ SDH"
217 default 8
218config IRQ_CNT
219 int "IRQ CNT"
220 default 8
221config IRQ_KEY
222 int "IRQ KEY"
223 default 8
224config IRQ_CAN1_RX
225 int "IRQ CAN1 RX"
226 default 11
227config IRQ_CAN1_TX
228 int "IRQ_CAN1_TX"
229 default 11
230config IRQ_SDH_MASK0
231 int "IRQ_SDH_MASK0"
232 default 11
233config IRQ_SDH_MASK1
234 int "IRQ_SDH_MASK1"
235 default 11
236config IRQ_USB_INT0
237 int "IRQ USB INT0"
238 default 11
239config IRQ_USB_INT1
240 int "IRQ USB INT1"
241 default 11
242config IRQ_USB_INT2
243 int "IRQ USB INT2"
244 default 11
245config IRQ_USB_DMA
246 int "IRQ USB DMA"
247 default 11
248config IRQ_OTPSEC
249 int "IRQ OPTSEC"
250 default 11
251config IRQ_TIMER0
252 int "IRQ_TIMER0"
253 default 11
254config IRQ_TIMER1
255 int "IRQ_TIMER1"
256 default 11
257config IRQ_TIMER2
258 int "IRQ_TIMER2"
259 default 11
260config IRQ_TIMER3
261 int "IRQ_TIMER3"
262 default 11
263config IRQ_TIMER4
264 int "IRQ_TIMER4"
265 default 11
266config IRQ_TIMER5
267 int "IRQ_TIMER5"
268 default 11
269config IRQ_TIMER6
270 int "IRQ_TIMER6"
271 default 11
272config IRQ_TIMER7
273 int "IRQ_TIMER7"
274 default 11
275config IRQ_PINT2
276 int "IRQ_PIN2"
277 default 11
278config IRQ_PINT3
279 int "IRQ_PIN3"
280 default 11
281
282 help
283 Enter the priority numbers between 7-13 ONLY. Others are Reserved.
284 This applies to all the above. It is not recommended to assign the
285 highest priority number 7 to UART or any other device.
286
287endmenu
288
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800[diff] [blame]289comment "Pin Interrupt to Port Assignment"
290menu "Assignment"
291
292config PINTx_REASSIGN
293 bool "Reprogram PINT Assignment"
Michael Hennerich31430ba2007-07-24 16:27:25 +0800[diff] [blame]294 default y
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800[diff] [blame]295 help
296 The interrupt assignment registers controls the pin-to-interrupt
297 assignment in a byte-wide manner. Each option allows you to select
298 a set of pins (High/Low Byte) of an specific Port being mapped
299 to one of the four PIN Interrupts IRQ_PINTx.
300
301 You shouldn't change any of these unless you know exactly what you're doing.
302 Please consult the Blackfin BF54x Processor Hardware Reference Manual.
303
304config PINT0_ASSIGN
305 hex "PINT0_ASSIGN"
306 depends on PINTx_REASSIGN
307 default 0x00000101
308config PINT1_ASSIGN
309 hex "PINT1_ASSIGN"
310 depends on PINTx_REASSIGN
311 default 0x01010000
312config PINT2_ASSIGN
313 hex "PINT2_ASSIGN"
314 depends on PINTx_REASSIGN
Michael Hennerich31430ba2007-07-24 16:27:25 +0800[diff] [blame]315 default 0x07000101
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800[diff] [blame]316config PINT3_ASSIGN
317 hex "PINT3_ASSIGN"
318 depends on PINTx_REASSIGN
319 default 0x02020303
320
321endmenu
322
Roy Huang24a07a12007-07-12 22:41:45 +0800[diff] [blame]323endmenu
324
325endif