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gerrit-public.fairphone.software / kernel / msm-4.19 / 50bd6153d1a68354a0a0c8bca1fe949fa8875875 / . / arch / powerpc / include / asm / tlbflush.h
blob: 2def01ed0cb296ad48296366b4eb8a8dfb9e0da0 [file] [log] [blame]
Stephen Rothwell19702822005-11-04 16:58:59 +1100[diff] [blame]1#ifndef _ASM_POWERPC_TLBFLUSH_H
2#define _ASM_POWERPC_TLBFLUSH_H
Benjamin Herrenschmidte701d262007-10-30 09:46:06 +1100[diff] [blame]3
Stephen Rothwell19702822005-11-04 16:58:59 +1100[diff] [blame]4/*
5 * TLB flushing:
6 *
7 * - flush_tlb_mm(mm) flushes the specified mm context TLB's
8 * - flush_tlb_page(vma, vmaddr) flushes one page
Benjamin Herrenschmidtd4e167d2009-07-23 23:15:24 +0000[diff] [blame]9 * - local_flush_tlb_mm(mm, full) flushes the specified mm context on
Benjamin Herrenschmidtf048aac2008-12-18 19:13:38 +0000[diff] [blame]10 * the local processor
11 * - local_flush_tlb_page(vma, vmaddr) flushes one page on the local processor
Stephen Rothwell19702822005-11-04 16:58:59 +1100[diff] [blame]12 * - flush_tlb_page_nohash(vma, vmaddr) flushes one page if SW loaded TLB
13 * - flush_tlb_range(vma, start, end) flushes a range of pages
14 * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
Stephen Rothwell19702822005-11-04 16:58:59 +1100[diff] [blame]15 *
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License
18 * as published by the Free Software Foundation; either version
19 * 2 of the License, or (at your option) any later version.
20 */
21#ifdef __KERNEL__
22
Benjamin Herrenschmidtf048aac2008-12-18 19:13:38 +0000[diff] [blame]23#ifdef CONFIG_PPC_MMU_NOHASH
David Gibson62102302007-04-24 13:09:12 +1000[diff] [blame]24/*
25 * TLB flushing for software loaded TLB chips
26 *
27 * TODO: (CONFIG_FSL_BOOKE) determine if flush_tlb_range &
28 * flush_tlb_kernel_range are best implemented as tlbia vs
29 * specific tlbie's
30 */
31
Benjamin Herrenschmidtd4e167d2009-07-23 23:15:24 +0000[diff] [blame]32struct vm_area_struct;
33struct mm_struct;
Benjamin Herrenschmidte701d262007-10-30 09:46:06 +1100[diff] [blame]34
Benjamin Herrenschmidt2ca8cf732008-12-18 19:13:29 +0000[diff] [blame]35#define MMU_NO_CONTEXT ((unsigned int)-1)
36
Benjamin Herrenschmidtf048aac2008-12-18 19:13:38 +0000[diff] [blame]37extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
38 unsigned long end);
39extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
Benjamin Herrenschmidt1a37a3f2008-12-14 19:44:24 +0000[diff] [blame]40
Benjamin Herrenschmidtf048aac2008-12-18 19:13:38 +0000[diff] [blame]41extern void local_flush_tlb_mm(struct mm_struct *mm);
42extern void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr);
David Gibson62102302007-04-24 13:09:12 +1000[diff] [blame]43
Benjamin Herrenschmidtd4e167d2009-07-23 23:15:24 +0000[diff] [blame]44extern void __local_flush_tlb_page(struct mm_struct *mm, unsigned long vmaddr,
45 int tsize, int ind);
46
Benjamin Herrenschmidtf048aac2008-12-18 19:13:38 +0000[diff] [blame]47#ifdef CONFIG_SMP
48extern void flush_tlb_mm(struct mm_struct *mm);
49extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr);
Benjamin Herrenschmidtd4e167d2009-07-23 23:15:24 +0000[diff] [blame]50extern void __flush_tlb_page(struct mm_struct *mm, unsigned long vmaddr,
51 int tsize, int ind);
Benjamin Herrenschmidtf048aac2008-12-18 19:13:38 +0000[diff] [blame]52#else
53#define flush_tlb_mm(mm) local_flush_tlb_mm(mm)
54#define flush_tlb_page(vma,addr) local_flush_tlb_page(vma,addr)
Benjamin Herrenschmidtd4e167d2009-07-23 23:15:24 +0000[diff] [blame]55#define __flush_tlb_page(mm,addr,p,i) __local_flush_tlb_page(mm,addr,p,i)
Benjamin Herrenschmidtf048aac2008-12-18 19:13:38 +0000[diff] [blame]56#endif
57#define flush_tlb_page_nohash(vma,addr) flush_tlb_page(vma,addr)
Kumar Galadf3b8612008-11-19 05:53:24 +0000[diff] [blame]58
Benjamin Herrenschmidtf048aac2008-12-18 19:13:38 +0000[diff] [blame]59#elif defined(CONFIG_PPC_STD_MMU_32)
David Gibson62102302007-04-24 13:09:12 +1000[diff] [blame]60
David Gibson62102302007-04-24 13:09:12 +1000[diff] [blame]61/*
Benjamin Herrenschmidtf048aac2008-12-18 19:13:38 +0000[diff] [blame]62 * TLB flushing for "classic" hash-MMU 32-bit CPUs, 6xx, 7xx, 7xxx
David Gibson62102302007-04-24 13:09:12 +1000[diff] [blame]63 */
David Gibson62102302007-04-24 13:09:12 +1000[diff] [blame]64extern void flush_tlb_mm(struct mm_struct *mm);
65extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr);
66extern void flush_tlb_page_nohash(struct vm_area_struct *vma, unsigned long addr);
67extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
68 unsigned long end);
69extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
Benjamin Herrenschmidtf048aac2008-12-18 19:13:38 +0000[diff] [blame]70static inline void local_flush_tlb_page(struct vm_area_struct *vma,
71 unsigned long vmaddr)
Kumar Galadf3b8612008-11-19 05:53:24 +0000[diff] [blame]72{
Benjamin Herrenschmidtf048aac2008-12-18 19:13:38 +0000[diff] [blame]73 flush_tlb_page(vma, vmaddr);
74}
75static inline void local_flush_tlb_mm(struct mm_struct *mm)
76{
77 flush_tlb_mm(mm);
Kumar Galadf3b8612008-11-19 05:53:24 +0000[diff] [blame]78}
David Gibson62102302007-04-24 13:09:12 +1000[diff] [blame]79
Benjamin Herrenschmidtf048aac2008-12-18 19:13:38 +0000[diff] [blame]80#elif defined(CONFIG_PPC_STD_MMU_64)
81
Michael Ellerman5e8e7b42011-04-12 19:00:04 +0000[diff] [blame]82#define MMU_NO_CONTEXT 0
83
David Gibson62102302007-04-24 13:09:12 +1000[diff] [blame]84/*
Benjamin Herrenschmidtf048aac2008-12-18 19:13:38 +0000[diff] [blame]85 * TLB flushing for 64-bit hash-MMU CPUs
David Gibson62102302007-04-24 13:09:12 +1000[diff] [blame]86 */
Stephen Rothwell19702822005-11-04 16:58:59 +1100[diff] [blame]87
88#include <linux/percpu.h>
89#include <asm/page.h>
90
91#define PPC64_TLB_BATCH_NR 192
92
93struct ppc64_tlb_batch {
Benjamin Herrenschmidta741e672007-04-10 17:09:37 +1000[diff] [blame]94 int active;
95 unsigned long index;
96 struct mm_struct *mm;
97 real_pte_t pte[PPC64_TLB_BATCH_NR];
Aneesh Kumar K.V5524a272012-09-10 02:52:50 +0000[diff] [blame]98 unsigned long vpn[PPC64_TLB_BATCH_NR];
Benjamin Herrenschmidta741e672007-04-10 17:09:37 +1000[diff] [blame]99 unsigned int psize;
Paul Mackerras1189be62007-10-11 20:37:10 +1000[diff] [blame]100 int ssize;
Stephen Rothwell19702822005-11-04 16:58:59 +1100[diff] [blame]101};
102DECLARE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch);
103
104extern void __flush_tlb_pending(struct ppc64_tlb_batch *batch);
105
Benjamin Herrenschmidta741e672007-04-10 17:09:37 +1000[diff] [blame]106#define __HAVE_ARCH_ENTER_LAZY_MMU_MODE
107
108static inline void arch_enter_lazy_mmu_mode(void)
Stephen Rothwell19702822005-11-04 16:58:59 +1100[diff] [blame]109{
Benjamin Herrenschmidta741e672007-04-10 17:09:37 +1000[diff] [blame]110 struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
111
112 batch->active = 1;
113}
114
115static inline void arch_leave_lazy_mmu_mode(void)
116{
117 struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
Stephen Rothwell19702822005-11-04 16:58:59 +1100[diff] [blame]118
119 if (batch->index)
120 __flush_tlb_pending(batch);
Benjamin Herrenschmidta741e672007-04-10 17:09:37 +1000[diff] [blame]121 batch->active = 0;
Stephen Rothwell19702822005-11-04 16:58:59 +1100[diff] [blame]122}
123
Benjamin Herrenschmidta741e672007-04-10 17:09:37 +1000[diff] [blame]124#define arch_flush_lazy_mmu_mode() do {} while (0)
125
126
Aneesh Kumar K.V5524a272012-09-10 02:52:50 +0000[diff] [blame]127extern void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize,
Paul Mackerras1189be62007-10-11 20:37:10 +1000[diff] [blame]128 int ssize, int local);
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100[diff] [blame]129extern void flush_hash_range(unsigned long number, int local);
Stephen Rothwell19702822005-11-04 16:58:59 +1100[diff] [blame]130
Stephen Rothwell19702822005-11-04 16:58:59 +1100[diff] [blame]131
Benjamin Herrenschmidtf048aac2008-12-18 19:13:38 +0000[diff] [blame]132static inline void local_flush_tlb_mm(struct mm_struct *mm)
133{
134}
135
David Gibson62102302007-04-24 13:09:12 +1000[diff] [blame]136static inline void flush_tlb_mm(struct mm_struct *mm)
137{
138}
Stephen Rothwell19702822005-11-04 16:58:59 +1100[diff] [blame]139
Benjamin Herrenschmidtf048aac2008-12-18 19:13:38 +0000[diff] [blame]140static inline void local_flush_tlb_page(struct vm_area_struct *vma,
141 unsigned long vmaddr)
Kumar Galadf3b8612008-11-19 05:53:24 +0000[diff] [blame]142{
143}
144
David Gibson62102302007-04-24 13:09:12 +1000[diff] [blame]145static inline void flush_tlb_page(struct vm_area_struct *vma,
146 unsigned long vmaddr)
147{
148}
Stephen Rothwell19702822005-11-04 16:58:59 +1100[diff] [blame]149
David Gibson62102302007-04-24 13:09:12 +1000[diff] [blame]150static inline void flush_tlb_page_nohash(struct vm_area_struct *vma,
151 unsigned long vmaddr)
152{
153}
Stephen Rothwell19702822005-11-04 16:58:59 +1100[diff] [blame]154
David Gibson62102302007-04-24 13:09:12 +1000[diff] [blame]155static inline void flush_tlb_range(struct vm_area_struct *vma,
156 unsigned long start, unsigned long end)
157{
158}
159
160static inline void flush_tlb_kernel_range(unsigned long start,
161 unsigned long end)
162{
163}
164
Benjamin Herrenschmidt3d5134e2007-06-04 15:15:36 +1000[diff] [blame]165/* Private function for use by PCI IO mapping code */
166extern void __flush_hash_table_range(struct mm_struct *mm, unsigned long start,
167 unsigned long end);
Aneesh Kumar K.V074c2ea2013-06-20 14:30:15 +0530[diff] [blame]168extern void flush_tlb_pmd_range(struct mm_struct *mm, pmd_t *pmd,
169 unsigned long addr);
Benjamin Herrenschmidtf048aac2008-12-18 19:13:38 +0000[diff] [blame]170#else
171#error Unsupported MMU type
Stephen Rothwell19702822005-11-04 16:58:59 +1100[diff] [blame]172#endif
173
Stephen Rothwell19702822005-11-04 16:58:59 +1100[diff] [blame]174#endif /*__KERNEL__ */
175#endif /* _ASM_POWERPC_TLBFLUSH_H */