Magnus Damm | 5f53a56 | 2010-12-21 08:37:32 +0000 | [diff] [blame] | 1 | /* |
| 2 | * sh73a0 processor support - INTC hardware block |
| 3 | * |
| 4 | * Copyright (C) 2010 Magnus Damm |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | #include <linux/kernel.h> |
| 20 | #include <linux/init.h> |
| 21 | #include <linux/interrupt.h> |
Magnus Damm | e2c31b3 | 2012-01-17 20:10:49 +0900 | [diff] [blame] | 22 | #include <linux/module.h> |
Magnus Damm | 5f53a56 | 2010-12-21 08:37:32 +0000 | [diff] [blame] | 23 | #include <linux/irq.h> |
| 24 | #include <linux/io.h> |
| 25 | #include <linux/sh_intc.h> |
Rob Herring | 520f7bd | 2012-12-27 13:10:24 -0600 | [diff] [blame^] | 26 | #include <linux/irqchip/arm-gic.h> |
Magnus Damm | a199305 | 2011-10-12 16:21:42 +0900 | [diff] [blame] | 27 | #include <mach/intc.h> |
Rob Herring | 250a272 | 2012-01-03 16:57:33 -0600 | [diff] [blame] | 28 | #include <mach/irqs.h> |
Magnus Damm | 566aad3 | 2011-10-17 18:00:52 +0900 | [diff] [blame] | 29 | #include <mach/sh73a0.h> |
Magnus Damm | 5f53a56 | 2010-12-21 08:37:32 +0000 | [diff] [blame] | 30 | #include <asm/mach-types.h> |
| 31 | #include <asm/mach/arch.h> |
| 32 | |
| 33 | enum { |
| 34 | UNUSED = 0, |
| 35 | |
| 36 | /* interrupt sources INTCS */ |
| 37 | PINTCS_PINT1, PINTCS_PINT2, |
| 38 | RTDMAC_0_DEI0, RTDMAC_0_DEI1, RTDMAC_0_DEI2, RTDMAC_0_DEI3, |
| 39 | CEU, MFI, BBIF2, VPU, TSIF1, _3DG_SGX543, _2DDMAC_2DDM0, |
| 40 | RTDMAC_1_DEI4, RTDMAC_1_DEI5, RTDMAC_1_DADERR, |
| 41 | KEYSC_KEY, VINT, MSIOF, |
| 42 | TMU0_TUNI00, TMU0_TUNI01, TMU0_TUNI02, |
| 43 | CMT0, TSIF0, CMT2, LMB, MSUG, MSU_MSU, MSU_MSU2, |
| 44 | CTI, RWDT0, ICB, PEP, ASA, JPU_JPEG, LCDC, LCRC, |
| 45 | RTDMAC_2_DEI6, RTDMAC_2_DEI7, RTDMAC_2_DEI8, RTDMAC_2_DEI9, |
| 46 | RTDMAC_3_DEI10, RTDMAC_3_DEI11, |
| 47 | FRC, GCU, LCDC1, CSIRX, |
| 48 | DSITX0_DSITX00, DSITX0_DSITX01, |
| 49 | SPU2_SPU0, SPU2_SPU1, FSI, |
| 50 | TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12, |
| 51 | TSIF2, CMT4, MFIS2, CPORTS2R, TSG, DMASCH1, SCUW, |
| 52 | VIO60, VIO61, CEU21, CSI21, DSITX1_DSITX10, DSITX1_DSITX11, |
| 53 | DISP, DSRV, EMUX2_EMUX20I, EMUX2_EMUX21I, |
| 54 | MSTIF0_MST00I, MSTIF0_MST01I, MSTIF1_MST10I, MSTIF1_MST11I, |
| 55 | SPUV, |
| 56 | |
| 57 | /* interrupt groups INTCS */ |
| 58 | RTDMAC_0, RTDMAC_1, RTDMAC_2, RTDMAC_3, |
| 59 | DSITX0, SPU2, TMU1, MSU, |
| 60 | }; |
| 61 | |
| 62 | static struct intc_vect intcs_vectors[] = { |
| 63 | INTCS_VECT(PINTCS_PINT1, 0x0600), INTCS_VECT(PINTCS_PINT2, 0x0620), |
| 64 | INTCS_VECT(RTDMAC_0_DEI0, 0x0800), INTCS_VECT(RTDMAC_0_DEI1, 0x0820), |
| 65 | INTCS_VECT(RTDMAC_0_DEI2, 0x0840), INTCS_VECT(RTDMAC_0_DEI3, 0x0860), |
| 66 | INTCS_VECT(CEU, 0x0880), INTCS_VECT(MFI, 0x0900), |
| 67 | INTCS_VECT(BBIF2, 0x0960), INTCS_VECT(VPU, 0x0980), |
| 68 | INTCS_VECT(TSIF1, 0x09a0), INTCS_VECT(_3DG_SGX543, 0x09e0), |
| 69 | INTCS_VECT(_2DDMAC_2DDM0, 0x0a00), |
| 70 | INTCS_VECT(RTDMAC_1_DEI4, 0x0b80), INTCS_VECT(RTDMAC_1_DEI5, 0x0ba0), |
| 71 | INTCS_VECT(RTDMAC_1_DADERR, 0x0bc0), |
| 72 | INTCS_VECT(KEYSC_KEY, 0x0be0), INTCS_VECT(VINT, 0x0c80), |
| 73 | INTCS_VECT(MSIOF, 0x0d20), |
| 74 | INTCS_VECT(TMU0_TUNI00, 0x0e80), INTCS_VECT(TMU0_TUNI01, 0x0ea0), |
| 75 | INTCS_VECT(TMU0_TUNI02, 0x0ec0), |
| 76 | INTCS_VECT(CMT0, 0x0f00), INTCS_VECT(TSIF0, 0x0f20), |
| 77 | INTCS_VECT(CMT2, 0x0f40), INTCS_VECT(LMB, 0x0f60), |
| 78 | INTCS_VECT(MSUG, 0x0f80), |
| 79 | INTCS_VECT(MSU_MSU, 0x0fa0), INTCS_VECT(MSU_MSU2, 0x0fc0), |
| 80 | INTCS_VECT(CTI, 0x0400), INTCS_VECT(RWDT0, 0x0440), |
| 81 | INTCS_VECT(ICB, 0x0480), INTCS_VECT(PEP, 0x04a0), |
| 82 | INTCS_VECT(ASA, 0x04c0), INTCS_VECT(JPU_JPEG, 0x0560), |
| 83 | INTCS_VECT(LCDC, 0x0580), INTCS_VECT(LCRC, 0x05a0), |
| 84 | INTCS_VECT(RTDMAC_2_DEI6, 0x1300), INTCS_VECT(RTDMAC_2_DEI7, 0x1320), |
| 85 | INTCS_VECT(RTDMAC_2_DEI8, 0x1340), INTCS_VECT(RTDMAC_2_DEI9, 0x1360), |
| 86 | INTCS_VECT(RTDMAC_3_DEI10, 0x1380), INTCS_VECT(RTDMAC_3_DEI11, 0x13a0), |
| 87 | INTCS_VECT(FRC, 0x1700), INTCS_VECT(GCU, 0x1760), |
| 88 | INTCS_VECT(LCDC1, 0x1780), INTCS_VECT(CSIRX, 0x17a0), |
| 89 | INTCS_VECT(DSITX0_DSITX00, 0x17c0), INTCS_VECT(DSITX0_DSITX01, 0x17e0), |
| 90 | INTCS_VECT(SPU2_SPU0, 0x1800), INTCS_VECT(SPU2_SPU1, 0x1820), |
| 91 | INTCS_VECT(FSI, 0x1840), |
| 92 | INTCS_VECT(TMU1_TUNI10, 0x1900), INTCS_VECT(TMU1_TUNI11, 0x1920), |
| 93 | INTCS_VECT(TMU1_TUNI12, 0x1940), |
| 94 | INTCS_VECT(TSIF2, 0x1960), INTCS_VECT(CMT4, 0x1980), |
| 95 | INTCS_VECT(MFIS2, 0x1a00), INTCS_VECT(CPORTS2R, 0x1a20), |
| 96 | INTCS_VECT(TSG, 0x1ae0), INTCS_VECT(DMASCH1, 0x1b00), |
| 97 | INTCS_VECT(SCUW, 0x1b40), |
| 98 | INTCS_VECT(VIO60, 0x1b60), INTCS_VECT(VIO61, 0x1b80), |
| 99 | INTCS_VECT(CEU21, 0x1ba0), INTCS_VECT(CSI21, 0x1be0), |
| 100 | INTCS_VECT(DSITX1_DSITX10, 0x1c00), INTCS_VECT(DSITX1_DSITX11, 0x1c20), |
| 101 | INTCS_VECT(DISP, 0x1c40), INTCS_VECT(DSRV, 0x1c60), |
| 102 | INTCS_VECT(EMUX2_EMUX20I, 0x1c80), INTCS_VECT(EMUX2_EMUX21I, 0x1ca0), |
| 103 | INTCS_VECT(MSTIF0_MST00I, 0x1cc0), INTCS_VECT(MSTIF0_MST01I, 0x1ce0), |
| 104 | INTCS_VECT(MSTIF1_MST10I, 0x1d00), INTCS_VECT(MSTIF1_MST11I, 0x1d20), |
| 105 | INTCS_VECT(SPUV, 0x2300), |
| 106 | }; |
| 107 | |
| 108 | static struct intc_group intcs_groups[] __initdata = { |
| 109 | INTC_GROUP(RTDMAC_0, RTDMAC_0_DEI0, RTDMAC_0_DEI1, |
| 110 | RTDMAC_0_DEI2, RTDMAC_0_DEI3), |
| 111 | INTC_GROUP(RTDMAC_1, RTDMAC_1_DEI4, RTDMAC_1_DEI5, RTDMAC_1_DADERR), |
| 112 | INTC_GROUP(RTDMAC_2, RTDMAC_2_DEI6, RTDMAC_2_DEI7, |
| 113 | RTDMAC_2_DEI8, RTDMAC_2_DEI9), |
| 114 | INTC_GROUP(RTDMAC_3, RTDMAC_3_DEI10, RTDMAC_3_DEI11), |
| 115 | INTC_GROUP(TMU1, TMU1_TUNI12, TMU1_TUNI11, TMU1_TUNI10), |
| 116 | INTC_GROUP(DSITX0, DSITX0_DSITX00, DSITX0_DSITX01), |
| 117 | INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1), |
| 118 | INTC_GROUP(MSU, MSU_MSU, MSU_MSU2), |
| 119 | }; |
| 120 | |
| 121 | static struct intc_mask_reg intcs_mask_registers[] = { |
| 122 | { 0xffd20184, 0xffd201c4, 8, /* IMR1SA / IMCR1SA */ |
| 123 | { 0, 0, 0, CEU, |
| 124 | 0, 0, 0, 0 } }, |
| 125 | { 0xffd20188, 0xffd201c8, 8, /* IMR2SA / IMCR2SA */ |
| 126 | { 0, 0, 0, VPU, |
| 127 | BBIF2, 0, 0, MFI } }, |
| 128 | { 0xffd2018c, 0xffd201cc, 8, /* IMR3SA / IMCR3SA */ |
| 129 | { 0, 0, 0, _2DDMAC_2DDM0, |
| 130 | 0, ASA, PEP, ICB } }, |
| 131 | { 0xffd20190, 0xffd201d0, 8, /* IMR4SA / IMCR4SA */ |
| 132 | { 0, 0, 0, CTI, |
| 133 | JPU_JPEG, 0, LCRC, LCDC } }, |
| 134 | { 0xffd20194, 0xffd201d4, 8, /* IMR5SA / IMCR5SA */ |
| 135 | { KEYSC_KEY, RTDMAC_1_DADERR, RTDMAC_1_DEI5, RTDMAC_1_DEI4, |
| 136 | RTDMAC_0_DEI3, RTDMAC_0_DEI2, RTDMAC_0_DEI1, RTDMAC_0_DEI0 } }, |
| 137 | { 0xffd20198, 0xffd201d8, 8, /* IMR6SA / IMCR6SA */ |
| 138 | { 0, 0, MSIOF, 0, |
| 139 | _3DG_SGX543, 0, 0, 0 } }, |
| 140 | { 0xffd2019c, 0xffd201dc, 8, /* IMR7SA / IMCR7SA */ |
| 141 | { 0, TMU0_TUNI02, TMU0_TUNI01, TMU0_TUNI00, |
| 142 | 0, 0, 0, 0 } }, |
| 143 | { 0xffd201a0, 0xffd201e0, 8, /* IMR8SA / IMCR8SA */ |
| 144 | { 0, 0, 0, 0, |
| 145 | 0, MSU_MSU, MSU_MSU2, MSUG } }, |
| 146 | { 0xffd201a4, 0xffd201e4, 8, /* IMR9SA / IMCR9SA */ |
| 147 | { 0, RWDT0, CMT2, CMT0, |
| 148 | 0, 0, 0, 0 } }, |
| 149 | { 0xffd201ac, 0xffd201ec, 8, /* IMR11SA / IMCR11SA */ |
| 150 | { 0, 0, 0, 0, |
| 151 | 0, TSIF1, LMB, TSIF0 } }, |
| 152 | { 0xffd201b0, 0xffd201f0, 8, /* IMR12SA / IMCR12SA */ |
| 153 | { 0, 0, 0, 0, |
| 154 | 0, 0, PINTCS_PINT2, PINTCS_PINT1 } }, |
| 155 | { 0xffd50180, 0xffd501c0, 8, /* IMR0SA3 / IMCR0SA3 */ |
| 156 | { RTDMAC_2_DEI6, RTDMAC_2_DEI7, RTDMAC_2_DEI8, RTDMAC_2_DEI9, |
| 157 | RTDMAC_3_DEI10, RTDMAC_3_DEI11, 0, 0 } }, |
| 158 | { 0xffd50190, 0xffd501d0, 8, /* IMR4SA3 / IMCR4SA3 */ |
| 159 | { FRC, 0, 0, GCU, |
| 160 | LCDC1, CSIRX, DSITX0_DSITX00, DSITX0_DSITX01 } }, |
| 161 | { 0xffd50194, 0xffd501d4, 8, /* IMR5SA3 / IMCR5SA3 */ |
| 162 | { SPU2_SPU0, SPU2_SPU1, FSI, 0, |
| 163 | 0, 0, 0, 0 } }, |
| 164 | { 0xffd50198, 0xffd501d8, 8, /* IMR6SA3 / IMCR6SA3 */ |
| 165 | { TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12, 0, |
| 166 | TSIF2, CMT4, 0, 0 } }, |
| 167 | { 0xffd5019c, 0xffd501dc, 8, /* IMR7SA3 / IMCR7SA3 */ |
| 168 | { MFIS2, CPORTS2R, 0, 0, |
| 169 | 0, 0, 0, TSG } }, |
| 170 | { 0xffd501a0, 0xffd501e0, 8, /* IMR8SA3 / IMCR8SA3 */ |
| 171 | { DMASCH1, 0, SCUW, VIO60, |
| 172 | VIO61, CEU21, 0, CSI21 } }, |
| 173 | { 0xffd501a4, 0xffd501e4, 8, /* IMR9SA3 / IMCR9SA3 */ |
| 174 | { DSITX1_DSITX10, DSITX1_DSITX11, DISP, DSRV, |
| 175 | EMUX2_EMUX20I, EMUX2_EMUX21I, MSTIF0_MST00I, MSTIF0_MST01I } }, |
| 176 | { 0xffd501a8, 0xffd501e8, 8, /* IMR10SA3 / IMCR10SA3 */ |
| 177 | { MSTIF0_MST00I, MSTIF0_MST01I, 0, 0, |
| 178 | 0, 0, 0, 0 } }, |
| 179 | { 0xffd60180, 0xffd601c0, 8, /* IMR0SA4 / IMCR0SA4 */ |
| 180 | { SPUV, 0, 0, 0, |
| 181 | 0, 0, 0, 0 } }, |
| 182 | }; |
| 183 | |
| 184 | /* Priority is needed for INTCA to receive the INTCS interrupt */ |
| 185 | static struct intc_prio_reg intcs_prio_registers[] = { |
| 186 | { 0xffd20000, 0, 16, 4, /* IPRAS */ { CTI, 0, _2DDMAC_2DDM0, ICB } }, |
| 187 | { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPU_JPEG, LCDC, 0, LCRC } }, |
| 188 | { 0xffd20008, 0, 16, 4, /* IPRCS */ { BBIF2, 0, 0, 0 } }, |
| 189 | { 0xffd2000c, 0, 16, 4, /* IPRDS */ { PINTCS_PINT1, PINTCS_PINT2, |
| 190 | 0, 0 } }, |
| 191 | { 0xffd20010, 0, 16, 4, /* IPRES */ { RTDMAC_0, CEU, MFI, VPU } }, |
| 192 | { 0xffd20014, 0, 16, 4, /* IPRFS */ { KEYSC_KEY, RTDMAC_1, |
| 193 | CMT2, CMT0 } }, |
| 194 | { 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU0_TUNI00, TMU0_TUNI01, |
| 195 | TMU0_TUNI02, TSIF1 } }, |
| 196 | { 0xffd2001c, 0, 16, 4, /* IPRHS */ { VINT, 0, 0, 0 } }, |
| 197 | { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, MSIOF, TSIF0, 0 } }, |
| 198 | { 0xffd20024, 0, 16, 4, /* IPRJS */ { 0, _3DG_SGX543, MSUG, MSU } }, |
| 199 | { 0xffd20028, 0, 16, 4, /* IPRKS */ { 0, ASA, LMB, PEP } }, |
| 200 | { 0xffd20030, 0, 16, 4, /* IPRMS */ { 0, 0, 0, RWDT0 } }, |
| 201 | { 0xffd50000, 0, 16, 4, /* IPRAS3 */ { RTDMAC_2, 0, 0, 0 } }, |
| 202 | { 0xffd50004, 0, 16, 4, /* IPRBS3 */ { RTDMAC_3, 0, 0, 0 } }, |
| 203 | { 0xffd50020, 0, 16, 4, /* IPRIS3 */ { FRC, 0, 0, 0 } }, |
| 204 | { 0xffd50024, 0, 16, 4, /* IPRJS3 */ { LCDC1, CSIRX, DSITX0, 0 } }, |
| 205 | { 0xffd50028, 0, 16, 4, /* IPRKS3 */ { SPU2, 0, FSI, 0 } }, |
| 206 | { 0xffd50030, 0, 16, 4, /* IPRMS3 */ { TMU1, 0, 0, TSIF2 } }, |
| 207 | { 0xffd50034, 0, 16, 4, /* IPRNS3 */ { CMT4, 0, 0, 0 } }, |
| 208 | { 0xffd50038, 0, 16, 4, /* IPROS3 */ { MFIS2, CPORTS2R, 0, 0 } }, |
| 209 | { 0xffd50040, 0, 16, 4, /* IPRQS3 */ { DMASCH1, 0, SCUW, VIO60 } }, |
| 210 | { 0xffd50044, 0, 16, 4, /* IPRRS3 */ { VIO61, CEU21, 0, CSI21 } }, |
| 211 | { 0xffd50048, 0, 16, 4, /* IPRSS3 */ { DSITX1_DSITX10, DSITX1_DSITX11, |
| 212 | DISP, DSRV } }, |
| 213 | { 0xffd5004c, 0, 16, 4, /* IPRTS3 */ { EMUX2_EMUX20I, EMUX2_EMUX21I, |
| 214 | MSTIF0_MST00I, MSTIF0_MST01I } }, |
| 215 | { 0xffd50050, 0, 16, 4, /* IPRUS3 */ { MSTIF1_MST10I, MSTIF1_MST11I, |
| 216 | 0, 0 } }, |
| 217 | { 0xffd60000, 0, 16, 4, /* IPRAS4 */ { SPUV, 0, 0, 0 } }, |
| 218 | }; |
| 219 | |
| 220 | static struct resource intcs_resources[] __initdata = { |
| 221 | [0] = { |
| 222 | .start = 0xffd20000, |
| 223 | .end = 0xffd201ff, |
| 224 | .flags = IORESOURCE_MEM, |
| 225 | }, |
| 226 | [1] = { |
| 227 | .start = 0xffd50000, |
| 228 | .end = 0xffd501ff, |
| 229 | .flags = IORESOURCE_MEM, |
| 230 | }, |
| 231 | [2] = { |
| 232 | .start = 0xffd60000, |
| 233 | .end = 0xffd601ff, |
| 234 | .flags = IORESOURCE_MEM, |
| 235 | } |
| 236 | }; |
| 237 | |
| 238 | static struct intc_desc intcs_desc __initdata = { |
| 239 | .name = "sh73a0-intcs", |
| 240 | .resource = intcs_resources, |
| 241 | .num_resources = ARRAY_SIZE(intcs_resources), |
| 242 | .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers, |
| 243 | intcs_prio_registers, NULL, NULL), |
| 244 | }; |
| 245 | |
| 246 | static struct irqaction sh73a0_intcs_cascade; |
| 247 | |
| 248 | static irqreturn_t sh73a0_intcs_demux(int irq, void *dev_id) |
| 249 | { |
| 250 | unsigned int evtcodeas = ioread32((void __iomem *)dev_id); |
| 251 | |
| 252 | generic_handle_irq(intcs_evt2irq(evtcodeas)); |
| 253 | |
| 254 | return IRQ_HANDLED; |
| 255 | } |
| 256 | |
Magnus Damm | 485b2ab | 2011-06-09 06:20:03 +0000 | [diff] [blame] | 257 | static int sh73a0_set_wake(struct irq_data *data, unsigned int on) |
| 258 | { |
| 259 | return 0; /* always allow wakeup */ |
| 260 | } |
| 261 | |
Kuninori Morimoto | 6c0274c | 2012-08-22 12:13:48 +0200 | [diff] [blame] | 262 | #define RELOC_BASE 0x1200 |
Magnus Damm | a199305 | 2011-10-12 16:21:42 +0900 | [diff] [blame] | 263 | |
Kuninori Morimoto | 6c0274c | 2012-08-22 12:13:48 +0200 | [diff] [blame] | 264 | /* INTCA IRQ pins at INTCS + RELOC_BASE to make space for GIC+INTC handling */ |
Magnus Damm | a199305 | 2011-10-12 16:21:42 +0900 | [diff] [blame] | 265 | #define INTCS_VECT_RELOC(n, vect) INTCS_VECT((n), (vect) + RELOC_BASE) |
| 266 | |
| 267 | INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000, |
| 268 | INTCS_VECT_RELOC, "sh73a0-intca-irq-pins"); |
| 269 | |
| 270 | static int to_gic_irq(struct irq_data *data) |
| 271 | { |
| 272 | unsigned int vect = irq2evt(data->irq) - INTCS_VECT_BASE; |
| 273 | |
| 274 | if (vect >= 0x3200) |
| 275 | vect -= 0x3000; |
| 276 | else |
| 277 | vect -= 0x0200; |
| 278 | |
| 279 | return gic_spi((vect >> 5) + 1); |
| 280 | } |
| 281 | |
| 282 | static int to_intca_reloc_irq(struct irq_data *data) |
| 283 | { |
| 284 | return data->irq + (RELOC_BASE >> 5); |
| 285 | } |
| 286 | |
| 287 | #define irq_cb(cb, irq) irq_get_chip(irq)->cb(irq_get_irq_data(irq)) |
| 288 | #define irq_cbp(cb, irq, p...) irq_get_chip(irq)->cb(irq_get_irq_data(irq), p) |
| 289 | |
| 290 | static void intca_gic_enable(struct irq_data *data) |
| 291 | { |
| 292 | irq_cb(irq_unmask, to_intca_reloc_irq(data)); |
| 293 | irq_cb(irq_unmask, to_gic_irq(data)); |
| 294 | } |
| 295 | |
| 296 | static void intca_gic_disable(struct irq_data *data) |
| 297 | { |
| 298 | irq_cb(irq_mask, to_gic_irq(data)); |
| 299 | irq_cb(irq_mask, to_intca_reloc_irq(data)); |
| 300 | } |
| 301 | |
| 302 | static void intca_gic_mask_ack(struct irq_data *data) |
| 303 | { |
| 304 | irq_cb(irq_mask, to_gic_irq(data)); |
| 305 | irq_cb(irq_mask_ack, to_intca_reloc_irq(data)); |
| 306 | } |
| 307 | |
| 308 | static void intca_gic_eoi(struct irq_data *data) |
| 309 | { |
| 310 | irq_cb(irq_eoi, to_gic_irq(data)); |
| 311 | } |
| 312 | |
| 313 | static int intca_gic_set_type(struct irq_data *data, unsigned int type) |
| 314 | { |
| 315 | return irq_cbp(irq_set_type, to_intca_reloc_irq(data), type); |
| 316 | } |
| 317 | |
| 318 | static int intca_gic_set_wake(struct irq_data *data, unsigned int on) |
| 319 | { |
| 320 | return irq_cbp(irq_set_wake, to_intca_reloc_irq(data), on); |
| 321 | } |
| 322 | |
| 323 | #ifdef CONFIG_SMP |
| 324 | static int intca_gic_set_affinity(struct irq_data *data, |
| 325 | const struct cpumask *cpumask, |
| 326 | bool force) |
| 327 | { |
| 328 | return irq_cbp(irq_set_affinity, to_gic_irq(data), cpumask, force); |
| 329 | } |
| 330 | #endif |
| 331 | |
| 332 | struct irq_chip intca_gic_irq_chip = { |
| 333 | .name = "INTCA-GIC", |
| 334 | .irq_mask = intca_gic_disable, |
| 335 | .irq_unmask = intca_gic_enable, |
| 336 | .irq_mask_ack = intca_gic_mask_ack, |
| 337 | .irq_eoi = intca_gic_eoi, |
| 338 | .irq_enable = intca_gic_enable, |
| 339 | .irq_disable = intca_gic_disable, |
| 340 | .irq_shutdown = intca_gic_disable, |
| 341 | .irq_set_type = intca_gic_set_type, |
| 342 | .irq_set_wake = intca_gic_set_wake, |
| 343 | #ifdef CONFIG_SMP |
| 344 | .irq_set_affinity = intca_gic_set_affinity, |
| 345 | #endif |
| 346 | }; |
| 347 | |
| 348 | static int to_intc_vect(int irq) |
| 349 | { |
| 350 | unsigned int irq_pin = irq - gic_spi(1); |
| 351 | unsigned int offs; |
| 352 | |
| 353 | if (irq_pin < 16) |
| 354 | offs = 0x0200; |
| 355 | else |
| 356 | offs = 0x3000; |
| 357 | |
| 358 | return offs + (irq_pin << 5); |
| 359 | } |
| 360 | |
| 361 | static irqreturn_t sh73a0_irq_pin_demux(int irq, void *dev_id) |
| 362 | { |
| 363 | generic_handle_irq(intcs_evt2irq(to_intc_vect(irq))); |
| 364 | return IRQ_HANDLED; |
| 365 | } |
| 366 | |
| 367 | static struct irqaction sh73a0_irq_pin_cascade[32]; |
| 368 | |
Arnd Bergmann | 0a4b04d | 2012-09-14 20:08:08 +0000 | [diff] [blame] | 369 | #define PINTER0_PHYS 0xe69000a0 |
| 370 | #define PINTER1_PHYS 0xe69000a4 |
| 371 | #define PINTER0_VIRT IOMEM(0xe69000a0) |
| 372 | #define PINTER1_VIRT IOMEM(0xe69000a4) |
| 373 | #define PINTRR0 IOMEM(0xe69000d0) |
| 374 | #define PINTRR1 IOMEM(0xe69000d4) |
Magnus Damm | 566aad3 | 2011-10-17 18:00:52 +0900 | [diff] [blame] | 375 | |
| 376 | #define PINT0A_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq)) |
| 377 | #define PINT0B_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq + 8)) |
| 378 | #define PINT0C_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq + 16)) |
| 379 | #define PINT0D_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq + 24)) |
| 380 | #define PINT1E_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT1_IRQ(irq)) |
| 381 | |
Arnd Bergmann | 0a4b04d | 2012-09-14 20:08:08 +0000 | [diff] [blame] | 382 | INTC_PINT(intc_pint0, PINTER0_PHYS, 0xe69000b0, "sh73a0-pint0", \ |
Magnus Damm | 566aad3 | 2011-10-17 18:00:52 +0900 | [diff] [blame] | 383 | INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D), \ |
| 384 | INTC_PINT_V(A, PINT0A_IRQ), INTC_PINT_V(B, PINT0B_IRQ), \ |
| 385 | INTC_PINT_V(C, PINT0C_IRQ), INTC_PINT_V(D, PINT0D_IRQ), \ |
| 386 | INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D), \ |
| 387 | INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D)); |
| 388 | |
Arnd Bergmann | 0a4b04d | 2012-09-14 20:08:08 +0000 | [diff] [blame] | 389 | INTC_PINT(intc_pint1, PINTER1_PHYS, 0xe69000c0, "sh73a0-pint1", \ |
Magnus Damm | 566aad3 | 2011-10-17 18:00:52 +0900 | [diff] [blame] | 390 | INTC_PINT_E(E), INTC_PINT_E_EMPTY, INTC_PINT_E_EMPTY, INTC_PINT_E_EMPTY, \ |
| 391 | INTC_PINT_V(E, PINT1E_IRQ), INTC_PINT_V_NONE, \ |
| 392 | INTC_PINT_V_NONE, INTC_PINT_V_NONE, \ |
| 393 | INTC_PINT_E_NONE, INTC_PINT_E_NONE, INTC_PINT_E_NONE, INTC_PINT_E(E), \ |
| 394 | INTC_PINT_E(E), INTC_PINT_E_NONE, INTC_PINT_E_NONE, INTC_PINT_E_NONE); |
| 395 | |
| 396 | static struct irqaction sh73a0_pint0_cascade; |
| 397 | static struct irqaction sh73a0_pint1_cascade; |
| 398 | |
Arnd Bergmann | 0a4b04d | 2012-09-14 20:08:08 +0000 | [diff] [blame] | 399 | static void pint_demux(void __iomem *rr, void __iomem *er, int base_irq) |
Magnus Damm | 566aad3 | 2011-10-17 18:00:52 +0900 | [diff] [blame] | 400 | { |
| 401 | unsigned long value = ioread32(rr) & ioread32(er); |
| 402 | int k; |
| 403 | |
| 404 | for (k = 0; k < 32; k++) { |
| 405 | if (value & (1 << (31 - k))) { |
| 406 | generic_handle_irq(base_irq + k); |
| 407 | iowrite32(~(1 << (31 - k)), rr); |
| 408 | } |
| 409 | } |
| 410 | } |
| 411 | |
| 412 | static irqreturn_t sh73a0_pint0_demux(int irq, void *dev_id) |
| 413 | { |
Arnd Bergmann | 0a4b04d | 2012-09-14 20:08:08 +0000 | [diff] [blame] | 414 | pint_demux(PINTRR0, PINTER0_VIRT, SH73A0_PINT0_IRQ(0)); |
Magnus Damm | 566aad3 | 2011-10-17 18:00:52 +0900 | [diff] [blame] | 415 | return IRQ_HANDLED; |
| 416 | } |
| 417 | |
| 418 | static irqreturn_t sh73a0_pint1_demux(int irq, void *dev_id) |
| 419 | { |
Arnd Bergmann | 0a4b04d | 2012-09-14 20:08:08 +0000 | [diff] [blame] | 420 | pint_demux(PINTRR1, PINTER1_VIRT, SH73A0_PINT1_IRQ(0)); |
Magnus Damm | 566aad3 | 2011-10-17 18:00:52 +0900 | [diff] [blame] | 421 | return IRQ_HANDLED; |
| 422 | } |
| 423 | |
Magnus Damm | 5f53a56 | 2010-12-21 08:37:32 +0000 | [diff] [blame] | 424 | void __init sh73a0_init_irq(void) |
| 425 | { |
Rob Herring | a2a47ca | 2012-03-09 17:16:40 -0600 | [diff] [blame] | 426 | void __iomem *gic_dist_base = IOMEM(0xf0001000); |
| 427 | void __iomem *gic_cpu_base = IOMEM(0xf0000100); |
Magnus Damm | 5f53a56 | 2010-12-21 08:37:32 +0000 | [diff] [blame] | 428 | void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE); |
Magnus Damm | a199305 | 2011-10-12 16:21:42 +0900 | [diff] [blame] | 429 | int k, n; |
Magnus Damm | 5f53a56 | 2010-12-21 08:37:32 +0000 | [diff] [blame] | 430 | |
Yoshii Takashi | bd1689c | 2011-01-13 13:17:15 +0000 | [diff] [blame] | 431 | gic_init(0, 29, gic_dist_base, gic_cpu_base); |
Magnus Damm | 485b2ab | 2011-06-09 06:20:03 +0000 | [diff] [blame] | 432 | gic_arch_extn.irq_set_wake = sh73a0_set_wake; |
Magnus Damm | 5f53a56 | 2010-12-21 08:37:32 +0000 | [diff] [blame] | 433 | |
| 434 | register_intc_controller(&intcs_desc); |
Magnus Damm | a199305 | 2011-10-12 16:21:42 +0900 | [diff] [blame] | 435 | register_intc_controller(&intca_irq_pins_desc); |
Magnus Damm | 566aad3 | 2011-10-17 18:00:52 +0900 | [diff] [blame] | 436 | register_intc_controller(&intc_pint0_desc); |
| 437 | register_intc_controller(&intc_pint1_desc); |
Magnus Damm | 5f53a56 | 2010-12-21 08:37:32 +0000 | [diff] [blame] | 438 | |
| 439 | /* demux using INTEVTSA */ |
| 440 | sh73a0_intcs_cascade.name = "INTCS cascade"; |
| 441 | sh73a0_intcs_cascade.handler = sh73a0_intcs_demux; |
| 442 | sh73a0_intcs_cascade.dev_id = intevtsa; |
| 443 | setup_irq(gic_spi(50), &sh73a0_intcs_cascade); |
Magnus Damm | a199305 | 2011-10-12 16:21:42 +0900 | [diff] [blame] | 444 | |
| 445 | /* IRQ pins require special handling through INTCA and GIC */ |
| 446 | for (k = 0; k < 32; k++) { |
| 447 | sh73a0_irq_pin_cascade[k].name = "INTCA-GIC cascade"; |
| 448 | sh73a0_irq_pin_cascade[k].handler = sh73a0_irq_pin_demux; |
| 449 | setup_irq(gic_spi(1 + k), &sh73a0_irq_pin_cascade[k]); |
| 450 | |
| 451 | n = intcs_evt2irq(to_intc_vect(gic_spi(1 + k))); |
Magnus Damm | e2c31b3 | 2012-01-17 20:10:49 +0900 | [diff] [blame] | 452 | WARN_ON(irq_alloc_desc_at(n, numa_node_id()) != n); |
Magnus Damm | a199305 | 2011-10-12 16:21:42 +0900 | [diff] [blame] | 453 | irq_set_chip_and_handler_name(n, &intca_gic_irq_chip, |
| 454 | handle_level_irq, "level"); |
| 455 | set_irq_flags(n, IRQF_VALID); /* yuck */ |
| 456 | } |
Magnus Damm | 566aad3 | 2011-10-17 18:00:52 +0900 | [diff] [blame] | 457 | |
| 458 | /* PINT pins are sanely tied to the GIC as SPI */ |
| 459 | sh73a0_pint0_cascade.name = "PINT0 cascade"; |
| 460 | sh73a0_pint0_cascade.handler = sh73a0_pint0_demux; |
| 461 | setup_irq(gic_spi(33), &sh73a0_pint0_cascade); |
| 462 | |
| 463 | sh73a0_pint1_cascade.name = "PINT1 cascade"; |
| 464 | sh73a0_pint1_cascade.handler = sh73a0_pint1_demux; |
| 465 | setup_irq(gic_spi(34), &sh73a0_pint1_cascade); |
Magnus Damm | 5f53a56 | 2010-12-21 08:37:32 +0000 | [diff] [blame] | 466 | } |