blob: 35c274177da88bf4712665304f40b27cc38eb481 [file] [log] [blame]
Zhi Wang82d375d2016-07-05 12:40:49 -04001/*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Eddie Dong <eddie.dong@intel.com>
25 * Kevin Tian <kevin.tian@intel.com>
26 *
27 * Contributors:
28 * Ping Gao <ping.a.gao@intel.com>
29 * Zhi Wang <zhi.a.wang@intel.com>
30 * Bing Niu <bing.niu@intel.com>
31 *
32 */
33
34#include "i915_drv.h"
Zhenyu Wangfeddf6e2016-10-20 17:15:03 +080035#include "gvt.h"
36#include "i915_pvinfo.h"
Zhi Wang82d375d2016-07-05 12:40:49 -040037
38static void clean_vgpu_mmio(struct intel_vgpu *vgpu)
39{
40 vfree(vgpu->mmio.vreg);
41 vgpu->mmio.vreg = vgpu->mmio.sreg = NULL;
42}
43
Ping Gao23736d12016-10-26 09:38:52 +080044int setup_vgpu_mmio(struct intel_vgpu *vgpu)
Zhi Wang82d375d2016-07-05 12:40:49 -040045{
46 struct intel_gvt *gvt = vgpu->gvt;
47 const struct intel_gvt_device_info *info = &gvt->device_info;
48
Du, Changbinf4b0c282016-11-11 10:31:37 +080049 if (vgpu->mmio.vreg)
50 memset(vgpu->mmio.vreg, 0, info->mmio_size * 2);
51 else {
52 vgpu->mmio.vreg = vzalloc(info->mmio_size * 2);
53 if (!vgpu->mmio.vreg)
54 return -ENOMEM;
55 }
Zhi Wang82d375d2016-07-05 12:40:49 -040056
57 vgpu->mmio.sreg = vgpu->mmio.vreg + info->mmio_size;
58
59 memcpy(vgpu->mmio.vreg, gvt->firmware.mmio, info->mmio_size);
60 memcpy(vgpu->mmio.sreg, gvt->firmware.mmio, info->mmio_size);
Zhi Wange39c5ad2016-09-02 13:33:29 +080061
62 vgpu_vreg(vgpu, GEN6_GT_THREAD_STATUS_REG) = 0;
63
64 /* set the bit 0:2(Core C-State ) to C0 */
65 vgpu_vreg(vgpu, GEN6_GT_CORE_STATUS) = 0;
Zhi Wang82d375d2016-07-05 12:40:49 -040066 return 0;
67}
68
Ping Gao23736d12016-10-26 09:38:52 +080069void populate_pvinfo_page(struct intel_vgpu *vgpu)
Zhi Wang82d375d2016-07-05 12:40:49 -040070{
71 /* setup the ballooning information */
72 vgpu_vreg64(vgpu, vgtif_reg(magic)) = VGT_MAGIC;
73 vgpu_vreg(vgpu, vgtif_reg(version_major)) = 1;
74 vgpu_vreg(vgpu, vgtif_reg(version_minor)) = 0;
75 vgpu_vreg(vgpu, vgtif_reg(display_ready)) = 0;
76 vgpu_vreg(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
77 vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) =
78 vgpu_aperture_gmadr_base(vgpu);
79 vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.size)) =
80 vgpu_aperture_sz(vgpu);
81 vgpu_vreg(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base)) =
82 vgpu_hidden_gmadr_base(vgpu);
83 vgpu_vreg(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.size)) =
84 vgpu_hidden_sz(vgpu);
85
86 vgpu_vreg(vgpu, vgtif_reg(avail_rs.fence_num)) = vgpu_fence_sz(vgpu);
87
88 gvt_dbg_core("Populate PVINFO PAGE for vGPU %d\n", vgpu->id);
89 gvt_dbg_core("aperture base [GMADR] 0x%llx size 0x%llx\n",
90 vgpu_aperture_gmadr_base(vgpu), vgpu_aperture_sz(vgpu));
91 gvt_dbg_core("hidden base [GMADR] 0x%llx size=0x%llx\n",
92 vgpu_hidden_gmadr_base(vgpu), vgpu_hidden_sz(vgpu));
93 gvt_dbg_core("fence size %d\n", vgpu_fence_sz(vgpu));
94
95 WARN_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
96}
97
98/**
Zhenyu Wang1f31c822016-11-03 18:38:31 +080099 * intel_gvt_init_vgpu_types - initialize vGPU type list
100 * @gvt : GVT device
101 *
102 * Initialize vGPU type list based on available resource.
103 *
104 */
105int intel_gvt_init_vgpu_types(struct intel_gvt *gvt)
106{
107 unsigned int num_types;
108 unsigned int i, low_avail;
109 unsigned int min_low;
110
111 /* vGPU type name is defined as GVTg_Vx_y which contains
112 * physical GPU generation type and 'y' means maximum vGPU
113 * instances user can create on one physical GPU for this
114 * type.
115 *
116 * Depend on physical SKU resource, might see vGPU types like
117 * GVTg_V4_8, GVTg_V4_4, GVTg_V4_2, etc. We can create
118 * different types of vGPU on same physical GPU depending on
119 * available resource. Each vGPU type will have "avail_instance"
120 * to indicate how many vGPU instance can be created for this
121 * type.
122 *
123 * Currently use static size here as we init type earlier..
124 */
125 low_avail = MB_TO_BYTES(256) - HOST_LOW_GM_SIZE;
126 num_types = 4;
127
128 gvt->types = kzalloc(num_types * sizeof(struct intel_vgpu_type),
129 GFP_KERNEL);
130 if (!gvt->types)
131 return -ENOMEM;
132
133 min_low = MB_TO_BYTES(32);
134 for (i = 0; i < num_types; ++i) {
135 if (low_avail / min_low == 0)
136 break;
137 gvt->types[i].low_gm_size = min_low;
Zhenyu Wang888530b2017-01-05 10:26:13 +0800138 gvt->types[i].high_gm_size = max((min_low<<3), MB_TO_BYTES(384U));
Zhenyu Wang1f31c822016-11-03 18:38:31 +0800139 gvt->types[i].fence = 4;
140 gvt->types[i].max_instance = low_avail / min_low;
141 gvt->types[i].avail_instance = gvt->types[i].max_instance;
142
143 if (IS_GEN8(gvt->dev_priv))
144 sprintf(gvt->types[i].name, "GVTg_V4_%u",
145 gvt->types[i].max_instance);
146 else if (IS_GEN9(gvt->dev_priv))
147 sprintf(gvt->types[i].name, "GVTg_V5_%u",
148 gvt->types[i].max_instance);
149
150 min_low <<= 1;
151 gvt_dbg_core("type[%d]: %s max %u avail %u low %u high %u fence %u\n",
152 i, gvt->types[i].name, gvt->types[i].max_instance,
153 gvt->types[i].avail_instance,
154 gvt->types[i].low_gm_size,
155 gvt->types[i].high_gm_size, gvt->types[i].fence);
156 }
157
158 gvt->num_types = i;
159 return 0;
160}
161
162void intel_gvt_clean_vgpu_types(struct intel_gvt *gvt)
163{
164 kfree(gvt->types);
165}
166
167static void intel_gvt_update_vgpu_types(struct intel_gvt *gvt)
168{
169 int i;
170 unsigned int low_gm_avail, high_gm_avail, fence_avail;
171 unsigned int low_gm_min, high_gm_min, fence_min, total_min;
172
173 /* Need to depend on maxium hw resource size but keep on
174 * static config for now.
175 */
176 low_gm_avail = MB_TO_BYTES(256) - HOST_LOW_GM_SIZE -
177 gvt->gm.vgpu_allocated_low_gm_size;
Zhenyu Wang888530b2017-01-05 10:26:13 +0800178 high_gm_avail = MB_TO_BYTES(256) * 8UL - HOST_HIGH_GM_SIZE -
Zhenyu Wang1f31c822016-11-03 18:38:31 +0800179 gvt->gm.vgpu_allocated_high_gm_size;
180 fence_avail = gvt_fence_sz(gvt) - HOST_FENCE -
181 gvt->fence.vgpu_allocated_fence_num;
182
183 for (i = 0; i < gvt->num_types; i++) {
184 low_gm_min = low_gm_avail / gvt->types[i].low_gm_size;
185 high_gm_min = high_gm_avail / gvt->types[i].high_gm_size;
186 fence_min = fence_avail / gvt->types[i].fence;
187 total_min = min(min(low_gm_min, high_gm_min), fence_min);
188 gvt->types[i].avail_instance = min(gvt->types[i].max_instance,
189 total_min);
190
191 gvt_dbg_core("update type[%d]: %s max %u avail %u low %u high %u fence %u\n",
192 i, gvt->types[i].name, gvt->types[i].max_instance,
193 gvt->types[i].avail_instance, gvt->types[i].low_gm_size,
194 gvt->types[i].high_gm_size, gvt->types[i].fence);
195 }
196}
197
198/**
Zhi Wang82d375d2016-07-05 12:40:49 -0400199 * intel_gvt_destroy_vgpu - destroy a virtual GPU
200 * @vgpu: virtual GPU
201 *
202 * This function is called when user wants to destroy a virtual GPU.
203 *
204 */
205void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu)
206{
207 struct intel_gvt *gvt = vgpu->gvt;
208
209 mutex_lock(&gvt->lock);
210
211 vgpu->active = false;
212 idr_remove(&gvt->vgpu_idr, vgpu->id);
213
Zhi Wang4b639602016-05-01 17:09:58 -0400214 if (atomic_read(&vgpu->running_workload_num)) {
215 mutex_unlock(&gvt->lock);
216 intel_gvt_wait_vgpu_idle(vgpu);
217 mutex_lock(&gvt->lock);
218 }
219
220 intel_vgpu_stop_schedule(vgpu);
221 intel_vgpu_clean_sched_policy(vgpu);
Zhi Wange4734052016-05-01 07:42:16 -0400222 intel_vgpu_clean_gvt_context(vgpu);
Zhi Wang28c4c6c2016-05-01 05:22:47 -0400223 intel_vgpu_clean_execlist(vgpu);
Zhi Wang04d348a2016-04-25 18:28:56 -0400224 intel_vgpu_clean_display(vgpu);
Zhi Wang4d60c5fd2016-07-20 01:14:38 -0400225 intel_vgpu_clean_opregion(vgpu);
Zhi Wang2707e442016-03-28 23:23:16 +0800226 intel_vgpu_clean_gtt(vgpu);
Zhi Wang82d375d2016-07-05 12:40:49 -0400227 intel_gvt_hypervisor_detach_vgpu(vgpu);
228 intel_vgpu_free_resource(vgpu);
229 clean_vgpu_mmio(vgpu);
230 vfree(vgpu);
231
Zhenyu Wang1f31c822016-11-03 18:38:31 +0800232 intel_gvt_update_vgpu_types(gvt);
Zhi Wang82d375d2016-07-05 12:40:49 -0400233 mutex_unlock(&gvt->lock);
234}
235
Zhenyu Wang1f31c822016-11-03 18:38:31 +0800236static struct intel_vgpu *__intel_gvt_create_vgpu(struct intel_gvt *gvt,
Zhi Wang82d375d2016-07-05 12:40:49 -0400237 struct intel_vgpu_creation_params *param)
238{
239 struct intel_vgpu *vgpu;
240 int ret;
241
242 gvt_dbg_core("handle %llu low %llu MB high %llu MB fence %llu\n",
243 param->handle, param->low_gm_sz, param->high_gm_sz,
244 param->fence_sz);
245
246 vgpu = vzalloc(sizeof(*vgpu));
247 if (!vgpu)
248 return ERR_PTR(-ENOMEM);
249
250 mutex_lock(&gvt->lock);
251
252 ret = idr_alloc(&gvt->vgpu_idr, vgpu, 1, GVT_MAX_VGPU, GFP_KERNEL);
253 if (ret < 0)
254 goto out_free_vgpu;
255
256 vgpu->id = ret;
257 vgpu->handle = param->handle;
258 vgpu->gvt = gvt;
Zhi Wang17865712016-05-01 19:02:37 -0400259 bitmap_zero(vgpu->tlb_handle_pending, I915_NUM_ENGINES);
Zhi Wang82d375d2016-07-05 12:40:49 -0400260
Changbin Du536fc232017-01-13 11:15:58 +0800261 intel_vgpu_init_cfg_space(vgpu, param->primary);
Zhi Wang82d375d2016-07-05 12:40:49 -0400262
263 ret = setup_vgpu_mmio(vgpu);
264 if (ret)
Jike Song4e537892017-01-06 15:16:22 +0800265 goto out_clean_idr;
Zhi Wang82d375d2016-07-05 12:40:49 -0400266
267 ret = intel_vgpu_alloc_resource(vgpu, param);
268 if (ret)
269 goto out_clean_vgpu_mmio;
270
271 populate_pvinfo_page(vgpu);
272
273 ret = intel_gvt_hypervisor_attach_vgpu(vgpu);
274 if (ret)
275 goto out_clean_vgpu_resource;
276
Zhi Wang2707e442016-03-28 23:23:16 +0800277 ret = intel_vgpu_init_gtt(vgpu);
278 if (ret)
279 goto out_detach_hypervisor_vgpu;
280
Zhi Wang04d348a2016-04-25 18:28:56 -0400281 ret = intel_vgpu_init_display(vgpu);
282 if (ret)
Jike Song8f897432016-11-03 18:38:32 +0800283 goto out_clean_gtt;
Zhi Wang04d348a2016-04-25 18:28:56 -0400284
Zhi Wang8453d672016-05-01 02:48:25 -0400285 ret = intel_vgpu_init_execlist(vgpu);
286 if (ret)
287 goto out_clean_display;
288
Zhi Wange4734052016-05-01 07:42:16 -0400289 ret = intel_vgpu_init_gvt_context(vgpu);
290 if (ret)
291 goto out_clean_execlist;
292
Zhi Wang4b639602016-05-01 17:09:58 -0400293 ret = intel_vgpu_init_sched_policy(vgpu);
294 if (ret)
295 goto out_clean_shadow_ctx;
296
Zhi Wang82d375d2016-07-05 12:40:49 -0400297 vgpu->active = true;
298 mutex_unlock(&gvt->lock);
299
300 return vgpu;
301
Zhi Wang4b639602016-05-01 17:09:58 -0400302out_clean_shadow_ctx:
303 intel_vgpu_clean_gvt_context(vgpu);
Zhi Wange4734052016-05-01 07:42:16 -0400304out_clean_execlist:
305 intel_vgpu_clean_execlist(vgpu);
Zhi Wang8453d672016-05-01 02:48:25 -0400306out_clean_display:
307 intel_vgpu_clean_display(vgpu);
Zhi Wang4d60c5fd2016-07-20 01:14:38 -0400308out_clean_gtt:
309 intel_vgpu_clean_gtt(vgpu);
Zhi Wang2707e442016-03-28 23:23:16 +0800310out_detach_hypervisor_vgpu:
311 intel_gvt_hypervisor_detach_vgpu(vgpu);
Zhi Wang82d375d2016-07-05 12:40:49 -0400312out_clean_vgpu_resource:
313 intel_vgpu_free_resource(vgpu);
314out_clean_vgpu_mmio:
315 clean_vgpu_mmio(vgpu);
Jike Song4e537892017-01-06 15:16:22 +0800316out_clean_idr:
317 idr_remove(&gvt->vgpu_idr, vgpu->id);
Zhi Wang82d375d2016-07-05 12:40:49 -0400318out_free_vgpu:
319 vfree(vgpu);
320 mutex_unlock(&gvt->lock);
321 return ERR_PTR(ret);
322}
Zhenyu Wang1f31c822016-11-03 18:38:31 +0800323
324/**
325 * intel_gvt_create_vgpu - create a virtual GPU
326 * @gvt: GVT device
327 * @type: type of the vGPU to create
328 *
329 * This function is called when user wants to create a virtual GPU.
330 *
331 * Returns:
332 * pointer to intel_vgpu, error pointer if failed.
333 */
334struct intel_vgpu *intel_gvt_create_vgpu(struct intel_gvt *gvt,
335 struct intel_vgpu_type *type)
336{
337 struct intel_vgpu_creation_params param;
338 struct intel_vgpu *vgpu;
339
340 param.handle = 0;
Du, Changbine992fae2016-11-21 17:08:14 +0800341 param.primary = 1;
Zhenyu Wang1f31c822016-11-03 18:38:31 +0800342 param.low_gm_sz = type->low_gm_size;
343 param.high_gm_sz = type->high_gm_size;
344 param.fence_sz = type->fence;
345
346 /* XXX current param based on MB */
347 param.low_gm_sz = BYTES_TO_MB(param.low_gm_sz);
348 param.high_gm_sz = BYTES_TO_MB(param.high_gm_sz);
349
350 vgpu = __intel_gvt_create_vgpu(gvt, &param);
351 if (IS_ERR(vgpu))
352 return vgpu;
353
354 /* calculate left instance change for types */
355 intel_gvt_update_vgpu_types(gvt);
356
357 return vgpu;
358}
Jike Song9ec1e662016-11-03 18:38:35 +0800359
360/**
361 * intel_gvt_reset_vgpu - reset a virtual GPU
362 * @vgpu: virtual GPU
363 *
364 * This function is called when user wants to reset a virtual GPU.
365 *
366 */
367void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu)
368{
369}