Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1 | /******************************************************************************* |
| 2 | |
| 3 | Intel PRO/1000 Linux driver |
Bruce Allan | bf67044 | 2013-01-01 16:00:01 +0000 | [diff] [blame] | 4 | Copyright(c) 1999 - 2013 Intel Corporation. |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5 | |
| 6 | This program is free software; you can redistribute it and/or modify it |
| 7 | under the terms and conditions of the GNU General Public License, |
| 8 | version 2, as published by the Free Software Foundation. |
| 9 | |
| 10 | This program is distributed in the hope it will be useful, but WITHOUT |
| 11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | more details. |
| 14 | |
| 15 | You should have received a copy of the GNU General Public License along with |
| 16 | this program; if not, write to the Free Software Foundation, Inc., |
| 17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
| 18 | |
| 19 | The full GNU General Public License is included in this distribution in |
| 20 | the file called "COPYING". |
| 21 | |
| 22 | Contact Information: |
| 23 | Linux NICS <linux.nics@intel.com> |
| 24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
| 25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
| 26 | |
| 27 | *******************************************************************************/ |
| 28 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 29 | #include "e1000.h" |
| 30 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 31 | static s32 e1000_wait_autoneg(struct e1000_hw *hw); |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 32 | static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 33 | u16 *data, bool read, bool page_set); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 34 | static u32 e1000_get_phy_addr_for_hv_page(u32 page); |
| 35 | static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, |
Bruce Allan | 1f96012d | 2013-01-05 03:06:54 +0000 | [diff] [blame] | 36 | u16 *data, bool read); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 37 | |
| 38 | /* Cable length tables */ |
Bruce Allan | 6480641 | 2010-12-11 05:53:42 +0000 | [diff] [blame] | 39 | static const u16 e1000_m88_cable_length_table[] = { |
| 40 | 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED }; |
Bruce Allan | eb656d4 | 2009-12-01 15:47:02 +0000 | [diff] [blame] | 41 | #define M88E1000_CABLE_LENGTH_TABLE_SIZE \ |
| 42 | ARRAY_SIZE(e1000_m88_cable_length_table) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 43 | |
Bruce Allan | 6480641 | 2010-12-11 05:53:42 +0000 | [diff] [blame] | 44 | static const u16 e1000_igp_2_cable_length_table[] = { |
| 45 | 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3, |
| 46 | 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22, |
| 47 | 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40, |
| 48 | 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61, |
| 49 | 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82, |
| 50 | 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95, |
| 51 | 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121, |
| 52 | 124}; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 53 | #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ |
Alejandro Martinez Ruiz | c00acf4 | 2007-10-18 10:16:33 +0200 | [diff] [blame] | 54 | ARRAY_SIZE(e1000_igp_2_cable_length_table) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 55 | |
| 56 | /** |
| 57 | * e1000e_check_reset_block_generic - Check if PHY reset is blocked |
| 58 | * @hw: pointer to the HW structure |
| 59 | * |
| 60 | * Read the PHY management control register and check whether a PHY reset |
| 61 | * is blocked. If a reset is not blocked return 0, otherwise |
| 62 | * return E1000_BLK_PHY_RESET (12). |
| 63 | **/ |
| 64 | s32 e1000e_check_reset_block_generic(struct e1000_hw *hw) |
| 65 | { |
| 66 | u32 manc; |
| 67 | |
| 68 | manc = er32(MANC); |
| 69 | |
| 70 | return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? |
| 71 | E1000_BLK_PHY_RESET : 0; |
| 72 | } |
| 73 | |
| 74 | /** |
| 75 | * e1000e_get_phy_id - Retrieve the PHY ID and revision |
| 76 | * @hw: pointer to the HW structure |
| 77 | * |
| 78 | * Reads the PHY registers and stores the PHY ID and possibly the PHY |
| 79 | * revision in the hardware structure. |
| 80 | **/ |
| 81 | s32 e1000e_get_phy_id(struct e1000_hw *hw) |
| 82 | { |
| 83 | struct e1000_phy_info *phy = &hw->phy; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 84 | s32 ret_val = 0; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 85 | u16 phy_id; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 86 | u16 retry_count = 0; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 87 | |
Bruce Allan | 668018d | 2012-01-31 07:02:56 +0000 | [diff] [blame] | 88 | if (!phy->ops.read_reg) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 89 | return 0; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 90 | |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 91 | while (retry_count < 2) { |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 92 | ret_val = e1e_rphy(hw, MII_PHYSID1, &phy_id); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 93 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 94 | return ret_val; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 95 | |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 96 | phy->id = (u32)(phy_id << 16); |
| 97 | udelay(20); |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 98 | ret_val = e1e_rphy(hw, MII_PHYSID2, &phy_id); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 99 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 100 | return ret_val; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 101 | |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 102 | phy->id |= (u32)(phy_id & PHY_REVISION_MASK); |
| 103 | phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); |
| 104 | |
| 105 | if (phy->id != 0 && phy->id != PHY_REVISION_MASK) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 106 | return 0; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 107 | |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 108 | retry_count++; |
| 109 | } |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 110 | |
| 111 | return 0; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 112 | } |
| 113 | |
| 114 | /** |
| 115 | * e1000e_phy_reset_dsp - Reset PHY DSP |
| 116 | * @hw: pointer to the HW structure |
| 117 | * |
| 118 | * Reset the digital signal processor. |
| 119 | **/ |
| 120 | s32 e1000e_phy_reset_dsp(struct e1000_hw *hw) |
| 121 | { |
| 122 | s32 ret_val; |
| 123 | |
| 124 | ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); |
| 125 | if (ret_val) |
| 126 | return ret_val; |
| 127 | |
| 128 | return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0); |
| 129 | } |
| 130 | |
| 131 | /** |
David Graham | 2d9498f | 2008-04-23 11:09:14 -0700 | [diff] [blame] | 132 | * e1000e_read_phy_reg_mdic - Read MDI control register |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 133 | * @hw: pointer to the HW structure |
| 134 | * @offset: register offset to be read |
| 135 | * @data: pointer to the read data |
| 136 | * |
Auke Kok | 489815c | 2008-02-21 15:11:07 -0800 | [diff] [blame] | 137 | * Reads the MDI control register in the PHY at offset and stores the |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 138 | * information read to data. |
| 139 | **/ |
David Graham | 2d9498f | 2008-04-23 11:09:14 -0700 | [diff] [blame] | 140 | s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 141 | { |
| 142 | struct e1000_phy_info *phy = &hw->phy; |
| 143 | u32 i, mdic = 0; |
| 144 | |
| 145 | if (offset > MAX_PHY_REG_ADDRESS) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 146 | e_dbg("PHY Address %d is out of range\n", offset); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 147 | return -E1000_ERR_PARAM; |
| 148 | } |
| 149 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 150 | /* Set up Op-code, Phy Address, and register offset in the MDI |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 151 | * Control register. The MAC will take care of interfacing with the |
| 152 | * PHY to retrieve the desired data. |
| 153 | */ |
| 154 | mdic = ((offset << E1000_MDIC_REG_SHIFT) | |
| 155 | (phy->addr << E1000_MDIC_PHY_SHIFT) | |
| 156 | (E1000_MDIC_OP_READ)); |
| 157 | |
| 158 | ew32(MDIC, mdic); |
| 159 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 160 | /* Poll the ready bit to see if the MDI read completed |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 161 | * Increasing the time out as testing showed failures with |
| 162 | * the lower time out |
| 163 | */ |
David Graham | 2d9498f | 2008-04-23 11:09:14 -0700 | [diff] [blame] | 164 | for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 165 | udelay(50); |
| 166 | mdic = er32(MDIC); |
| 167 | if (mdic & E1000_MDIC_READY) |
| 168 | break; |
| 169 | } |
| 170 | if (!(mdic & E1000_MDIC_READY)) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 171 | e_dbg("MDI Read did not complete\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 172 | return -E1000_ERR_PHY; |
| 173 | } |
| 174 | if (mdic & E1000_MDIC_ERROR) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 175 | e_dbg("MDI Error\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 176 | return -E1000_ERR_PHY; |
| 177 | } |
Bruce Allan | 53aa82d | 2013-02-20 04:06:06 +0000 | [diff] [blame^] | 178 | *data = (u16)mdic; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 179 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 180 | /* Allow some time after each MDIC transaction to avoid |
Bruce Allan | 664dc87 | 2010-11-24 06:01:46 +0000 | [diff] [blame] | 181 | * reading duplicate data in the next MDIC transaction. |
| 182 | */ |
| 183 | if (hw->mac.type == e1000_pch2lan) |
| 184 | udelay(100); |
| 185 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 186 | return 0; |
| 187 | } |
| 188 | |
| 189 | /** |
David Graham | 2d9498f | 2008-04-23 11:09:14 -0700 | [diff] [blame] | 190 | * e1000e_write_phy_reg_mdic - Write MDI control register |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 191 | * @hw: pointer to the HW structure |
| 192 | * @offset: register offset to write to |
| 193 | * @data: data to write to register at offset |
| 194 | * |
| 195 | * Writes data to MDI control register in the PHY at offset. |
| 196 | **/ |
David Graham | 2d9498f | 2008-04-23 11:09:14 -0700 | [diff] [blame] | 197 | s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 198 | { |
| 199 | struct e1000_phy_info *phy = &hw->phy; |
| 200 | u32 i, mdic = 0; |
| 201 | |
| 202 | if (offset > MAX_PHY_REG_ADDRESS) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 203 | e_dbg("PHY Address %d is out of range\n", offset); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 204 | return -E1000_ERR_PARAM; |
| 205 | } |
| 206 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 207 | /* Set up Op-code, Phy Address, and register offset in the MDI |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 208 | * Control register. The MAC will take care of interfacing with the |
| 209 | * PHY to retrieve the desired data. |
| 210 | */ |
| 211 | mdic = (((u32)data) | |
| 212 | (offset << E1000_MDIC_REG_SHIFT) | |
| 213 | (phy->addr << E1000_MDIC_PHY_SHIFT) | |
| 214 | (E1000_MDIC_OP_WRITE)); |
| 215 | |
| 216 | ew32(MDIC, mdic); |
| 217 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 218 | /* Poll the ready bit to see if the MDI read completed |
David Graham | 2d9498f | 2008-04-23 11:09:14 -0700 | [diff] [blame] | 219 | * Increasing the time out as testing showed failures with |
| 220 | * the lower time out |
| 221 | */ |
| 222 | for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { |
| 223 | udelay(50); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 224 | mdic = er32(MDIC); |
| 225 | if (mdic & E1000_MDIC_READY) |
| 226 | break; |
| 227 | } |
| 228 | if (!(mdic & E1000_MDIC_READY)) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 229 | e_dbg("MDI Write did not complete\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 230 | return -E1000_ERR_PHY; |
| 231 | } |
David Graham | 2d9498f | 2008-04-23 11:09:14 -0700 | [diff] [blame] | 232 | if (mdic & E1000_MDIC_ERROR) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 233 | e_dbg("MDI Error\n"); |
David Graham | 2d9498f | 2008-04-23 11:09:14 -0700 | [diff] [blame] | 234 | return -E1000_ERR_PHY; |
| 235 | } |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 236 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 237 | /* Allow some time after each MDIC transaction to avoid |
Bruce Allan | 664dc87 | 2010-11-24 06:01:46 +0000 | [diff] [blame] | 238 | * reading duplicate data in the next MDIC transaction. |
| 239 | */ |
| 240 | if (hw->mac.type == e1000_pch2lan) |
| 241 | udelay(100); |
| 242 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 243 | return 0; |
| 244 | } |
| 245 | |
| 246 | /** |
| 247 | * e1000e_read_phy_reg_m88 - Read m88 PHY register |
| 248 | * @hw: pointer to the HW structure |
| 249 | * @offset: register offset to be read |
| 250 | * @data: pointer to the read data |
| 251 | * |
| 252 | * Acquires semaphore, if necessary, then reads the PHY register at offset |
| 253 | * and storing the retrieved information in data. Release any acquired |
| 254 | * semaphores before exiting. |
| 255 | **/ |
| 256 | s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data) |
| 257 | { |
| 258 | s32 ret_val; |
| 259 | |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 260 | ret_val = hw->phy.ops.acquire(hw); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 261 | if (ret_val) |
| 262 | return ret_val; |
| 263 | |
David Graham | 2d9498f | 2008-04-23 11:09:14 -0700 | [diff] [blame] | 264 | ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
| 265 | data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 266 | |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 267 | hw->phy.ops.release(hw); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 268 | |
| 269 | return ret_val; |
| 270 | } |
| 271 | |
| 272 | /** |
| 273 | * e1000e_write_phy_reg_m88 - Write m88 PHY register |
| 274 | * @hw: pointer to the HW structure |
| 275 | * @offset: register offset to write to |
| 276 | * @data: data to write at register offset |
| 277 | * |
| 278 | * Acquires semaphore, if necessary, then writes the data to PHY register |
| 279 | * at the offset. Release any acquired semaphores before exiting. |
| 280 | **/ |
| 281 | s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data) |
| 282 | { |
| 283 | s32 ret_val; |
| 284 | |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 285 | ret_val = hw->phy.ops.acquire(hw); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 286 | if (ret_val) |
| 287 | return ret_val; |
| 288 | |
David Graham | 2d9498f | 2008-04-23 11:09:14 -0700 | [diff] [blame] | 289 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
| 290 | data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 291 | |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 292 | hw->phy.ops.release(hw); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 293 | |
| 294 | return ret_val; |
| 295 | } |
| 296 | |
| 297 | /** |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 298 | * e1000_set_page_igp - Set page as on IGP-like PHY(s) |
| 299 | * @hw: pointer to the HW structure |
| 300 | * @page: page to set (shifted left when necessary) |
| 301 | * |
| 302 | * Sets PHY page required for PHY register access. Assumes semaphore is |
| 303 | * already acquired. Note, this function sets phy.addr to 1 so the caller |
| 304 | * must set it appropriately (if necessary) after this function returns. |
| 305 | **/ |
| 306 | s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page) |
| 307 | { |
| 308 | e_dbg("Setting page 0x%x\n", page); |
| 309 | |
| 310 | hw->phy.addr = 1; |
| 311 | |
| 312 | return e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page); |
| 313 | } |
| 314 | |
| 315 | /** |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 316 | * __e1000e_read_phy_reg_igp - Read igp PHY register |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 317 | * @hw: pointer to the HW structure |
| 318 | * @offset: register offset to be read |
| 319 | * @data: pointer to the read data |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 320 | * @locked: semaphore has already been acquired or not |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 321 | * |
| 322 | * Acquires semaphore, if necessary, then reads the PHY register at offset |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 323 | * and stores the retrieved information in data. Release any acquired |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 324 | * semaphores before exiting. |
| 325 | **/ |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 326 | static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data, |
Bruce Allan | 66501f5 | 2013-02-20 04:05:55 +0000 | [diff] [blame] | 327 | bool locked) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 328 | { |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 329 | s32 ret_val = 0; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 330 | |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 331 | if (!locked) { |
Bruce Allan | 668018d | 2012-01-31 07:02:56 +0000 | [diff] [blame] | 332 | if (!hw->phy.ops.acquire) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 333 | return 0; |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 334 | |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 335 | ret_val = hw->phy.ops.acquire(hw); |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 336 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 337 | return ret_val; |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 338 | } |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 339 | |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 340 | if (offset > MAX_PHY_MULTI_PAGE_REG) |
David Graham | 2d9498f | 2008-04-23 11:09:14 -0700 | [diff] [blame] | 341 | ret_val = e1000e_write_phy_reg_mdic(hw, |
| 342 | IGP01E1000_PHY_PAGE_SELECT, |
| 343 | (u16)offset); |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 344 | if (!ret_val) |
| 345 | ret_val = e1000e_read_phy_reg_mdic(hw, |
| 346 | MAX_PHY_REG_ADDRESS & offset, |
| 347 | data); |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 348 | if (!locked) |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 349 | hw->phy.ops.release(hw); |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 350 | |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 351 | return ret_val; |
| 352 | } |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 353 | |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 354 | /** |
| 355 | * e1000e_read_phy_reg_igp - Read igp PHY register |
| 356 | * @hw: pointer to the HW structure |
| 357 | * @offset: register offset to be read |
| 358 | * @data: pointer to the read data |
| 359 | * |
| 360 | * Acquires semaphore then reads the PHY register at offset and stores the |
| 361 | * retrieved information in data. |
| 362 | * Release the acquired semaphore before exiting. |
| 363 | **/ |
| 364 | s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) |
| 365 | { |
| 366 | return __e1000e_read_phy_reg_igp(hw, offset, data, false); |
| 367 | } |
| 368 | |
| 369 | /** |
| 370 | * e1000e_read_phy_reg_igp_locked - Read igp PHY register |
| 371 | * @hw: pointer to the HW structure |
| 372 | * @offset: register offset to be read |
| 373 | * @data: pointer to the read data |
| 374 | * |
| 375 | * Reads the PHY register at offset and stores the retrieved information |
| 376 | * in data. Assumes semaphore already acquired. |
| 377 | **/ |
| 378 | s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data) |
| 379 | { |
| 380 | return __e1000e_read_phy_reg_igp(hw, offset, data, true); |
| 381 | } |
| 382 | |
| 383 | /** |
| 384 | * e1000e_write_phy_reg_igp - Write igp PHY register |
| 385 | * @hw: pointer to the HW structure |
| 386 | * @offset: register offset to write to |
| 387 | * @data: data to write at register offset |
| 388 | * @locked: semaphore has already been acquired or not |
| 389 | * |
| 390 | * Acquires semaphore, if necessary, then writes the data to PHY register |
| 391 | * at the offset. Release any acquired semaphores before exiting. |
| 392 | **/ |
| 393 | static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data, |
Bruce Allan | 66501f5 | 2013-02-20 04:05:55 +0000 | [diff] [blame] | 394 | bool locked) |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 395 | { |
| 396 | s32 ret_val = 0; |
| 397 | |
| 398 | if (!locked) { |
Bruce Allan | 668018d | 2012-01-31 07:02:56 +0000 | [diff] [blame] | 399 | if (!hw->phy.ops.acquire) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 400 | return 0; |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 401 | |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 402 | ret_val = hw->phy.ops.acquire(hw); |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 403 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 404 | return ret_val; |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 405 | } |
| 406 | |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 407 | if (offset > MAX_PHY_MULTI_PAGE_REG) |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 408 | ret_val = e1000e_write_phy_reg_mdic(hw, |
| 409 | IGP01E1000_PHY_PAGE_SELECT, |
| 410 | (u16)offset); |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 411 | if (!ret_val) |
| 412 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & |
Bruce Allan | 17e813e | 2013-02-20 04:06:01 +0000 | [diff] [blame] | 413 | offset, data); |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 414 | if (!locked) |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 415 | hw->phy.ops.release(hw); |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 416 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 417 | return ret_val; |
| 418 | } |
| 419 | |
| 420 | /** |
| 421 | * e1000e_write_phy_reg_igp - Write igp PHY register |
| 422 | * @hw: pointer to the HW structure |
| 423 | * @offset: register offset to write to |
| 424 | * @data: data to write at register offset |
| 425 | * |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 426 | * Acquires semaphore then writes the data to PHY register |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 427 | * at the offset. Release any acquired semaphores before exiting. |
| 428 | **/ |
| 429 | s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) |
| 430 | { |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 431 | return __e1000e_write_phy_reg_igp(hw, offset, data, false); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 432 | } |
| 433 | |
| 434 | /** |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 435 | * e1000e_write_phy_reg_igp_locked - Write igp PHY register |
| 436 | * @hw: pointer to the HW structure |
| 437 | * @offset: register offset to write to |
| 438 | * @data: data to write at register offset |
| 439 | * |
| 440 | * Writes the data to PHY register at the offset. |
| 441 | * Assumes semaphore already acquired. |
| 442 | **/ |
| 443 | s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data) |
| 444 | { |
| 445 | return __e1000e_write_phy_reg_igp(hw, offset, data, true); |
| 446 | } |
| 447 | |
| 448 | /** |
| 449 | * __e1000_read_kmrn_reg - Read kumeran register |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 450 | * @hw: pointer to the HW structure |
| 451 | * @offset: register offset to be read |
| 452 | * @data: pointer to the read data |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 453 | * @locked: semaphore has already been acquired or not |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 454 | * |
| 455 | * Acquires semaphore, if necessary. Then reads the PHY register at offset |
| 456 | * using the kumeran interface. The information retrieved is stored in data. |
| 457 | * Release any acquired semaphores before exiting. |
| 458 | **/ |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 459 | static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data, |
Bruce Allan | 66501f5 | 2013-02-20 04:05:55 +0000 | [diff] [blame] | 460 | bool locked) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 461 | { |
| 462 | u32 kmrnctrlsta; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 463 | |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 464 | if (!locked) { |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 465 | s32 ret_val = 0; |
| 466 | |
Bruce Allan | 668018d | 2012-01-31 07:02:56 +0000 | [diff] [blame] | 467 | if (!hw->phy.ops.acquire) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 468 | return 0; |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 469 | |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 470 | ret_val = hw->phy.ops.acquire(hw); |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 471 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 472 | return ret_val; |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 473 | } |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 474 | |
| 475 | kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & |
| 476 | E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; |
| 477 | ew32(KMRNCTRLSTA, kmrnctrlsta); |
Jesse Brandeburg | 945a515 | 2011-07-20 00:56:21 +0000 | [diff] [blame] | 478 | e1e_flush(); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 479 | |
| 480 | udelay(2); |
| 481 | |
| 482 | kmrnctrlsta = er32(KMRNCTRLSTA); |
| 483 | *data = (u16)kmrnctrlsta; |
| 484 | |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 485 | if (!locked) |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 486 | hw->phy.ops.release(hw); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 487 | |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 488 | return 0; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 489 | } |
| 490 | |
| 491 | /** |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 492 | * e1000e_read_kmrn_reg - Read kumeran register |
| 493 | * @hw: pointer to the HW structure |
| 494 | * @offset: register offset to be read |
| 495 | * @data: pointer to the read data |
| 496 | * |
| 497 | * Acquires semaphore then reads the PHY register at offset using the |
| 498 | * kumeran interface. The information retrieved is stored in data. |
| 499 | * Release the acquired semaphore before exiting. |
| 500 | **/ |
| 501 | s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data) |
| 502 | { |
| 503 | return __e1000_read_kmrn_reg(hw, offset, data, false); |
| 504 | } |
| 505 | |
| 506 | /** |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 507 | * e1000e_read_kmrn_reg_locked - Read kumeran register |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 508 | * @hw: pointer to the HW structure |
| 509 | * @offset: register offset to be read |
| 510 | * @data: pointer to the read data |
| 511 | * |
| 512 | * Reads the PHY register at offset using the kumeran interface. The |
| 513 | * information retrieved is stored in data. |
| 514 | * Assumes semaphore already acquired. |
| 515 | **/ |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 516 | s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data) |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 517 | { |
| 518 | return __e1000_read_kmrn_reg(hw, offset, data, true); |
| 519 | } |
| 520 | |
| 521 | /** |
| 522 | * __e1000_write_kmrn_reg - Write kumeran register |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 523 | * @hw: pointer to the HW structure |
| 524 | * @offset: register offset to write to |
| 525 | * @data: data to write at register offset |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 526 | * @locked: semaphore has already been acquired or not |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 527 | * |
| 528 | * Acquires semaphore, if necessary. Then write the data to PHY register |
| 529 | * at the offset using the kumeran interface. Release any acquired semaphores |
| 530 | * before exiting. |
| 531 | **/ |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 532 | static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data, |
Bruce Allan | 66501f5 | 2013-02-20 04:05:55 +0000 | [diff] [blame] | 533 | bool locked) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 534 | { |
| 535 | u32 kmrnctrlsta; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 536 | |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 537 | if (!locked) { |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 538 | s32 ret_val = 0; |
| 539 | |
Bruce Allan | 668018d | 2012-01-31 07:02:56 +0000 | [diff] [blame] | 540 | if (!hw->phy.ops.acquire) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 541 | return 0; |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 542 | |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 543 | ret_val = hw->phy.ops.acquire(hw); |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 544 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 545 | return ret_val; |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 546 | } |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 547 | |
| 548 | kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & |
| 549 | E1000_KMRNCTRLSTA_OFFSET) | data; |
| 550 | ew32(KMRNCTRLSTA, kmrnctrlsta); |
Jesse Brandeburg | 945a515 | 2011-07-20 00:56:21 +0000 | [diff] [blame] | 551 | e1e_flush(); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 552 | |
| 553 | udelay(2); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 554 | |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 555 | if (!locked) |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 556 | hw->phy.ops.release(hw); |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 557 | |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 558 | return 0; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 559 | } |
| 560 | |
| 561 | /** |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 562 | * e1000e_write_kmrn_reg - Write kumeran register |
| 563 | * @hw: pointer to the HW structure |
| 564 | * @offset: register offset to write to |
| 565 | * @data: data to write at register offset |
| 566 | * |
| 567 | * Acquires semaphore then writes the data to the PHY register at the offset |
| 568 | * using the kumeran interface. Release the acquired semaphore before exiting. |
| 569 | **/ |
| 570 | s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data) |
| 571 | { |
| 572 | return __e1000_write_kmrn_reg(hw, offset, data, false); |
| 573 | } |
| 574 | |
| 575 | /** |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 576 | * e1000e_write_kmrn_reg_locked - Write kumeran register |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 577 | * @hw: pointer to the HW structure |
| 578 | * @offset: register offset to write to |
| 579 | * @data: data to write at register offset |
| 580 | * |
| 581 | * Write the data to PHY register at the offset using the kumeran interface. |
| 582 | * Assumes semaphore already acquired. |
| 583 | **/ |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 584 | s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data) |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 585 | { |
| 586 | return __e1000_write_kmrn_reg(hw, offset, data, true); |
| 587 | } |
| 588 | |
| 589 | /** |
Bruce Allan | 7b9f7e3 | 2012-03-20 03:47:41 +0000 | [diff] [blame] | 590 | * e1000_set_master_slave_mode - Setup PHY for Master/slave mode |
| 591 | * @hw: pointer to the HW structure |
| 592 | * |
| 593 | * Sets up Master/slave mode |
| 594 | **/ |
| 595 | static s32 e1000_set_master_slave_mode(struct e1000_hw *hw) |
| 596 | { |
| 597 | s32 ret_val; |
| 598 | u16 phy_data; |
| 599 | |
| 600 | /* Resolve Master/Slave mode */ |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 601 | ret_val = e1e_rphy(hw, MII_CTRL1000, &phy_data); |
Bruce Allan | 7b9f7e3 | 2012-03-20 03:47:41 +0000 | [diff] [blame] | 602 | if (ret_val) |
| 603 | return ret_val; |
| 604 | |
| 605 | /* load defaults for future use */ |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 606 | hw->phy.original_ms_type = (phy_data & CTL1000_ENABLE_MASTER) ? |
| 607 | ((phy_data & CTL1000_AS_MASTER) ? |
Bruce Allan | 7b9f7e3 | 2012-03-20 03:47:41 +0000 | [diff] [blame] | 608 | e1000_ms_force_master : e1000_ms_force_slave) : e1000_ms_auto; |
| 609 | |
| 610 | switch (hw->phy.ms_type) { |
| 611 | case e1000_ms_force_master: |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 612 | phy_data |= (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER); |
Bruce Allan | 7b9f7e3 | 2012-03-20 03:47:41 +0000 | [diff] [blame] | 613 | break; |
| 614 | case e1000_ms_force_slave: |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 615 | phy_data |= CTL1000_ENABLE_MASTER; |
| 616 | phy_data &= ~(CTL1000_AS_MASTER); |
Bruce Allan | 7b9f7e3 | 2012-03-20 03:47:41 +0000 | [diff] [blame] | 617 | break; |
| 618 | case e1000_ms_auto: |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 619 | phy_data &= ~CTL1000_ENABLE_MASTER; |
Bruce Allan | 7b9f7e3 | 2012-03-20 03:47:41 +0000 | [diff] [blame] | 620 | /* fall-through */ |
| 621 | default: |
| 622 | break; |
| 623 | } |
| 624 | |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 625 | return e1e_wphy(hw, MII_CTRL1000, phy_data); |
Bruce Allan | 7b9f7e3 | 2012-03-20 03:47:41 +0000 | [diff] [blame] | 626 | } |
| 627 | |
| 628 | /** |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 629 | * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link |
| 630 | * @hw: pointer to the HW structure |
| 631 | * |
| 632 | * Sets up Carrier-sense on Transmit and downshift values. |
| 633 | **/ |
| 634 | s32 e1000_copper_link_setup_82577(struct e1000_hw *hw) |
| 635 | { |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 636 | s32 ret_val; |
| 637 | u16 phy_data; |
| 638 | |
Bruce Allan | af667a2 | 2010-12-31 06:10:01 +0000 | [diff] [blame] | 639 | /* Enable CRS on Tx. This must be set for half-duplex operation. */ |
Bruce Allan | 482fed8 | 2011-01-06 14:29:49 +0000 | [diff] [blame] | 640 | ret_val = e1e_rphy(hw, I82577_CFG_REG, &phy_data); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 641 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 642 | return ret_val; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 643 | |
| 644 | phy_data |= I82577_CFG_ASSERT_CRS_ON_TX; |
| 645 | |
| 646 | /* Enable downshift */ |
| 647 | phy_data |= I82577_CFG_ENABLE_DOWNSHIFT; |
| 648 | |
Bruce Allan | 7b9f7e3 | 2012-03-20 03:47:41 +0000 | [diff] [blame] | 649 | ret_val = e1e_wphy(hw, I82577_CFG_REG, phy_data); |
| 650 | if (ret_val) |
| 651 | return ret_val; |
| 652 | |
Bruce W Allan | e86fd89 | 2012-07-26 02:30:59 +0000 | [diff] [blame] | 653 | /* Set MDI/MDIX mode */ |
| 654 | ret_val = e1e_rphy(hw, I82577_PHY_CTRL_2, &phy_data); |
| 655 | if (ret_val) |
| 656 | return ret_val; |
| 657 | phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK; |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 658 | /* Options: |
Bruce W Allan | e86fd89 | 2012-07-26 02:30:59 +0000 | [diff] [blame] | 659 | * 0 - Auto (default) |
| 660 | * 1 - MDI mode |
| 661 | * 2 - MDI-X mode |
| 662 | */ |
| 663 | switch (hw->phy.mdix) { |
| 664 | case 1: |
| 665 | break; |
| 666 | case 2: |
| 667 | phy_data |= I82577_PHY_CTRL2_MANUAL_MDIX; |
| 668 | break; |
| 669 | case 0: |
| 670 | default: |
| 671 | phy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX; |
| 672 | break; |
| 673 | } |
| 674 | ret_val = e1e_wphy(hw, I82577_PHY_CTRL_2, phy_data); |
| 675 | if (ret_val) |
| 676 | return ret_val; |
| 677 | |
Bruce Allan | 7b9f7e3 | 2012-03-20 03:47:41 +0000 | [diff] [blame] | 678 | return e1000_set_master_slave_mode(hw); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 679 | } |
| 680 | |
| 681 | /** |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 682 | * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link |
| 683 | * @hw: pointer to the HW structure |
| 684 | * |
| 685 | * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock |
| 686 | * and downshift values are set also. |
| 687 | **/ |
| 688 | s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw) |
| 689 | { |
| 690 | struct e1000_phy_info *phy = &hw->phy; |
| 691 | s32 ret_val; |
| 692 | u16 phy_data; |
| 693 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 694 | /* Enable CRS on Tx. This must be set for half-duplex operation. */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 695 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
| 696 | if (ret_val) |
| 697 | return ret_val; |
| 698 | |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 699 | /* For BM PHY this bit is downshift enable */ |
| 700 | if (phy->type != e1000_phy_bm) |
David Graham | 2d9498f | 2008-04-23 11:09:14 -0700 | [diff] [blame] | 701 | phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 702 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 703 | /* Options: |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 704 | * MDI/MDI-X = 0 (default) |
| 705 | * 0 - Auto for all speeds |
| 706 | * 1 - MDI mode |
| 707 | * 2 - MDI-X mode |
| 708 | * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) |
| 709 | */ |
| 710 | phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; |
| 711 | |
| 712 | switch (phy->mdix) { |
| 713 | case 1: |
| 714 | phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; |
| 715 | break; |
| 716 | case 2: |
| 717 | phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; |
| 718 | break; |
| 719 | case 3: |
| 720 | phy_data |= M88E1000_PSCR_AUTO_X_1000T; |
| 721 | break; |
| 722 | case 0: |
| 723 | default: |
| 724 | phy_data |= M88E1000_PSCR_AUTO_X_MODE; |
| 725 | break; |
| 726 | } |
| 727 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 728 | /* Options: |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 729 | * disable_polarity_correction = 0 (default) |
| 730 | * Automatic Correction for Reversed Cable Polarity |
| 731 | * 0 - Disabled |
| 732 | * 1 - Enabled |
| 733 | */ |
| 734 | phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; |
Bruce Allan | 04499ec | 2012-04-13 00:08:31 +0000 | [diff] [blame] | 735 | if (phy->disable_polarity_correction) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 736 | phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; |
| 737 | |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 738 | /* Enable downshift on BM (disabled by default) */ |
Matthew Vick | 885fe7b | 2012-04-25 07:25:18 +0000 | [diff] [blame] | 739 | if (phy->type == e1000_phy_bm) { |
| 740 | /* For 82574/82583, first disable then enable downshift */ |
| 741 | if (phy->id == BME1000_E_PHY_ID_R2) { |
| 742 | phy_data &= ~BME1000_PSCR_ENABLE_DOWNSHIFT; |
| 743 | ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, |
| 744 | phy_data); |
| 745 | if (ret_val) |
| 746 | return ret_val; |
| 747 | /* Commit the changes. */ |
Bruce Allan | 6b598e1 | 2013-01-23 06:50:05 +0000 | [diff] [blame] | 748 | ret_val = phy->ops.commit(hw); |
Matthew Vick | 885fe7b | 2012-04-25 07:25:18 +0000 | [diff] [blame] | 749 | if (ret_val) { |
| 750 | e_dbg("Error committing the PHY changes\n"); |
| 751 | return ret_val; |
| 752 | } |
| 753 | } |
| 754 | |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 755 | phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT; |
Matthew Vick | 885fe7b | 2012-04-25 07:25:18 +0000 | [diff] [blame] | 756 | } |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 757 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 758 | ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
| 759 | if (ret_val) |
| 760 | return ret_val; |
| 761 | |
Bruce Allan | 4662e82 | 2008-08-26 18:37:06 -0700 | [diff] [blame] | 762 | if ((phy->type == e1000_phy_m88) && |
| 763 | (phy->revision < E1000_REVISION_4) && |
| 764 | (phy->id != BME1000_E_PHY_ID_R2)) { |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 765 | /* Force TX_CLK in the Extended PHY Specific Control Register |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 766 | * to 25MHz clock. |
| 767 | */ |
| 768 | ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); |
| 769 | if (ret_val) |
| 770 | return ret_val; |
| 771 | |
| 772 | phy_data |= M88E1000_EPSCR_TX_CLK_25; |
| 773 | |
| 774 | if ((phy->revision == 2) && |
| 775 | (phy->id == M88E1111_I_PHY_ID)) { |
| 776 | /* 82573L PHY - set the downshift counter to 5x. */ |
| 777 | phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; |
| 778 | phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; |
| 779 | } else { |
| 780 | /* Configure Master and Slave downshift values */ |
| 781 | phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | |
| 782 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); |
| 783 | phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | |
| 784 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); |
| 785 | } |
| 786 | ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); |
| 787 | if (ret_val) |
| 788 | return ret_val; |
| 789 | } |
| 790 | |
Bruce Allan | 4662e82 | 2008-08-26 18:37:06 -0700 | [diff] [blame] | 791 | if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) { |
| 792 | /* Set PHY page 0, register 29 to 0x0003 */ |
| 793 | ret_val = e1e_wphy(hw, 29, 0x0003); |
| 794 | if (ret_val) |
| 795 | return ret_val; |
| 796 | |
| 797 | /* Set PHY page 0, register 30 to 0x0000 */ |
| 798 | ret_val = e1e_wphy(hw, 30, 0x0000); |
| 799 | if (ret_val) |
| 800 | return ret_val; |
| 801 | } |
| 802 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 803 | /* Commit the changes. */ |
Bruce Allan | 6b598e1 | 2013-01-23 06:50:05 +0000 | [diff] [blame] | 804 | if (phy->ops.commit) { |
| 805 | ret_val = phy->ops.commit(hw); |
| 806 | if (ret_val) { |
| 807 | e_dbg("Error committing the PHY changes\n"); |
| 808 | return ret_val; |
| 809 | } |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 810 | } |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 811 | |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 812 | if (phy->type == e1000_phy_82578) { |
Bruce Allan | 482fed8 | 2011-01-06 14:29:49 +0000 | [diff] [blame] | 813 | ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 814 | if (ret_val) |
| 815 | return ret_val; |
| 816 | |
| 817 | /* 82578 PHY - set the downshift count to 1x. */ |
| 818 | phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE; |
| 819 | phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK; |
Bruce Allan | 482fed8 | 2011-01-06 14:29:49 +0000 | [diff] [blame] | 820 | ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 821 | if (ret_val) |
| 822 | return ret_val; |
| 823 | } |
| 824 | |
| 825 | return 0; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 826 | } |
| 827 | |
| 828 | /** |
| 829 | * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link |
| 830 | * @hw: pointer to the HW structure |
| 831 | * |
| 832 | * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for |
| 833 | * igp PHY's. |
| 834 | **/ |
| 835 | s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw) |
| 836 | { |
| 837 | struct e1000_phy_info *phy = &hw->phy; |
| 838 | s32 ret_val; |
| 839 | u16 data; |
| 840 | |
| 841 | ret_val = e1000_phy_hw_reset(hw); |
| 842 | if (ret_val) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 843 | e_dbg("Error resetting the PHY.\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 844 | return ret_val; |
| 845 | } |
| 846 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 847 | /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid |
David Graham | 2d9498f | 2008-04-23 11:09:14 -0700 | [diff] [blame] | 848 | * timeout issues when LFS is enabled. |
| 849 | */ |
| 850 | msleep(100); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 851 | |
| 852 | /* disable lplu d0 during driver init */ |
Bruce Allan | 7de89f0 | 2013-01-05 08:06:03 +0000 | [diff] [blame] | 853 | if (hw->phy.ops.set_d0_lplu_state) { |
| 854 | ret_val = hw->phy.ops.set_d0_lplu_state(hw, false); |
| 855 | if (ret_val) { |
| 856 | e_dbg("Error Disabling LPLU D0\n"); |
| 857 | return ret_val; |
| 858 | } |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 859 | } |
| 860 | /* Configure mdi-mdix settings */ |
| 861 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data); |
| 862 | if (ret_val) |
| 863 | return ret_val; |
| 864 | |
| 865 | data &= ~IGP01E1000_PSCR_AUTO_MDIX; |
| 866 | |
| 867 | switch (phy->mdix) { |
| 868 | case 1: |
| 869 | data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; |
| 870 | break; |
| 871 | case 2: |
| 872 | data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; |
| 873 | break; |
| 874 | case 0: |
| 875 | default: |
| 876 | data |= IGP01E1000_PSCR_AUTO_MDIX; |
| 877 | break; |
| 878 | } |
| 879 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data); |
| 880 | if (ret_val) |
| 881 | return ret_val; |
| 882 | |
| 883 | /* set auto-master slave resolution settings */ |
| 884 | if (hw->mac.autoneg) { |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 885 | /* when autonegotiation advertisement is only 1000Mbps then we |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 886 | * should disable SmartSpeed and enable Auto MasterSlave |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 887 | * resolution as hardware default. |
| 888 | */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 889 | if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { |
| 890 | /* Disable SmartSpeed */ |
| 891 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 892 | &data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 893 | if (ret_val) |
| 894 | return ret_val; |
| 895 | |
| 896 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
| 897 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 898 | data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 899 | if (ret_val) |
| 900 | return ret_val; |
| 901 | |
| 902 | /* Set auto Master/Slave resolution process */ |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 903 | ret_val = e1e_rphy(hw, MII_CTRL1000, &data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 904 | if (ret_val) |
| 905 | return ret_val; |
| 906 | |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 907 | data &= ~CTL1000_ENABLE_MASTER; |
| 908 | ret_val = e1e_wphy(hw, MII_CTRL1000, data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 909 | if (ret_val) |
| 910 | return ret_val; |
| 911 | } |
| 912 | |
Bruce Allan | 7b9f7e3 | 2012-03-20 03:47:41 +0000 | [diff] [blame] | 913 | ret_val = e1000_set_master_slave_mode(hw); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 914 | } |
| 915 | |
| 916 | return ret_val; |
| 917 | } |
| 918 | |
| 919 | /** |
| 920 | * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation |
| 921 | * @hw: pointer to the HW structure |
| 922 | * |
| 923 | * Reads the MII auto-neg advertisement register and/or the 1000T control |
| 924 | * register and if the PHY is already setup for auto-negotiation, then |
| 925 | * return successful. Otherwise, setup advertisement and flow control to |
| 926 | * the appropriate values for the wanted auto-negotiation. |
| 927 | **/ |
| 928 | static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) |
| 929 | { |
| 930 | struct e1000_phy_info *phy = &hw->phy; |
| 931 | s32 ret_val; |
| 932 | u16 mii_autoneg_adv_reg; |
| 933 | u16 mii_1000t_ctrl_reg = 0; |
| 934 | |
| 935 | phy->autoneg_advertised &= phy->autoneg_mask; |
| 936 | |
| 937 | /* Read the MII Auto-Neg Advertisement Register (Address 4). */ |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 938 | ret_val = e1e_rphy(hw, MII_ADVERTISE, &mii_autoneg_adv_reg); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 939 | if (ret_val) |
| 940 | return ret_val; |
| 941 | |
| 942 | if (phy->autoneg_mask & ADVERTISE_1000_FULL) { |
| 943 | /* Read the MII 1000Base-T Control Register (Address 9). */ |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 944 | ret_val = e1e_rphy(hw, MII_CTRL1000, &mii_1000t_ctrl_reg); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 945 | if (ret_val) |
| 946 | return ret_val; |
| 947 | } |
| 948 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 949 | /* Need to parse both autoneg_advertised and fc and set up |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 950 | * the appropriate PHY registers. First we will parse for |
| 951 | * autoneg_advertised software override. Since we can advertise |
| 952 | * a plethora of combinations, we need to check each bit |
| 953 | * individually. |
| 954 | */ |
| 955 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 956 | /* First we clear all the 10/100 mb speed bits in the Auto-Neg |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 957 | * Advertisement Register (Address 4) and the 1000 mb speed bits in |
| 958 | * the 1000Base-T Control Register (Address 9). |
| 959 | */ |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 960 | mii_autoneg_adv_reg &= ~(ADVERTISE_100FULL | |
| 961 | ADVERTISE_100HALF | |
| 962 | ADVERTISE_10FULL | ADVERTISE_10HALF); |
| 963 | mii_1000t_ctrl_reg &= ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 964 | |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 965 | e_dbg("autoneg_advertised %x\n", phy->autoneg_advertised); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 966 | |
| 967 | /* Do we want to advertise 10 Mb Half Duplex? */ |
| 968 | if (phy->autoneg_advertised & ADVERTISE_10_HALF) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 969 | e_dbg("Advertise 10mb Half duplex\n"); |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 970 | mii_autoneg_adv_reg |= ADVERTISE_10HALF; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 971 | } |
| 972 | |
| 973 | /* Do we want to advertise 10 Mb Full Duplex? */ |
| 974 | if (phy->autoneg_advertised & ADVERTISE_10_FULL) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 975 | e_dbg("Advertise 10mb Full duplex\n"); |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 976 | mii_autoneg_adv_reg |= ADVERTISE_10FULL; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 977 | } |
| 978 | |
| 979 | /* Do we want to advertise 100 Mb Half Duplex? */ |
| 980 | if (phy->autoneg_advertised & ADVERTISE_100_HALF) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 981 | e_dbg("Advertise 100mb Half duplex\n"); |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 982 | mii_autoneg_adv_reg |= ADVERTISE_100HALF; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 983 | } |
| 984 | |
| 985 | /* Do we want to advertise 100 Mb Full Duplex? */ |
| 986 | if (phy->autoneg_advertised & ADVERTISE_100_FULL) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 987 | e_dbg("Advertise 100mb Full duplex\n"); |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 988 | mii_autoneg_adv_reg |= ADVERTISE_100FULL; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 989 | } |
| 990 | |
| 991 | /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ |
| 992 | if (phy->autoneg_advertised & ADVERTISE_1000_HALF) |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 993 | e_dbg("Advertise 1000mb Half duplex request denied!\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 994 | |
| 995 | /* Do we want to advertise 1000 Mb Full Duplex? */ |
| 996 | if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 997 | e_dbg("Advertise 1000mb Full duplex\n"); |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 998 | mii_1000t_ctrl_reg |= ADVERTISE_1000FULL; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 999 | } |
| 1000 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1001 | /* Check for a software override of the flow control settings, and |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1002 | * setup the PHY advertisement registers accordingly. If |
| 1003 | * auto-negotiation is enabled, then software will have to set the |
| 1004 | * "PAUSE" bits to the correct value in the Auto-Negotiation |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1005 | * Advertisement Register (MII_ADVERTISE) and re-start auto- |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1006 | * negotiation. |
| 1007 | * |
| 1008 | * The possible values of the "fc" parameter are: |
| 1009 | * 0: Flow control is completely disabled |
| 1010 | * 1: Rx flow control is enabled (we can receive pause frames |
Bruce Allan | 3d3a167 | 2012-02-23 03:13:18 +0000 | [diff] [blame] | 1011 | * but not send pause frames). |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1012 | * 2: Tx flow control is enabled (we can send pause frames |
Bruce Allan | 3d3a167 | 2012-02-23 03:13:18 +0000 | [diff] [blame] | 1013 | * but we do not support receiving pause frames). |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1014 | * 3: Both Rx and Tx flow control (symmetric) are enabled. |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1015 | * other: No software override. The flow control configuration |
Bruce Allan | 3d3a167 | 2012-02-23 03:13:18 +0000 | [diff] [blame] | 1016 | * in the EEPROM is used. |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1017 | */ |
Bruce Allan | 5c48ef3e2 | 2008-11-21 16:57:36 -0800 | [diff] [blame] | 1018 | switch (hw->fc.current_mode) { |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1019 | case e1000_fc_none: |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1020 | /* Flow control (Rx & Tx) is completely disabled by a |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1021 | * software over-ride. |
| 1022 | */ |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1023 | mii_autoneg_adv_reg &= |
| 1024 | ~(ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1025 | break; |
| 1026 | case e1000_fc_rx_pause: |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1027 | /* Rx Flow control is enabled, and Tx Flow control is |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1028 | * disabled, by a software over-ride. |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1029 | * |
| 1030 | * Since there really isn't a way to advertise that we are |
| 1031 | * capable of Rx Pause ONLY, we will advertise that we |
| 1032 | * support both symmetric and asymmetric Rx PAUSE. Later |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1033 | * (in e1000e_config_fc_after_link_up) we will disable the |
| 1034 | * hw's ability to send PAUSE frames. |
| 1035 | */ |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1036 | mii_autoneg_adv_reg |= |
| 1037 | (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1038 | break; |
| 1039 | case e1000_fc_tx_pause: |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1040 | /* Tx Flow control is enabled, and Rx Flow control is |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1041 | * disabled, by a software over-ride. |
| 1042 | */ |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1043 | mii_autoneg_adv_reg |= ADVERTISE_PAUSE_ASYM; |
| 1044 | mii_autoneg_adv_reg &= ~ADVERTISE_PAUSE_CAP; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1045 | break; |
| 1046 | case e1000_fc_full: |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1047 | /* Flow control (both Rx and Tx) is enabled by a software |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1048 | * over-ride. |
| 1049 | */ |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1050 | mii_autoneg_adv_reg |= |
| 1051 | (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1052 | break; |
| 1053 | default: |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1054 | e_dbg("Flow control param set incorrectly\n"); |
Bruce Allan | 7eb61d8 | 2012-02-08 02:55:03 +0000 | [diff] [blame] | 1055 | return -E1000_ERR_CONFIG; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1056 | } |
| 1057 | |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1058 | ret_val = e1e_wphy(hw, MII_ADVERTISE, mii_autoneg_adv_reg); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1059 | if (ret_val) |
| 1060 | return ret_val; |
| 1061 | |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1062 | e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1063 | |
Bruce Allan | b1cdfea | 2010-12-11 05:53:47 +0000 | [diff] [blame] | 1064 | if (phy->autoneg_mask & ADVERTISE_1000_FULL) |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1065 | ret_val = e1e_wphy(hw, MII_CTRL1000, mii_1000t_ctrl_reg); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1066 | |
| 1067 | return ret_val; |
| 1068 | } |
| 1069 | |
| 1070 | /** |
| 1071 | * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link |
| 1072 | * @hw: pointer to the HW structure |
| 1073 | * |
| 1074 | * Performs initial bounds checking on autoneg advertisement parameter, then |
| 1075 | * configure to advertise the full capability. Setup the PHY to autoneg |
| 1076 | * and restart the negotiation process between the link partner. If |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1077 | * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1078 | **/ |
| 1079 | static s32 e1000_copper_link_autoneg(struct e1000_hw *hw) |
| 1080 | { |
| 1081 | struct e1000_phy_info *phy = &hw->phy; |
| 1082 | s32 ret_val; |
| 1083 | u16 phy_ctrl; |
| 1084 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1085 | /* Perform some bounds checking on the autoneg advertisement |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1086 | * parameter. |
| 1087 | */ |
| 1088 | phy->autoneg_advertised &= phy->autoneg_mask; |
| 1089 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1090 | /* If autoneg_advertised is zero, we assume it was not defaulted |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1091 | * by the calling code so we set to advertise full capability. |
| 1092 | */ |
Bruce Allan | 04499ec | 2012-04-13 00:08:31 +0000 | [diff] [blame] | 1093 | if (!phy->autoneg_advertised) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1094 | phy->autoneg_advertised = phy->autoneg_mask; |
| 1095 | |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1096 | e_dbg("Reconfiguring auto-neg advertisement params\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1097 | ret_val = e1000_phy_setup_autoneg(hw); |
| 1098 | if (ret_val) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1099 | e_dbg("Error Setting up Auto-Negotiation\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1100 | return ret_val; |
| 1101 | } |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1102 | e_dbg("Restarting Auto-Neg\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1103 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1104 | /* Restart auto-negotiation by setting the Auto Neg Enable bit and |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1105 | * the Auto Neg Restart bit in the PHY control register. |
| 1106 | */ |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1107 | ret_val = e1e_rphy(hw, MII_BMCR, &phy_ctrl); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1108 | if (ret_val) |
| 1109 | return ret_val; |
| 1110 | |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1111 | phy_ctrl |= (BMCR_ANENABLE | BMCR_ANRESTART); |
| 1112 | ret_val = e1e_wphy(hw, MII_BMCR, phy_ctrl); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1113 | if (ret_val) |
| 1114 | return ret_val; |
| 1115 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1116 | /* Does the user want to wait for Auto-Neg to complete here, or |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1117 | * check at a later time (for example, callback routine). |
| 1118 | */ |
Jeff Kirsher | 318a94d | 2008-03-28 09:15:16 -0700 | [diff] [blame] | 1119 | if (phy->autoneg_wait_to_complete) { |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1120 | ret_val = e1000_wait_autoneg(hw); |
| 1121 | if (ret_val) { |
Bruce Allan | 434f139 | 2011-12-16 00:46:54 +0000 | [diff] [blame] | 1122 | e_dbg("Error while waiting for autoneg to complete\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1123 | return ret_val; |
| 1124 | } |
| 1125 | } |
| 1126 | |
Bruce Allan | f92518d | 2012-02-01 11:16:42 +0000 | [diff] [blame] | 1127 | hw->mac.get_link_status = true; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1128 | |
| 1129 | return ret_val; |
| 1130 | } |
| 1131 | |
| 1132 | /** |
| 1133 | * e1000e_setup_copper_link - Configure copper link settings |
| 1134 | * @hw: pointer to the HW structure |
| 1135 | * |
| 1136 | * Calls the appropriate function to configure the link for auto-neg or forced |
| 1137 | * speed and duplex. Then we check for link, once link is established calls |
| 1138 | * to configure collision distance and flow control are called. If link is |
| 1139 | * not established, we return -E1000_ERR_PHY (-2). |
| 1140 | **/ |
| 1141 | s32 e1000e_setup_copper_link(struct e1000_hw *hw) |
| 1142 | { |
| 1143 | s32 ret_val; |
| 1144 | bool link; |
| 1145 | |
| 1146 | if (hw->mac.autoneg) { |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1147 | /* Setup autoneg and flow control advertisement and perform |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1148 | * autonegotiation. |
| 1149 | */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1150 | ret_val = e1000_copper_link_autoneg(hw); |
| 1151 | if (ret_val) |
| 1152 | return ret_val; |
| 1153 | } else { |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1154 | /* PHY will be set to 10H, 10F, 100H or 100F |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1155 | * depending on user settings. |
| 1156 | */ |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1157 | e_dbg("Forcing Speed and Duplex\n"); |
Bruce Allan | c2c6629 | 2013-01-05 08:06:08 +0000 | [diff] [blame] | 1158 | ret_val = hw->phy.ops.force_speed_duplex(hw); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1159 | if (ret_val) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1160 | e_dbg("Error Forcing Speed and Duplex\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1161 | return ret_val; |
| 1162 | } |
| 1163 | } |
| 1164 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1165 | /* Check link status. Wait up to 100 microseconds for link to become |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1166 | * valid. |
| 1167 | */ |
Bruce Allan | 3d3a167 | 2012-02-23 03:13:18 +0000 | [diff] [blame] | 1168 | ret_val = e1000e_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10, |
| 1169 | &link); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1170 | if (ret_val) |
| 1171 | return ret_val; |
| 1172 | |
| 1173 | if (link) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1174 | e_dbg("Valid link established!!!\n"); |
Bruce Allan | 57cde76 | 2012-02-22 09:02:58 +0000 | [diff] [blame] | 1175 | hw->mac.ops.config_collision_dist(hw); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1176 | ret_val = e1000e_config_fc_after_link_up(hw); |
| 1177 | } else { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1178 | e_dbg("Unable to establish link!!!\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1179 | } |
| 1180 | |
| 1181 | return ret_val; |
| 1182 | } |
| 1183 | |
| 1184 | /** |
| 1185 | * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY |
| 1186 | * @hw: pointer to the HW structure |
| 1187 | * |
| 1188 | * Calls the PHY setup function to force speed and duplex. Clears the |
| 1189 | * auto-crossover to force MDI manually. Waits for link and returns |
| 1190 | * successful if link up is successful, else -E1000_ERR_PHY (-2). |
| 1191 | **/ |
| 1192 | s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw) |
| 1193 | { |
| 1194 | struct e1000_phy_info *phy = &hw->phy; |
| 1195 | s32 ret_val; |
| 1196 | u16 phy_data; |
| 1197 | bool link; |
| 1198 | |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1199 | ret_val = e1e_rphy(hw, MII_BMCR, &phy_data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1200 | if (ret_val) |
| 1201 | return ret_val; |
| 1202 | |
| 1203 | e1000e_phy_force_speed_duplex_setup(hw, &phy_data); |
| 1204 | |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1205 | ret_val = e1e_wphy(hw, MII_BMCR, phy_data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1206 | if (ret_val) |
| 1207 | return ret_val; |
| 1208 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1209 | /* Clear Auto-Crossover to force MDI manually. IGP requires MDI |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1210 | * forced whenever speed and duplex are forced. |
| 1211 | */ |
| 1212 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); |
| 1213 | if (ret_val) |
| 1214 | return ret_val; |
| 1215 | |
| 1216 | phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; |
| 1217 | phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; |
| 1218 | |
| 1219 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); |
| 1220 | if (ret_val) |
| 1221 | return ret_val; |
| 1222 | |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1223 | e_dbg("IGP PSCR: %X\n", phy_data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1224 | |
| 1225 | udelay(1); |
| 1226 | |
Jeff Kirsher | 318a94d | 2008-03-28 09:15:16 -0700 | [diff] [blame] | 1227 | if (phy->autoneg_wait_to_complete) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1228 | e_dbg("Waiting for forced speed/duplex link on IGP phy.\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1229 | |
Bruce Allan | 3d3a167 | 2012-02-23 03:13:18 +0000 | [diff] [blame] | 1230 | ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, |
| 1231 | 100000, &link); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1232 | if (ret_val) |
| 1233 | return ret_val; |
| 1234 | |
| 1235 | if (!link) |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1236 | e_dbg("Link taking longer than expected.\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1237 | |
| 1238 | /* Try once more */ |
Bruce Allan | 3d3a167 | 2012-02-23 03:13:18 +0000 | [diff] [blame] | 1239 | ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, |
| 1240 | 100000, &link); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1241 | } |
| 1242 | |
| 1243 | return ret_val; |
| 1244 | } |
| 1245 | |
| 1246 | /** |
| 1247 | * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY |
| 1248 | * @hw: pointer to the HW structure |
| 1249 | * |
| 1250 | * Calls the PHY setup function to force speed and duplex. Clears the |
| 1251 | * auto-crossover to force MDI manually. Resets the PHY to commit the |
| 1252 | * changes. If time expires while waiting for link up, we reset the DSP. |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1253 | * After reset, TX_CLK and CRS on Tx must be set. Return successful upon |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1254 | * successful completion, else return corresponding error code. |
| 1255 | **/ |
| 1256 | s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw) |
| 1257 | { |
| 1258 | struct e1000_phy_info *phy = &hw->phy; |
| 1259 | s32 ret_val; |
| 1260 | u16 phy_data; |
| 1261 | bool link; |
| 1262 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1263 | /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1264 | * forced whenever speed and duplex are forced. |
| 1265 | */ |
| 1266 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
| 1267 | if (ret_val) |
| 1268 | return ret_val; |
| 1269 | |
| 1270 | phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; |
| 1271 | ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
| 1272 | if (ret_val) |
| 1273 | return ret_val; |
| 1274 | |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1275 | e_dbg("M88E1000 PSCR: %X\n", phy_data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1276 | |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1277 | ret_val = e1e_rphy(hw, MII_BMCR, &phy_data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1278 | if (ret_val) |
| 1279 | return ret_val; |
| 1280 | |
| 1281 | e1000e_phy_force_speed_duplex_setup(hw, &phy_data); |
| 1282 | |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1283 | ret_val = e1e_wphy(hw, MII_BMCR, phy_data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1284 | if (ret_val) |
| 1285 | return ret_val; |
| 1286 | |
Bruce Allan | 5aa49c8 | 2008-11-21 16:49:53 -0800 | [diff] [blame] | 1287 | /* Reset the phy to commit changes. */ |
Bruce Allan | 6b598e1 | 2013-01-23 06:50:05 +0000 | [diff] [blame] | 1288 | if (hw->phy.ops.commit) { |
| 1289 | ret_val = hw->phy.ops.commit(hw); |
| 1290 | if (ret_val) |
| 1291 | return ret_val; |
| 1292 | } |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1293 | |
Jeff Kirsher | 318a94d | 2008-03-28 09:15:16 -0700 | [diff] [blame] | 1294 | if (phy->autoneg_wait_to_complete) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1295 | e_dbg("Waiting for forced speed/duplex link on M88 phy.\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1296 | |
| 1297 | ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, |
Bruce Allan | 17e813e | 2013-02-20 04:06:01 +0000 | [diff] [blame] | 1298 | 100000, &link); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1299 | if (ret_val) |
| 1300 | return ret_val; |
| 1301 | |
| 1302 | if (!link) { |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 1303 | if (hw->phy.type != e1000_phy_m88) { |
| 1304 | e_dbg("Link taking longer than expected.\n"); |
| 1305 | } else { |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1306 | /* We didn't get link. |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 1307 | * Reset the DSP and cross our fingers. |
| 1308 | */ |
Bruce Allan | 482fed8 | 2011-01-06 14:29:49 +0000 | [diff] [blame] | 1309 | ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT, |
| 1310 | 0x001d); |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 1311 | if (ret_val) |
| 1312 | return ret_val; |
| 1313 | ret_val = e1000e_phy_reset_dsp(hw); |
| 1314 | if (ret_val) |
| 1315 | return ret_val; |
| 1316 | } |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1317 | } |
| 1318 | |
| 1319 | /* Try once more */ |
| 1320 | ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, |
Bruce Allan | 17e813e | 2013-02-20 04:06:01 +0000 | [diff] [blame] | 1321 | 100000, &link); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1322 | if (ret_val) |
| 1323 | return ret_val; |
| 1324 | } |
| 1325 | |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 1326 | if (hw->phy.type != e1000_phy_m88) |
| 1327 | return 0; |
| 1328 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1329 | ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); |
| 1330 | if (ret_val) |
| 1331 | return ret_val; |
| 1332 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1333 | /* Resetting the phy means we need to re-force TX_CLK in the |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1334 | * Extended PHY Specific Control Register to 25MHz clock from |
| 1335 | * the reset value of 2.5MHz. |
| 1336 | */ |
| 1337 | phy_data |= M88E1000_EPSCR_TX_CLK_25; |
| 1338 | ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); |
| 1339 | if (ret_val) |
| 1340 | return ret_val; |
| 1341 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1342 | /* In addition, we must re-enable CRS on Tx for both half and full |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1343 | * duplex. |
| 1344 | */ |
| 1345 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
| 1346 | if (ret_val) |
| 1347 | return ret_val; |
| 1348 | |
| 1349 | phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; |
| 1350 | ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
| 1351 | |
| 1352 | return ret_val; |
| 1353 | } |
| 1354 | |
| 1355 | /** |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 1356 | * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex |
| 1357 | * @hw: pointer to the HW structure |
| 1358 | * |
| 1359 | * Forces the speed and duplex settings of the PHY. |
| 1360 | * This is a function pointer entry point only called by |
| 1361 | * PHY setup routines. |
| 1362 | **/ |
| 1363 | s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw) |
| 1364 | { |
| 1365 | struct e1000_phy_info *phy = &hw->phy; |
| 1366 | s32 ret_val; |
| 1367 | u16 data; |
| 1368 | bool link; |
| 1369 | |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1370 | ret_val = e1e_rphy(hw, MII_BMCR, &data); |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 1371 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1372 | return ret_val; |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 1373 | |
| 1374 | e1000e_phy_force_speed_duplex_setup(hw, &data); |
| 1375 | |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1376 | ret_val = e1e_wphy(hw, MII_BMCR, data); |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 1377 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1378 | return ret_val; |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 1379 | |
| 1380 | /* Disable MDI-X support for 10/100 */ |
| 1381 | ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data); |
| 1382 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1383 | return ret_val; |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 1384 | |
| 1385 | data &= ~IFE_PMC_AUTO_MDIX; |
| 1386 | data &= ~IFE_PMC_FORCE_MDIX; |
| 1387 | |
| 1388 | ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data); |
| 1389 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1390 | return ret_val; |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 1391 | |
| 1392 | e_dbg("IFE PMC: %X\n", data); |
| 1393 | |
| 1394 | udelay(1); |
| 1395 | |
| 1396 | if (phy->autoneg_wait_to_complete) { |
| 1397 | e_dbg("Waiting for forced speed/duplex link on IFE phy.\n"); |
| 1398 | |
Bruce Allan | 3d3a167 | 2012-02-23 03:13:18 +0000 | [diff] [blame] | 1399 | ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, |
| 1400 | 100000, &link); |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 1401 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1402 | return ret_val; |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 1403 | |
| 1404 | if (!link) |
| 1405 | e_dbg("Link taking longer than expected.\n"); |
| 1406 | |
| 1407 | /* Try once more */ |
Bruce Allan | 3d3a167 | 2012-02-23 03:13:18 +0000 | [diff] [blame] | 1408 | ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, |
| 1409 | 100000, &link); |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 1410 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1411 | return ret_val; |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 1412 | } |
| 1413 | |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1414 | return 0; |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 1415 | } |
| 1416 | |
| 1417 | /** |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1418 | * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex |
| 1419 | * @hw: pointer to the HW structure |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1420 | * @phy_ctrl: pointer to current value of MII_BMCR |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1421 | * |
| 1422 | * Forces speed and duplex on the PHY by doing the following: disable flow |
| 1423 | * control, force speed/duplex on the MAC, disable auto speed detection, |
| 1424 | * disable auto-negotiation, configure duplex, configure speed, configure |
| 1425 | * the collision distance, write configuration to CTRL register. The |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1426 | * caller must write to the MII_BMCR register for these settings to |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1427 | * take affect. |
| 1428 | **/ |
| 1429 | void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl) |
| 1430 | { |
| 1431 | struct e1000_mac_info *mac = &hw->mac; |
| 1432 | u32 ctrl; |
| 1433 | |
| 1434 | /* Turn off flow control when forcing speed/duplex */ |
Bruce Allan | 5c48ef3e2 | 2008-11-21 16:57:36 -0800 | [diff] [blame] | 1435 | hw->fc.current_mode = e1000_fc_none; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1436 | |
| 1437 | /* Force speed/duplex on the mac */ |
| 1438 | ctrl = er32(CTRL); |
| 1439 | ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); |
| 1440 | ctrl &= ~E1000_CTRL_SPD_SEL; |
| 1441 | |
| 1442 | /* Disable Auto Speed Detection */ |
| 1443 | ctrl &= ~E1000_CTRL_ASDE; |
| 1444 | |
| 1445 | /* Disable autoneg on the phy */ |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1446 | *phy_ctrl &= ~BMCR_ANENABLE; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1447 | |
| 1448 | /* Forcing Full or Half Duplex? */ |
| 1449 | if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { |
| 1450 | ctrl &= ~E1000_CTRL_FD; |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1451 | *phy_ctrl &= ~BMCR_FULLDPLX; |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1452 | e_dbg("Half Duplex\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1453 | } else { |
| 1454 | ctrl |= E1000_CTRL_FD; |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1455 | *phy_ctrl |= BMCR_FULLDPLX; |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1456 | e_dbg("Full Duplex\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1457 | } |
| 1458 | |
| 1459 | /* Forcing 10mb or 100mb? */ |
| 1460 | if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) { |
| 1461 | ctrl |= E1000_CTRL_SPD_100; |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1462 | *phy_ctrl |= BMCR_SPEED100; |
| 1463 | *phy_ctrl &= ~BMCR_SPEED1000; |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1464 | e_dbg("Forcing 100mb\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1465 | } else { |
| 1466 | ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1467 | *phy_ctrl &= ~(BMCR_SPEED1000 | BMCR_SPEED100); |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1468 | e_dbg("Forcing 10mb\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1469 | } |
| 1470 | |
Bruce Allan | 57cde76 | 2012-02-22 09:02:58 +0000 | [diff] [blame] | 1471 | hw->mac.ops.config_collision_dist(hw); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1472 | |
| 1473 | ew32(CTRL, ctrl); |
| 1474 | } |
| 1475 | |
| 1476 | /** |
| 1477 | * e1000e_set_d3_lplu_state - Sets low power link up state for D3 |
| 1478 | * @hw: pointer to the HW structure |
| 1479 | * @active: boolean used to enable/disable lplu |
| 1480 | * |
| 1481 | * Success returns 0, Failure returns 1 |
| 1482 | * |
| 1483 | * The low power link up (lplu) state is set to the power management level D3 |
| 1484 | * and SmartSpeed is disabled when active is true, else clear lplu for D3 |
| 1485 | * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU |
| 1486 | * is used during Dx states where the power conservation is most important. |
| 1487 | * During driver activity, SmartSpeed should be enabled so performance is |
| 1488 | * maintained. |
| 1489 | **/ |
| 1490 | s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active) |
| 1491 | { |
| 1492 | struct e1000_phy_info *phy = &hw->phy; |
| 1493 | s32 ret_val; |
| 1494 | u16 data; |
| 1495 | |
| 1496 | ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data); |
| 1497 | if (ret_val) |
| 1498 | return ret_val; |
| 1499 | |
| 1500 | if (!active) { |
| 1501 | data &= ~IGP02E1000_PM_D3_LPLU; |
David Graham | 2d9498f | 2008-04-23 11:09:14 -0700 | [diff] [blame] | 1502 | ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1503 | if (ret_val) |
| 1504 | return ret_val; |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1505 | /* LPLU and SmartSpeed are mutually exclusive. LPLU is used |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1506 | * during Dx states where the power conservation is most |
| 1507 | * important. During driver activity we should enable |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1508 | * SmartSpeed, so performance is maintained. |
| 1509 | */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1510 | if (phy->smart_speed == e1000_smart_speed_on) { |
| 1511 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1512 | &data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1513 | if (ret_val) |
| 1514 | return ret_val; |
| 1515 | |
| 1516 | data |= IGP01E1000_PSCFR_SMART_SPEED; |
| 1517 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1518 | data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1519 | if (ret_val) |
| 1520 | return ret_val; |
| 1521 | } else if (phy->smart_speed == e1000_smart_speed_off) { |
| 1522 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1523 | &data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1524 | if (ret_val) |
| 1525 | return ret_val; |
| 1526 | |
| 1527 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
| 1528 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1529 | data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1530 | if (ret_val) |
| 1531 | return ret_val; |
| 1532 | } |
| 1533 | } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || |
| 1534 | (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || |
| 1535 | (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { |
| 1536 | data |= IGP02E1000_PM_D3_LPLU; |
| 1537 | ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); |
| 1538 | if (ret_val) |
| 1539 | return ret_val; |
| 1540 | |
| 1541 | /* When LPLU is enabled, we should disable SmartSpeed */ |
| 1542 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); |
| 1543 | if (ret_val) |
| 1544 | return ret_val; |
| 1545 | |
| 1546 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
| 1547 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); |
| 1548 | } |
| 1549 | |
| 1550 | return ret_val; |
| 1551 | } |
| 1552 | |
| 1553 | /** |
Auke Kok | 489815c | 2008-02-21 15:11:07 -0800 | [diff] [blame] | 1554 | * e1000e_check_downshift - Checks whether a downshift in speed occurred |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1555 | * @hw: pointer to the HW structure |
| 1556 | * |
| 1557 | * Success returns 0, Failure returns 1 |
| 1558 | * |
| 1559 | * A downshift is detected by querying the PHY link health. |
| 1560 | **/ |
| 1561 | s32 e1000e_check_downshift(struct e1000_hw *hw) |
| 1562 | { |
| 1563 | struct e1000_phy_info *phy = &hw->phy; |
| 1564 | s32 ret_val; |
| 1565 | u16 phy_data, offset, mask; |
| 1566 | |
| 1567 | switch (phy->type) { |
| 1568 | case e1000_phy_m88: |
| 1569 | case e1000_phy_gg82563: |
Bruce Allan | 07f025e | 2009-12-01 15:53:48 +0000 | [diff] [blame] | 1570 | case e1000_phy_bm: |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 1571 | case e1000_phy_82578: |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1572 | offset = M88E1000_PHY_SPEC_STATUS; |
| 1573 | mask = M88E1000_PSSR_DOWNSHIFT; |
| 1574 | break; |
| 1575 | case e1000_phy_igp_2: |
| 1576 | case e1000_phy_igp_3: |
| 1577 | offset = IGP01E1000_PHY_LINK_HEALTH; |
| 1578 | mask = IGP01E1000_PLHR_SS_DOWNGRADE; |
| 1579 | break; |
| 1580 | default: |
| 1581 | /* speed downshift not supported */ |
Bruce Allan | 564ea9b | 2009-11-20 23:26:44 +0000 | [diff] [blame] | 1582 | phy->speed_downgraded = false; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1583 | return 0; |
| 1584 | } |
| 1585 | |
| 1586 | ret_val = e1e_rphy(hw, offset, &phy_data); |
| 1587 | |
| 1588 | if (!ret_val) |
Bruce Allan | 04499ec | 2012-04-13 00:08:31 +0000 | [diff] [blame] | 1589 | phy->speed_downgraded = !!(phy_data & mask); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1590 | |
| 1591 | return ret_val; |
| 1592 | } |
| 1593 | |
| 1594 | /** |
| 1595 | * e1000_check_polarity_m88 - Checks the polarity. |
| 1596 | * @hw: pointer to the HW structure |
| 1597 | * |
| 1598 | * Success returns 0, Failure returns -E1000_ERR_PHY (-2) |
| 1599 | * |
| 1600 | * Polarity is determined based on the PHY specific status register. |
| 1601 | **/ |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 1602 | s32 e1000_check_polarity_m88(struct e1000_hw *hw) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1603 | { |
| 1604 | struct e1000_phy_info *phy = &hw->phy; |
| 1605 | s32 ret_val; |
| 1606 | u16 data; |
| 1607 | |
| 1608 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data); |
| 1609 | |
| 1610 | if (!ret_val) |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 1611 | phy->cable_polarity = ((data & M88E1000_PSSR_REV_POLARITY) |
| 1612 | ? e1000_rev_polarity_reversed |
| 1613 | : e1000_rev_polarity_normal); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1614 | |
| 1615 | return ret_val; |
| 1616 | } |
| 1617 | |
| 1618 | /** |
| 1619 | * e1000_check_polarity_igp - Checks the polarity. |
| 1620 | * @hw: pointer to the HW structure |
| 1621 | * |
| 1622 | * Success returns 0, Failure returns -E1000_ERR_PHY (-2) |
| 1623 | * |
| 1624 | * Polarity is determined based on the PHY port status register, and the |
| 1625 | * current speed (since there is no polarity at 100Mbps). |
| 1626 | **/ |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 1627 | s32 e1000_check_polarity_igp(struct e1000_hw *hw) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1628 | { |
| 1629 | struct e1000_phy_info *phy = &hw->phy; |
| 1630 | s32 ret_val; |
| 1631 | u16 data, offset, mask; |
| 1632 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1633 | /* Polarity is determined based on the speed of |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1634 | * our connection. |
| 1635 | */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1636 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data); |
| 1637 | if (ret_val) |
| 1638 | return ret_val; |
| 1639 | |
| 1640 | if ((data & IGP01E1000_PSSR_SPEED_MASK) == |
| 1641 | IGP01E1000_PSSR_SPEED_1000MBPS) { |
| 1642 | offset = IGP01E1000_PHY_PCS_INIT_REG; |
| 1643 | mask = IGP01E1000_PHY_POLARITY_MASK; |
| 1644 | } else { |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1645 | /* This really only applies to 10Mbps since |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1646 | * there is no polarity for 100Mbps (always 0). |
| 1647 | */ |
| 1648 | offset = IGP01E1000_PHY_PORT_STATUS; |
| 1649 | mask = IGP01E1000_PSSR_POLARITY_REVERSED; |
| 1650 | } |
| 1651 | |
| 1652 | ret_val = e1e_rphy(hw, offset, &data); |
| 1653 | |
| 1654 | if (!ret_val) |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 1655 | phy->cable_polarity = ((data & mask) |
| 1656 | ? e1000_rev_polarity_reversed |
| 1657 | : e1000_rev_polarity_normal); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1658 | |
| 1659 | return ret_val; |
| 1660 | } |
| 1661 | |
| 1662 | /** |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 1663 | * e1000_check_polarity_ife - Check cable polarity for IFE PHY |
| 1664 | * @hw: pointer to the HW structure |
| 1665 | * |
| 1666 | * Polarity is determined on the polarity reversal feature being enabled. |
| 1667 | **/ |
| 1668 | s32 e1000_check_polarity_ife(struct e1000_hw *hw) |
| 1669 | { |
| 1670 | struct e1000_phy_info *phy = &hw->phy; |
| 1671 | s32 ret_val; |
| 1672 | u16 phy_data, offset, mask; |
| 1673 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1674 | /* Polarity is determined based on the reversal feature being enabled. |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 1675 | */ |
| 1676 | if (phy->polarity_correction) { |
| 1677 | offset = IFE_PHY_EXTENDED_STATUS_CONTROL; |
| 1678 | mask = IFE_PESC_POLARITY_REVERSED; |
| 1679 | } else { |
| 1680 | offset = IFE_PHY_SPECIAL_CONTROL; |
| 1681 | mask = IFE_PSC_FORCE_POLARITY; |
| 1682 | } |
| 1683 | |
| 1684 | ret_val = e1e_rphy(hw, offset, &phy_data); |
| 1685 | |
| 1686 | if (!ret_val) |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 1687 | phy->cable_polarity = ((phy_data & mask) |
| 1688 | ? e1000_rev_polarity_reversed |
| 1689 | : e1000_rev_polarity_normal); |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 1690 | |
| 1691 | return ret_val; |
| 1692 | } |
| 1693 | |
| 1694 | /** |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1695 | * e1000_wait_autoneg - Wait for auto-neg completion |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1696 | * @hw: pointer to the HW structure |
| 1697 | * |
| 1698 | * Waits for auto-negotiation to complete or for the auto-negotiation time |
| 1699 | * limit to expire, which ever happens first. |
| 1700 | **/ |
| 1701 | static s32 e1000_wait_autoneg(struct e1000_hw *hw) |
| 1702 | { |
| 1703 | s32 ret_val = 0; |
| 1704 | u16 i, phy_status; |
| 1705 | |
| 1706 | /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ |
| 1707 | for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1708 | ret_val = e1e_rphy(hw, MII_BMSR, &phy_status); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1709 | if (ret_val) |
| 1710 | break; |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1711 | ret_val = e1e_rphy(hw, MII_BMSR, &phy_status); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1712 | if (ret_val) |
| 1713 | break; |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1714 | if (phy_status & BMSR_ANEGCOMPLETE) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1715 | break; |
| 1716 | msleep(100); |
| 1717 | } |
| 1718 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1719 | /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1720 | * has completed. |
| 1721 | */ |
| 1722 | return ret_val; |
| 1723 | } |
| 1724 | |
| 1725 | /** |
| 1726 | * e1000e_phy_has_link_generic - Polls PHY for link |
| 1727 | * @hw: pointer to the HW structure |
| 1728 | * @iterations: number of times to poll for link |
| 1729 | * @usec_interval: delay between polling attempts |
| 1730 | * @success: pointer to whether polling was successful or not |
| 1731 | * |
| 1732 | * Polls the PHY status register for link, 'iterations' number of times. |
| 1733 | **/ |
| 1734 | s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, |
Bruce Allan | 17e813e | 2013-02-20 04:06:01 +0000 | [diff] [blame] | 1735 | u32 usec_interval, bool *success) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1736 | { |
| 1737 | s32 ret_val = 0; |
| 1738 | u16 i, phy_status; |
| 1739 | |
| 1740 | for (i = 0; i < iterations; i++) { |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1741 | /* Some PHYs require the MII_BMSR register to be read |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1742 | * twice due to the link bit being sticky. No harm doing |
| 1743 | * it across the board. |
| 1744 | */ |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1745 | ret_val = e1e_rphy(hw, MII_BMSR, &phy_status); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1746 | if (ret_val) |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1747 | /* If the first read fails, another entity may have |
Bruce Allan | 906e8d9 | 2009-07-01 13:28:50 +0000 | [diff] [blame] | 1748 | * ownership of the resources, wait and try again to |
| 1749 | * see if they have relinquished the resources yet. |
| 1750 | */ |
| 1751 | udelay(usec_interval); |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1752 | ret_val = e1e_rphy(hw, MII_BMSR, &phy_status); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1753 | if (ret_val) |
| 1754 | break; |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1755 | if (phy_status & BMSR_LSTATUS) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1756 | break; |
| 1757 | if (usec_interval >= 1000) |
Bruce Allan | 362e20c | 2013-02-20 04:05:45 +0000 | [diff] [blame] | 1758 | mdelay(usec_interval / 1000); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1759 | else |
| 1760 | udelay(usec_interval); |
| 1761 | } |
| 1762 | |
| 1763 | *success = (i < iterations); |
| 1764 | |
| 1765 | return ret_val; |
| 1766 | } |
| 1767 | |
| 1768 | /** |
| 1769 | * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY |
| 1770 | * @hw: pointer to the HW structure |
| 1771 | * |
| 1772 | * Reads the PHY specific status register to retrieve the cable length |
| 1773 | * information. The cable length is determined by averaging the minimum and |
| 1774 | * maximum values to get the "average" cable length. The m88 PHY has four |
| 1775 | * possible cable length values, which are: |
| 1776 | * Register Value Cable Length |
| 1777 | * 0 < 50 meters |
| 1778 | * 1 50 - 80 meters |
| 1779 | * 2 80 - 110 meters |
| 1780 | * 3 110 - 140 meters |
| 1781 | * 4 > 140 meters |
| 1782 | **/ |
| 1783 | s32 e1000e_get_cable_length_m88(struct e1000_hw *hw) |
| 1784 | { |
| 1785 | struct e1000_phy_info *phy = &hw->phy; |
| 1786 | s32 ret_val; |
| 1787 | u16 phy_data, index; |
| 1788 | |
| 1789 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); |
| 1790 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1791 | return ret_val; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1792 | |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 1793 | index = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >> |
| 1794 | M88E1000_PSSR_CABLE_LENGTH_SHIFT); |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1795 | |
| 1796 | if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) |
| 1797 | return -E1000_ERR_PHY; |
Bruce Allan | eb656d4 | 2009-12-01 15:47:02 +0000 | [diff] [blame] | 1798 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1799 | phy->min_cable_length = e1000_m88_cable_length_table[index]; |
Bruce Allan | eb656d4 | 2009-12-01 15:47:02 +0000 | [diff] [blame] | 1800 | phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1801 | |
| 1802 | phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; |
| 1803 | |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1804 | return 0; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1805 | } |
| 1806 | |
| 1807 | /** |
| 1808 | * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY |
| 1809 | * @hw: pointer to the HW structure |
| 1810 | * |
| 1811 | * The automatic gain control (agc) normalizes the amplitude of the |
| 1812 | * received signal, adjusting for the attenuation produced by the |
Auke Kok | 489815c | 2008-02-21 15:11:07 -0800 | [diff] [blame] | 1813 | * cable. By reading the AGC registers, which represent the |
Bruce Allan | 5ff5b66 | 2009-12-01 15:51:11 +0000 | [diff] [blame] | 1814 | * combination of coarse and fine gain value, the value can be put |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1815 | * into a lookup table to obtain the approximate cable length |
| 1816 | * for each channel. |
| 1817 | **/ |
| 1818 | s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw) |
| 1819 | { |
| 1820 | struct e1000_phy_info *phy = &hw->phy; |
| 1821 | s32 ret_val; |
| 1822 | u16 phy_data, i, agc_value = 0; |
| 1823 | u16 cur_agc_index, max_agc_index = 0; |
| 1824 | u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; |
Jeff Kirsher | 6674450 | 2010-12-01 19:59:50 +0000 | [diff] [blame] | 1825 | static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = { |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 1826 | IGP02E1000_PHY_AGC_A, |
| 1827 | IGP02E1000_PHY_AGC_B, |
| 1828 | IGP02E1000_PHY_AGC_C, |
| 1829 | IGP02E1000_PHY_AGC_D |
Jeff Kirsher | 6674450 | 2010-12-01 19:59:50 +0000 | [diff] [blame] | 1830 | }; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1831 | |
| 1832 | /* Read the AGC registers for all channels */ |
| 1833 | for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { |
| 1834 | ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data); |
| 1835 | if (ret_val) |
| 1836 | return ret_val; |
| 1837 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 1838 | /* Getting bits 15:9, which represent the combination of |
Bruce Allan | 5ff5b66 | 2009-12-01 15:51:11 +0000 | [diff] [blame] | 1839 | * coarse and fine gain values. The result is a number |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1840 | * that can be put into the lookup table to obtain the |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1841 | * approximate cable length. |
| 1842 | */ |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 1843 | cur_agc_index = ((phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & |
| 1844 | IGP02E1000_AGC_LENGTH_MASK); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1845 | |
| 1846 | /* Array index bound check. */ |
| 1847 | if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) || |
| 1848 | (cur_agc_index == 0)) |
| 1849 | return -E1000_ERR_PHY; |
| 1850 | |
| 1851 | /* Remove min & max AGC values from calculation. */ |
| 1852 | if (e1000_igp_2_cable_length_table[min_agc_index] > |
| 1853 | e1000_igp_2_cable_length_table[cur_agc_index]) |
| 1854 | min_agc_index = cur_agc_index; |
| 1855 | if (e1000_igp_2_cable_length_table[max_agc_index] < |
| 1856 | e1000_igp_2_cable_length_table[cur_agc_index]) |
| 1857 | max_agc_index = cur_agc_index; |
| 1858 | |
| 1859 | agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; |
| 1860 | } |
| 1861 | |
| 1862 | agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + |
| 1863 | e1000_igp_2_cable_length_table[max_agc_index]); |
| 1864 | agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); |
| 1865 | |
| 1866 | /* Calculate cable length with the error range of +/- 10 meters. */ |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 1867 | phy->min_cable_length = (((agc_value - IGP02E1000_AGC_RANGE) > 0) ? |
| 1868 | (agc_value - IGP02E1000_AGC_RANGE) : 0); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1869 | phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE; |
| 1870 | |
| 1871 | phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; |
| 1872 | |
Bruce Allan | 8260725 | 2012-02-08 02:55:09 +0000 | [diff] [blame] | 1873 | return 0; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1874 | } |
| 1875 | |
| 1876 | /** |
| 1877 | * e1000e_get_phy_info_m88 - Retrieve PHY information |
| 1878 | * @hw: pointer to the HW structure |
| 1879 | * |
| 1880 | * Valid for only copper links. Read the PHY status register (sticky read) |
| 1881 | * to verify that link is up. Read the PHY special control register to |
| 1882 | * determine the polarity and 10base-T extended distance. Read the PHY |
| 1883 | * special status register to determine MDI/MDIx and current speed. If |
| 1884 | * speed is 1000, then determine cable length, local and remote receiver. |
| 1885 | **/ |
| 1886 | s32 e1000e_get_phy_info_m88(struct e1000_hw *hw) |
| 1887 | { |
| 1888 | struct e1000_phy_info *phy = &hw->phy; |
| 1889 | s32 ret_val; |
| 1890 | u16 phy_data; |
| 1891 | bool link; |
| 1892 | |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 1893 | if (phy->media_type != e1000_media_type_copper) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1894 | e_dbg("Phy info is only valid for copper media\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1895 | return -E1000_ERR_CONFIG; |
| 1896 | } |
| 1897 | |
| 1898 | ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); |
| 1899 | if (ret_val) |
| 1900 | return ret_val; |
| 1901 | |
| 1902 | if (!link) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1903 | e_dbg("Phy info is only valid if link is up\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1904 | return -E1000_ERR_CONFIG; |
| 1905 | } |
| 1906 | |
| 1907 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
| 1908 | if (ret_val) |
| 1909 | return ret_val; |
| 1910 | |
Bruce Allan | 04499ec | 2012-04-13 00:08:31 +0000 | [diff] [blame] | 1911 | phy->polarity_correction = !!(phy_data & |
| 1912 | M88E1000_PSCR_POLARITY_REVERSAL); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1913 | |
| 1914 | ret_val = e1000_check_polarity_m88(hw); |
| 1915 | if (ret_val) |
| 1916 | return ret_val; |
| 1917 | |
| 1918 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); |
| 1919 | if (ret_val) |
| 1920 | return ret_val; |
| 1921 | |
Bruce Allan | 04499ec | 2012-04-13 00:08:31 +0000 | [diff] [blame] | 1922 | phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1923 | |
| 1924 | if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { |
Bruce Allan | dde3a57 | 2013-01-05 08:06:24 +0000 | [diff] [blame] | 1925 | ret_val = hw->phy.ops.get_cable_length(hw); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1926 | if (ret_val) |
| 1927 | return ret_val; |
| 1928 | |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1929 | ret_val = e1e_rphy(hw, MII_STAT1000, &phy_data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1930 | if (ret_val) |
| 1931 | return ret_val; |
| 1932 | |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1933 | phy->local_rx = (phy_data & LPA_1000LOCALRXOK) |
| 1934 | ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1935 | |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1936 | phy->remote_rx = (phy_data & LPA_1000REMRXOK) |
| 1937 | ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1938 | } else { |
| 1939 | /* Set values to "undefined" */ |
| 1940 | phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; |
| 1941 | phy->local_rx = e1000_1000t_rx_status_undefined; |
| 1942 | phy->remote_rx = e1000_1000t_rx_status_undefined; |
| 1943 | } |
| 1944 | |
| 1945 | return ret_val; |
| 1946 | } |
| 1947 | |
| 1948 | /** |
| 1949 | * e1000e_get_phy_info_igp - Retrieve igp PHY information |
| 1950 | * @hw: pointer to the HW structure |
| 1951 | * |
| 1952 | * Read PHY status to determine if link is up. If link is up, then |
| 1953 | * set/determine 10base-T extended distance and polarity correction. Read |
| 1954 | * PHY port status to determine MDI/MDIx and speed. Based on the speed, |
| 1955 | * determine on the cable length, local and remote receiver. |
| 1956 | **/ |
| 1957 | s32 e1000e_get_phy_info_igp(struct e1000_hw *hw) |
| 1958 | { |
| 1959 | struct e1000_phy_info *phy = &hw->phy; |
| 1960 | s32 ret_val; |
| 1961 | u16 data; |
| 1962 | bool link; |
| 1963 | |
| 1964 | ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); |
| 1965 | if (ret_val) |
| 1966 | return ret_val; |
| 1967 | |
| 1968 | if (!link) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1969 | e_dbg("Phy info is only valid if link is up\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1970 | return -E1000_ERR_CONFIG; |
| 1971 | } |
| 1972 | |
Bruce Allan | 564ea9b | 2009-11-20 23:26:44 +0000 | [diff] [blame] | 1973 | phy->polarity_correction = true; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1974 | |
| 1975 | ret_val = e1000_check_polarity_igp(hw); |
| 1976 | if (ret_val) |
| 1977 | return ret_val; |
| 1978 | |
| 1979 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data); |
| 1980 | if (ret_val) |
| 1981 | return ret_val; |
| 1982 | |
Bruce Allan | 04499ec | 2012-04-13 00:08:31 +0000 | [diff] [blame] | 1983 | phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1984 | |
| 1985 | if ((data & IGP01E1000_PSSR_SPEED_MASK) == |
| 1986 | IGP01E1000_PSSR_SPEED_1000MBPS) { |
Bruce Allan | dde3a57 | 2013-01-05 08:06:24 +0000 | [diff] [blame] | 1987 | ret_val = phy->ops.get_cable_length(hw); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1988 | if (ret_val) |
| 1989 | return ret_val; |
| 1990 | |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1991 | ret_val = e1e_rphy(hw, MII_STAT1000, &data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1992 | if (ret_val) |
| 1993 | return ret_val; |
| 1994 | |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1995 | phy->local_rx = (data & LPA_1000LOCALRXOK) |
| 1996 | ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1997 | |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 1998 | phy->remote_rx = (data & LPA_1000REMRXOK) |
| 1999 | ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2000 | } else { |
| 2001 | phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; |
| 2002 | phy->local_rx = e1000_1000t_rx_status_undefined; |
| 2003 | phy->remote_rx = e1000_1000t_rx_status_undefined; |
| 2004 | } |
| 2005 | |
| 2006 | return ret_val; |
| 2007 | } |
| 2008 | |
| 2009 | /** |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 2010 | * e1000_get_phy_info_ife - Retrieves various IFE PHY states |
| 2011 | * @hw: pointer to the HW structure |
| 2012 | * |
| 2013 | * Populates "phy" structure with various feature states. |
| 2014 | **/ |
| 2015 | s32 e1000_get_phy_info_ife(struct e1000_hw *hw) |
| 2016 | { |
| 2017 | struct e1000_phy_info *phy = &hw->phy; |
| 2018 | s32 ret_val; |
| 2019 | u16 data; |
| 2020 | bool link; |
| 2021 | |
| 2022 | ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); |
| 2023 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2024 | return ret_val; |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 2025 | |
| 2026 | if (!link) { |
| 2027 | e_dbg("Phy info is only valid if link is up\n"); |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2028 | return -E1000_ERR_CONFIG; |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 2029 | } |
| 2030 | |
| 2031 | ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data); |
| 2032 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2033 | return ret_val; |
Bruce Allan | 04499ec | 2012-04-13 00:08:31 +0000 | [diff] [blame] | 2034 | phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE); |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 2035 | |
| 2036 | if (phy->polarity_correction) { |
| 2037 | ret_val = e1000_check_polarity_ife(hw); |
| 2038 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2039 | return ret_val; |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 2040 | } else { |
| 2041 | /* Polarity is forced */ |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 2042 | phy->cable_polarity = ((data & IFE_PSC_FORCE_POLARITY) |
| 2043 | ? e1000_rev_polarity_reversed |
| 2044 | : e1000_rev_polarity_normal); |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 2045 | } |
| 2046 | |
| 2047 | ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data); |
| 2048 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2049 | return ret_val; |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 2050 | |
Bruce Allan | 04499ec | 2012-04-13 00:08:31 +0000 | [diff] [blame] | 2051 | phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS); |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 2052 | |
| 2053 | /* The following parameters are undefined for 10/100 operation. */ |
| 2054 | phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; |
| 2055 | phy->local_rx = e1000_1000t_rx_status_undefined; |
| 2056 | phy->remote_rx = e1000_1000t_rx_status_undefined; |
| 2057 | |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2058 | return 0; |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 2059 | } |
| 2060 | |
| 2061 | /** |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2062 | * e1000e_phy_sw_reset - PHY software reset |
| 2063 | * @hw: pointer to the HW structure |
| 2064 | * |
| 2065 | * Does a software reset of the PHY by reading the PHY control register and |
| 2066 | * setting/write the control register reset bit to the PHY. |
| 2067 | **/ |
| 2068 | s32 e1000e_phy_sw_reset(struct e1000_hw *hw) |
| 2069 | { |
| 2070 | s32 ret_val; |
| 2071 | u16 phy_ctrl; |
| 2072 | |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 2073 | ret_val = e1e_rphy(hw, MII_BMCR, &phy_ctrl); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2074 | if (ret_val) |
| 2075 | return ret_val; |
| 2076 | |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 2077 | phy_ctrl |= BMCR_RESET; |
| 2078 | ret_val = e1e_wphy(hw, MII_BMCR, phy_ctrl); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2079 | if (ret_val) |
| 2080 | return ret_val; |
| 2081 | |
| 2082 | udelay(1); |
| 2083 | |
| 2084 | return ret_val; |
| 2085 | } |
| 2086 | |
| 2087 | /** |
| 2088 | * e1000e_phy_hw_reset_generic - PHY hardware reset |
| 2089 | * @hw: pointer to the HW structure |
| 2090 | * |
| 2091 | * Verify the reset block is not blocking us from resetting. Acquire |
| 2092 | * semaphore (if necessary) and read/set/write the device control reset |
| 2093 | * bit in the PHY. Wait the appropriate delay time for the device to |
Auke Kok | 489815c | 2008-02-21 15:11:07 -0800 | [diff] [blame] | 2094 | * reset and release the semaphore (if necessary). |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2095 | **/ |
| 2096 | s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw) |
| 2097 | { |
| 2098 | struct e1000_phy_info *phy = &hw->phy; |
| 2099 | s32 ret_val; |
| 2100 | u32 ctrl; |
| 2101 | |
Bruce Allan | 470a542 | 2012-05-26 06:08:48 +0000 | [diff] [blame] | 2102 | if (phy->ops.check_reset_block) { |
| 2103 | ret_val = phy->ops.check_reset_block(hw); |
| 2104 | if (ret_val) |
| 2105 | return 0; |
| 2106 | } |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2107 | |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 2108 | ret_val = phy->ops.acquire(hw); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2109 | if (ret_val) |
| 2110 | return ret_val; |
| 2111 | |
| 2112 | ctrl = er32(CTRL); |
| 2113 | ew32(CTRL, ctrl | E1000_CTRL_PHY_RST); |
| 2114 | e1e_flush(); |
| 2115 | |
| 2116 | udelay(phy->reset_delay_us); |
| 2117 | |
| 2118 | ew32(CTRL, ctrl); |
| 2119 | e1e_flush(); |
| 2120 | |
| 2121 | udelay(150); |
| 2122 | |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 2123 | phy->ops.release(hw); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2124 | |
Bruce Allan | 84c1bef | 2013-01-05 08:06:19 +0000 | [diff] [blame] | 2125 | return phy->ops.get_cfg_done(hw); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2126 | } |
| 2127 | |
| 2128 | /** |
Bruce Allan | fe90849 | 2013-01-05 08:06:14 +0000 | [diff] [blame] | 2129 | * e1000e_get_cfg_done_generic - Generic configuration done |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2130 | * @hw: pointer to the HW structure |
| 2131 | * |
| 2132 | * Generic function to wait 10 milli-seconds for configuration to complete |
| 2133 | * and return success. |
| 2134 | **/ |
Bruce Allan | 8bb6286 | 2013-01-16 08:46:49 +0000 | [diff] [blame] | 2135 | s32 e1000e_get_cfg_done_generic(struct e1000_hw __always_unused *hw) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2136 | { |
| 2137 | mdelay(10); |
Bruce Allan | 3d3a167 | 2012-02-23 03:13:18 +0000 | [diff] [blame] | 2138 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2139 | return 0; |
| 2140 | } |
| 2141 | |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 2142 | /** |
| 2143 | * e1000e_phy_init_script_igp3 - Inits the IGP3 PHY |
| 2144 | * @hw: pointer to the HW structure |
| 2145 | * |
| 2146 | * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. |
| 2147 | **/ |
| 2148 | s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw) |
| 2149 | { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 2150 | e_dbg("Running IGP 3 PHY init script\n"); |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 2151 | |
| 2152 | /* PHY init IGP 3 */ |
| 2153 | /* Enable rise/fall, 10-mode work in class-A */ |
| 2154 | e1e_wphy(hw, 0x2F5B, 0x9018); |
| 2155 | /* Remove all caps from Replica path filter */ |
| 2156 | e1e_wphy(hw, 0x2F52, 0x0000); |
| 2157 | /* Bias trimming for ADC, AFE and Driver (Default) */ |
| 2158 | e1e_wphy(hw, 0x2FB1, 0x8B24); |
| 2159 | /* Increase Hybrid poly bias */ |
| 2160 | e1e_wphy(hw, 0x2FB2, 0xF8F0); |
| 2161 | /* Add 4% to Tx amplitude in Gig mode */ |
| 2162 | e1e_wphy(hw, 0x2010, 0x10B0); |
| 2163 | /* Disable trimming (TTT) */ |
| 2164 | e1e_wphy(hw, 0x2011, 0x0000); |
| 2165 | /* Poly DC correction to 94.6% + 2% for all channels */ |
| 2166 | e1e_wphy(hw, 0x20DD, 0x249A); |
| 2167 | /* ABS DC correction to 95.9% */ |
| 2168 | e1e_wphy(hw, 0x20DE, 0x00D3); |
| 2169 | /* BG temp curve trim */ |
| 2170 | e1e_wphy(hw, 0x28B4, 0x04CE); |
| 2171 | /* Increasing ADC OPAMP stage 1 currents to max */ |
| 2172 | e1e_wphy(hw, 0x2F70, 0x29E4); |
| 2173 | /* Force 1000 ( required for enabling PHY regs configuration) */ |
| 2174 | e1e_wphy(hw, 0x0000, 0x0140); |
| 2175 | /* Set upd_freq to 6 */ |
| 2176 | e1e_wphy(hw, 0x1F30, 0x1606); |
| 2177 | /* Disable NPDFE */ |
| 2178 | e1e_wphy(hw, 0x1F31, 0xB814); |
| 2179 | /* Disable adaptive fixed FFE (Default) */ |
| 2180 | e1e_wphy(hw, 0x1F35, 0x002A); |
| 2181 | /* Enable FFE hysteresis */ |
| 2182 | e1e_wphy(hw, 0x1F3E, 0x0067); |
| 2183 | /* Fixed FFE for short cable lengths */ |
| 2184 | e1e_wphy(hw, 0x1F54, 0x0065); |
| 2185 | /* Fixed FFE for medium cable lengths */ |
| 2186 | e1e_wphy(hw, 0x1F55, 0x002A); |
| 2187 | /* Fixed FFE for long cable lengths */ |
| 2188 | e1e_wphy(hw, 0x1F56, 0x002A); |
| 2189 | /* Enable Adaptive Clip Threshold */ |
| 2190 | e1e_wphy(hw, 0x1F72, 0x3FB0); |
| 2191 | /* AHT reset limit to 1 */ |
| 2192 | e1e_wphy(hw, 0x1F76, 0xC0FF); |
| 2193 | /* Set AHT master delay to 127 msec */ |
| 2194 | e1e_wphy(hw, 0x1F77, 0x1DEC); |
| 2195 | /* Set scan bits for AHT */ |
| 2196 | e1e_wphy(hw, 0x1F78, 0xF9EF); |
| 2197 | /* Set AHT Preset bits */ |
| 2198 | e1e_wphy(hw, 0x1F79, 0x0210); |
| 2199 | /* Change integ_factor of channel A to 3 */ |
| 2200 | e1e_wphy(hw, 0x1895, 0x0003); |
| 2201 | /* Change prop_factor of channels BCD to 8 */ |
| 2202 | e1e_wphy(hw, 0x1796, 0x0008); |
| 2203 | /* Change cg_icount + enable integbp for channels BCD */ |
| 2204 | e1e_wphy(hw, 0x1798, 0xD008); |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 2205 | /* Change cg_icount + enable integbp + change prop_factor_master |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 2206 | * to 8 for channel A |
| 2207 | */ |
| 2208 | e1e_wphy(hw, 0x1898, 0xD918); |
| 2209 | /* Disable AHT in Slave mode on channel A */ |
| 2210 | e1e_wphy(hw, 0x187A, 0x0800); |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 2211 | /* Enable LPLU and disable AN to 1000 in non-D0a states, |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 2212 | * Enable SPD+B2B |
| 2213 | */ |
| 2214 | e1e_wphy(hw, 0x0019, 0x008D); |
| 2215 | /* Enable restart AN on an1000_dis change */ |
| 2216 | e1e_wphy(hw, 0x001B, 0x2080); |
| 2217 | /* Enable wh_fifo read clock in 10/100 modes */ |
| 2218 | e1e_wphy(hw, 0x0014, 0x0045); |
| 2219 | /* Restart AN, Speed selection is 1000 */ |
| 2220 | e1e_wphy(hw, 0x0000, 0x1340); |
| 2221 | |
| 2222 | return 0; |
| 2223 | } |
| 2224 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2225 | /** |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2226 | * e1000e_get_phy_type_from_id - Get PHY type from id |
| 2227 | * @phy_id: phy_id read from the phy |
| 2228 | * |
| 2229 | * Returns the phy type from the id. |
| 2230 | **/ |
| 2231 | enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id) |
| 2232 | { |
| 2233 | enum e1000_phy_type phy_type = e1000_phy_unknown; |
| 2234 | |
| 2235 | switch (phy_id) { |
| 2236 | case M88E1000_I_PHY_ID: |
| 2237 | case M88E1000_E_PHY_ID: |
| 2238 | case M88E1111_I_PHY_ID: |
| 2239 | case M88E1011_I_PHY_ID: |
| 2240 | phy_type = e1000_phy_m88; |
| 2241 | break; |
| 2242 | case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */ |
| 2243 | phy_type = e1000_phy_igp_2; |
| 2244 | break; |
| 2245 | case GG82563_E_PHY_ID: |
| 2246 | phy_type = e1000_phy_gg82563; |
| 2247 | break; |
| 2248 | case IGP03E1000_E_PHY_ID: |
| 2249 | phy_type = e1000_phy_igp_3; |
| 2250 | break; |
| 2251 | case IFE_E_PHY_ID: |
| 2252 | case IFE_PLUS_E_PHY_ID: |
| 2253 | case IFE_C_E_PHY_ID: |
| 2254 | phy_type = e1000_phy_ife; |
| 2255 | break; |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2256 | case BME1000_E_PHY_ID: |
| 2257 | case BME1000_E_PHY_ID_R2: |
| 2258 | phy_type = e1000_phy_bm; |
| 2259 | break; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2260 | case I82578_E_PHY_ID: |
| 2261 | phy_type = e1000_phy_82578; |
| 2262 | break; |
| 2263 | case I82577_E_PHY_ID: |
| 2264 | phy_type = e1000_phy_82577; |
| 2265 | break; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 2266 | case I82579_E_PHY_ID: |
| 2267 | phy_type = e1000_phy_82579; |
| 2268 | break; |
Bruce Allan | 2fbe452 | 2012-04-19 03:21:47 +0000 | [diff] [blame] | 2269 | case I217_E_PHY_ID: |
| 2270 | phy_type = e1000_phy_i217; |
| 2271 | break; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2272 | default: |
| 2273 | phy_type = e1000_phy_unknown; |
| 2274 | break; |
| 2275 | } |
| 2276 | return phy_type; |
| 2277 | } |
| 2278 | |
| 2279 | /** |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2280 | * e1000e_determine_phy_address - Determines PHY address. |
| 2281 | * @hw: pointer to the HW structure |
| 2282 | * |
| 2283 | * This uses a trial and error method to loop through possible PHY |
| 2284 | * addresses. It tests each by reading the PHY ID registers and |
| 2285 | * checking for a match. |
| 2286 | **/ |
| 2287 | s32 e1000e_determine_phy_address(struct e1000_hw *hw) |
| 2288 | { |
Bruce Allan | 5eb6f3c | 2009-12-02 17:02:43 +0000 | [diff] [blame] | 2289 | u32 phy_addr = 0; |
| 2290 | u32 i; |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2291 | enum e1000_phy_type phy_type = e1000_phy_unknown; |
| 2292 | |
Bruce Allan | 5eb6f3c | 2009-12-02 17:02:43 +0000 | [diff] [blame] | 2293 | hw->phy.id = phy_type; |
| 2294 | |
| 2295 | for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) { |
| 2296 | hw->phy.addr = phy_addr; |
| 2297 | i = 0; |
| 2298 | |
| 2299 | do { |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2300 | e1000e_get_phy_id(hw); |
| 2301 | phy_type = e1000e_get_phy_type_from_id(hw->phy.id); |
| 2302 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 2303 | /* If phy_type is valid, break - we found our |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2304 | * PHY address |
| 2305 | */ |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2306 | if (phy_type != e1000_phy_unknown) |
| 2307 | return 0; |
| 2308 | |
Bruce Allan | 1bba438 | 2011-03-19 00:27:20 +0000 | [diff] [blame] | 2309 | usleep_range(1000, 2000); |
Bruce Allan | 5eb6f3c | 2009-12-02 17:02:43 +0000 | [diff] [blame] | 2310 | i++; |
| 2311 | } while (i < 10); |
| 2312 | } |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2313 | |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2314 | return -E1000_ERR_PHY_TYPE; |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2315 | } |
| 2316 | |
| 2317 | /** |
| 2318 | * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address |
| 2319 | * @page: page to access |
| 2320 | * |
| 2321 | * Returns the phy address for the page requested. |
| 2322 | **/ |
| 2323 | static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg) |
| 2324 | { |
| 2325 | u32 phy_addr = 2; |
| 2326 | |
| 2327 | if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31)) |
| 2328 | phy_addr = 1; |
| 2329 | |
| 2330 | return phy_addr; |
| 2331 | } |
| 2332 | |
| 2333 | /** |
| 2334 | * e1000e_write_phy_reg_bm - Write BM PHY register |
| 2335 | * @hw: pointer to the HW structure |
| 2336 | * @offset: register offset to write to |
| 2337 | * @data: data to write at register offset |
| 2338 | * |
| 2339 | * Acquires semaphore, if necessary, then writes the data to PHY register |
| 2340 | * at the offset. Release any acquired semaphores before exiting. |
| 2341 | **/ |
| 2342 | s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data) |
| 2343 | { |
| 2344 | s32 ret_val; |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2345 | u32 page = offset >> IGP_PAGE_SHIFT; |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2346 | |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 2347 | ret_val = hw->phy.ops.acquire(hw); |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2348 | if (ret_val) |
| 2349 | return ret_val; |
| 2350 | |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2351 | /* Page 800 works differently than the rest so it has its own func */ |
| 2352 | if (page == BM_WUC_PAGE) { |
| 2353 | ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2354 | false, false); |
Bruce Allan | 75ce153 | 2012-02-08 02:54:48 +0000 | [diff] [blame] | 2355 | goto release; |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2356 | } |
| 2357 | |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2358 | hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); |
| 2359 | |
| 2360 | if (offset > MAX_PHY_MULTI_PAGE_REG) { |
Bruce Allan | 90da066 | 2011-01-06 07:02:53 +0000 | [diff] [blame] | 2361 | u32 page_shift, page_select; |
| 2362 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 2363 | /* Page select is register 31 for phy address 1 and 22 for |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2364 | * phy address 2 and 3. Page select is shifted only for |
| 2365 | * phy address 1. |
| 2366 | */ |
| 2367 | if (hw->phy.addr == 1) { |
| 2368 | page_shift = IGP_PAGE_SHIFT; |
| 2369 | page_select = IGP01E1000_PHY_PAGE_SELECT; |
| 2370 | } else { |
| 2371 | page_shift = 0; |
| 2372 | page_select = BM_PHY_PAGE_SELECT; |
| 2373 | } |
| 2374 | |
| 2375 | /* Page is shifted left, PHY expects (page x 32) */ |
| 2376 | ret_val = e1000e_write_phy_reg_mdic(hw, page_select, |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 2377 | (page << page_shift)); |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2378 | if (ret_val) |
Bruce Allan | 75ce153 | 2012-02-08 02:54:48 +0000 | [diff] [blame] | 2379 | goto release; |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2380 | } |
| 2381 | |
| 2382 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 2383 | data); |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2384 | |
Bruce Allan | 75ce153 | 2012-02-08 02:54:48 +0000 | [diff] [blame] | 2385 | release: |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 2386 | hw->phy.ops.release(hw); |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2387 | return ret_val; |
| 2388 | } |
| 2389 | |
| 2390 | /** |
| 2391 | * e1000e_read_phy_reg_bm - Read BM PHY register |
| 2392 | * @hw: pointer to the HW structure |
| 2393 | * @offset: register offset to be read |
| 2394 | * @data: pointer to the read data |
| 2395 | * |
| 2396 | * Acquires semaphore, if necessary, then reads the PHY register at offset |
| 2397 | * and storing the retrieved information in data. Release any acquired |
| 2398 | * semaphores before exiting. |
| 2399 | **/ |
| 2400 | s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data) |
| 2401 | { |
| 2402 | s32 ret_val; |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2403 | u32 page = offset >> IGP_PAGE_SHIFT; |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2404 | |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 2405 | ret_val = hw->phy.ops.acquire(hw); |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2406 | if (ret_val) |
| 2407 | return ret_val; |
| 2408 | |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2409 | /* Page 800 works differently than the rest so it has its own func */ |
| 2410 | if (page == BM_WUC_PAGE) { |
| 2411 | ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2412 | true, false); |
Bruce Allan | 75ce153 | 2012-02-08 02:54:48 +0000 | [diff] [blame] | 2413 | goto release; |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2414 | } |
| 2415 | |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2416 | hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); |
| 2417 | |
| 2418 | if (offset > MAX_PHY_MULTI_PAGE_REG) { |
Bruce Allan | 90da066 | 2011-01-06 07:02:53 +0000 | [diff] [blame] | 2419 | u32 page_shift, page_select; |
| 2420 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 2421 | /* Page select is register 31 for phy address 1 and 22 for |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2422 | * phy address 2 and 3. Page select is shifted only for |
| 2423 | * phy address 1. |
| 2424 | */ |
| 2425 | if (hw->phy.addr == 1) { |
| 2426 | page_shift = IGP_PAGE_SHIFT; |
| 2427 | page_select = IGP01E1000_PHY_PAGE_SELECT; |
| 2428 | } else { |
| 2429 | page_shift = 0; |
| 2430 | page_select = BM_PHY_PAGE_SELECT; |
| 2431 | } |
| 2432 | |
| 2433 | /* Page is shifted left, PHY expects (page x 32) */ |
| 2434 | ret_val = e1000e_write_phy_reg_mdic(hw, page_select, |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 2435 | (page << page_shift)); |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2436 | if (ret_val) |
Bruce Allan | 75ce153 | 2012-02-08 02:54:48 +0000 | [diff] [blame] | 2437 | goto release; |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2438 | } |
| 2439 | |
| 2440 | ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 2441 | data); |
Bruce Allan | 75ce153 | 2012-02-08 02:54:48 +0000 | [diff] [blame] | 2442 | release: |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 2443 | hw->phy.ops.release(hw); |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2444 | return ret_val; |
| 2445 | } |
| 2446 | |
| 2447 | /** |
Bruce Allan | 4662e82 | 2008-08-26 18:37:06 -0700 | [diff] [blame] | 2448 | * e1000e_read_phy_reg_bm2 - Read BM PHY register |
| 2449 | * @hw: pointer to the HW structure |
| 2450 | * @offset: register offset to be read |
| 2451 | * @data: pointer to the read data |
| 2452 | * |
| 2453 | * Acquires semaphore, if necessary, then reads the PHY register at offset |
| 2454 | * and storing the retrieved information in data. Release any acquired |
| 2455 | * semaphores before exiting. |
| 2456 | **/ |
| 2457 | s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data) |
| 2458 | { |
| 2459 | s32 ret_val; |
| 2460 | u16 page = (u16)(offset >> IGP_PAGE_SHIFT); |
| 2461 | |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 2462 | ret_val = hw->phy.ops.acquire(hw); |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2463 | if (ret_val) |
| 2464 | return ret_val; |
| 2465 | |
Bruce Allan | 4662e82 | 2008-08-26 18:37:06 -0700 | [diff] [blame] | 2466 | /* Page 800 works differently than the rest so it has its own func */ |
| 2467 | if (page == BM_WUC_PAGE) { |
| 2468 | ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2469 | true, false); |
Bruce Allan | 75ce153 | 2012-02-08 02:54:48 +0000 | [diff] [blame] | 2470 | goto release; |
Bruce Allan | 4662e82 | 2008-08-26 18:37:06 -0700 | [diff] [blame] | 2471 | } |
| 2472 | |
Bruce Allan | 4662e82 | 2008-08-26 18:37:06 -0700 | [diff] [blame] | 2473 | hw->phy.addr = 1; |
| 2474 | |
| 2475 | if (offset > MAX_PHY_MULTI_PAGE_REG) { |
Bruce Allan | 4662e82 | 2008-08-26 18:37:06 -0700 | [diff] [blame] | 2476 | /* Page is shifted left, PHY expects (page x 32) */ |
| 2477 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, |
| 2478 | page); |
| 2479 | |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2480 | if (ret_val) |
Bruce Allan | 75ce153 | 2012-02-08 02:54:48 +0000 | [diff] [blame] | 2481 | goto release; |
Bruce Allan | 4662e82 | 2008-08-26 18:37:06 -0700 | [diff] [blame] | 2482 | } |
| 2483 | |
| 2484 | ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
| 2485 | data); |
Bruce Allan | 75ce153 | 2012-02-08 02:54:48 +0000 | [diff] [blame] | 2486 | release: |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 2487 | hw->phy.ops.release(hw); |
Bruce Allan | 4662e82 | 2008-08-26 18:37:06 -0700 | [diff] [blame] | 2488 | return ret_val; |
| 2489 | } |
| 2490 | |
| 2491 | /** |
| 2492 | * e1000e_write_phy_reg_bm2 - Write BM PHY register |
| 2493 | * @hw: pointer to the HW structure |
| 2494 | * @offset: register offset to write to |
| 2495 | * @data: data to write at register offset |
| 2496 | * |
| 2497 | * Acquires semaphore, if necessary, then writes the data to PHY register |
| 2498 | * at the offset. Release any acquired semaphores before exiting. |
| 2499 | **/ |
| 2500 | s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data) |
| 2501 | { |
| 2502 | s32 ret_val; |
| 2503 | u16 page = (u16)(offset >> IGP_PAGE_SHIFT); |
| 2504 | |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 2505 | ret_val = hw->phy.ops.acquire(hw); |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2506 | if (ret_val) |
| 2507 | return ret_val; |
| 2508 | |
Bruce Allan | 4662e82 | 2008-08-26 18:37:06 -0700 | [diff] [blame] | 2509 | /* Page 800 works differently than the rest so it has its own func */ |
| 2510 | if (page == BM_WUC_PAGE) { |
| 2511 | ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2512 | false, false); |
Bruce Allan | 75ce153 | 2012-02-08 02:54:48 +0000 | [diff] [blame] | 2513 | goto release; |
Bruce Allan | 4662e82 | 2008-08-26 18:37:06 -0700 | [diff] [blame] | 2514 | } |
| 2515 | |
Bruce Allan | 4662e82 | 2008-08-26 18:37:06 -0700 | [diff] [blame] | 2516 | hw->phy.addr = 1; |
| 2517 | |
| 2518 | if (offset > MAX_PHY_MULTI_PAGE_REG) { |
| 2519 | /* Page is shifted left, PHY expects (page x 32) */ |
| 2520 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, |
| 2521 | page); |
| 2522 | |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2523 | if (ret_val) |
Bruce Allan | 75ce153 | 2012-02-08 02:54:48 +0000 | [diff] [blame] | 2524 | goto release; |
Bruce Allan | 4662e82 | 2008-08-26 18:37:06 -0700 | [diff] [blame] | 2525 | } |
| 2526 | |
| 2527 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
| 2528 | data); |
| 2529 | |
Bruce Allan | 75ce153 | 2012-02-08 02:54:48 +0000 | [diff] [blame] | 2530 | release: |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 2531 | hw->phy.ops.release(hw); |
Bruce Allan | 4662e82 | 2008-08-26 18:37:06 -0700 | [diff] [blame] | 2532 | return ret_val; |
| 2533 | } |
| 2534 | |
| 2535 | /** |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2536 | * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers |
| 2537 | * @hw: pointer to the HW structure |
| 2538 | * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG |
| 2539 | * |
| 2540 | * Assumes semaphore already acquired and phy_reg points to a valid memory |
| 2541 | * address to store contents of the BM_WUC_ENABLE_REG register. |
| 2542 | **/ |
| 2543 | s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) |
| 2544 | { |
| 2545 | s32 ret_val; |
| 2546 | u16 temp; |
| 2547 | |
| 2548 | /* All page select, port ctrl and wakeup registers use phy address 1 */ |
| 2549 | hw->phy.addr = 1; |
| 2550 | |
| 2551 | /* Select Port Control Registers page */ |
| 2552 | ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT)); |
| 2553 | if (ret_val) { |
| 2554 | e_dbg("Could not set Port Control page\n"); |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2555 | return ret_val; |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2556 | } |
| 2557 | |
| 2558 | ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); |
| 2559 | if (ret_val) { |
| 2560 | e_dbg("Could not read PHY register %d.%d\n", |
| 2561 | BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2562 | return ret_val; |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2563 | } |
| 2564 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 2565 | /* Enable both PHY wakeup mode and Wakeup register page writes. |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2566 | * Prevent a power state change by disabling ME and Host PHY wakeup. |
| 2567 | */ |
| 2568 | temp = *phy_reg; |
| 2569 | temp |= BM_WUC_ENABLE_BIT; |
| 2570 | temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT); |
| 2571 | |
| 2572 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp); |
| 2573 | if (ret_val) { |
| 2574 | e_dbg("Could not write PHY register %d.%d\n", |
| 2575 | BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2576 | return ret_val; |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2577 | } |
| 2578 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 2579 | /* Select Host Wakeup Registers page - caller now able to write |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2580 | * registers on the Wakeup registers page |
| 2581 | */ |
| 2582 | return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT)); |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2583 | } |
| 2584 | |
| 2585 | /** |
| 2586 | * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs |
| 2587 | * @hw: pointer to the HW structure |
| 2588 | * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG |
| 2589 | * |
| 2590 | * Restore BM_WUC_ENABLE_REG to its original value. |
| 2591 | * |
| 2592 | * Assumes semaphore already acquired and *phy_reg is the contents of the |
| 2593 | * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by |
| 2594 | * caller. |
| 2595 | **/ |
| 2596 | s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) |
| 2597 | { |
Bruce Allan | 70806a7 | 2013-01-05 05:08:37 +0000 | [diff] [blame] | 2598 | s32 ret_val; |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2599 | |
| 2600 | /* Select Port Control Registers page */ |
| 2601 | ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT)); |
| 2602 | if (ret_val) { |
| 2603 | e_dbg("Could not set Port Control page\n"); |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2604 | return ret_val; |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2605 | } |
| 2606 | |
| 2607 | /* Restore 769.17 to its original value */ |
| 2608 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg); |
| 2609 | if (ret_val) |
| 2610 | e_dbg("Could not restore PHY register %d.%d\n", |
| 2611 | BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2612 | |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2613 | return ret_val; |
| 2614 | } |
| 2615 | |
| 2616 | /** |
| 2617 | * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2618 | * @hw: pointer to the HW structure |
| 2619 | * @offset: register offset to be read or written |
| 2620 | * @data: pointer to the data to read or write |
| 2621 | * @read: determines if operation is read or write |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2622 | * @page_set: BM_WUC_PAGE already set and access enabled |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2623 | * |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2624 | * Read the PHY register at offset and store the retrieved information in |
| 2625 | * data, or write data to PHY register at offset. Note the procedure to |
| 2626 | * access the PHY wakeup registers is different than reading the other PHY |
| 2627 | * registers. It works as such: |
| 2628 | * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1 |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2629 | * 2) Set page to 800 for host (801 if we were manageability) |
| 2630 | * 3) Write the address using the address opcode (0x11) |
| 2631 | * 4) Read or write the data using the data opcode (0x12) |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2632 | * 5) Restore 769.17.2 to its original value |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2633 | * |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2634 | * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and |
| 2635 | * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm(). |
| 2636 | * |
| 2637 | * Assumes semaphore is already acquired. When page_set==true, assumes |
| 2638 | * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack |
| 2639 | * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()). |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2640 | **/ |
| 2641 | static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2642 | u16 *data, bool read, bool page_set) |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2643 | { |
| 2644 | s32 ret_val; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2645 | u16 reg = BM_PHY_REG_NUM(offset); |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2646 | u16 page = BM_PHY_REG_PAGE(offset); |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2647 | u16 phy_reg = 0; |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2648 | |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2649 | /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */ |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2650 | if ((hw->mac.type == e1000_pchlan) && |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2651 | (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE))) |
| 2652 | e_dbg("Attempting to access page %d while gig enabled.\n", |
| 2653 | page); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2654 | |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2655 | if (!page_set) { |
| 2656 | /* Enable access to PHY wakeup registers */ |
| 2657 | ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); |
| 2658 | if (ret_val) { |
| 2659 | e_dbg("Could not enable PHY wakeup reg access\n"); |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2660 | return ret_val; |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2661 | } |
Bruce Allan | 9b71b41 | 2009-12-01 15:53:07 +0000 | [diff] [blame] | 2662 | } |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2663 | |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2664 | e_dbg("Accessing PHY page %d reg 0x%x\n", page, reg); |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2665 | |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2666 | /* Write the Wakeup register page offset value using opcode 0x11 */ |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2667 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg); |
Bruce Allan | 9b71b41 | 2009-12-01 15:53:07 +0000 | [diff] [blame] | 2668 | if (ret_val) { |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2669 | e_dbg("Could not write address opcode to page %d\n", page); |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2670 | return ret_val; |
Bruce Allan | 9b71b41 | 2009-12-01 15:53:07 +0000 | [diff] [blame] | 2671 | } |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2672 | |
| 2673 | if (read) { |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2674 | /* Read the Wakeup register page value using opcode 0x12 */ |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2675 | ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 2676 | data); |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2677 | } else { |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2678 | /* Write the Wakeup register page value using opcode 0x12 */ |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2679 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, |
| 2680 | *data); |
| 2681 | } |
| 2682 | |
Bruce Allan | 9b71b41 | 2009-12-01 15:53:07 +0000 | [diff] [blame] | 2683 | if (ret_val) { |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2684 | e_dbg("Could not access PHY reg %d.%d\n", page, reg); |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2685 | return ret_val; |
Bruce Allan | 9b71b41 | 2009-12-01 15:53:07 +0000 | [diff] [blame] | 2686 | } |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2687 | |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2688 | if (!page_set) |
| 2689 | ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2690 | |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 2691 | return ret_val; |
| 2692 | } |
| 2693 | |
| 2694 | /** |
Bruce Allan | 17f208d | 2009-12-01 15:47:22 +0000 | [diff] [blame] | 2695 | * e1000_power_up_phy_copper - Restore copper link in case of PHY power down |
| 2696 | * @hw: pointer to the HW structure |
| 2697 | * |
| 2698 | * In the case of a PHY power down to save power, or to turn off link during a |
| 2699 | * driver unload, or wake on lan is not enabled, restore the link to previous |
| 2700 | * settings. |
| 2701 | **/ |
| 2702 | void e1000_power_up_phy_copper(struct e1000_hw *hw) |
| 2703 | { |
| 2704 | u16 mii_reg = 0; |
| 2705 | |
| 2706 | /* The PHY will retain its settings across a power down/up cycle */ |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 2707 | e1e_rphy(hw, MII_BMCR, &mii_reg); |
| 2708 | mii_reg &= ~BMCR_PDOWN; |
| 2709 | e1e_wphy(hw, MII_BMCR, mii_reg); |
Bruce Allan | 17f208d | 2009-12-01 15:47:22 +0000 | [diff] [blame] | 2710 | } |
| 2711 | |
| 2712 | /** |
| 2713 | * e1000_power_down_phy_copper - Restore copper link in case of PHY power down |
| 2714 | * @hw: pointer to the HW structure |
| 2715 | * |
| 2716 | * In the case of a PHY power down to save power, or to turn off link during a |
| 2717 | * driver unload, or wake on lan is not enabled, restore the link to previous |
| 2718 | * settings. |
| 2719 | **/ |
| 2720 | void e1000_power_down_phy_copper(struct e1000_hw *hw) |
| 2721 | { |
| 2722 | u16 mii_reg = 0; |
| 2723 | |
| 2724 | /* The PHY will retain its settings across a power down/up cycle */ |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 2725 | e1e_rphy(hw, MII_BMCR, &mii_reg); |
| 2726 | mii_reg |= BMCR_PDOWN; |
| 2727 | e1e_wphy(hw, MII_BMCR, mii_reg); |
Bruce Allan | 1bba438 | 2011-03-19 00:27:20 +0000 | [diff] [blame] | 2728 | usleep_range(1000, 2000); |
Bruce Allan | 17f208d | 2009-12-01 15:47:22 +0000 | [diff] [blame] | 2729 | } |
| 2730 | |
| 2731 | /** |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2732 | * __e1000_read_phy_reg_hv - Read HV PHY register |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2733 | * @hw: pointer to the HW structure |
| 2734 | * @offset: register offset to be read |
| 2735 | * @data: pointer to the read data |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2736 | * @locked: semaphore has already been acquired or not |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2737 | * |
| 2738 | * Acquires semaphore, if necessary, then reads the PHY register at offset |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2739 | * and stores the retrieved information in data. Release any acquired |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2740 | * semaphore before exiting. |
| 2741 | **/ |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2742 | static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data, |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2743 | bool locked, bool page_set) |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2744 | { |
| 2745 | s32 ret_val; |
| 2746 | u16 page = BM_PHY_REG_PAGE(offset); |
| 2747 | u16 reg = BM_PHY_REG_NUM(offset); |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2748 | u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2749 | |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2750 | if (!locked) { |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 2751 | ret_val = hw->phy.ops.acquire(hw); |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2752 | if (ret_val) |
| 2753 | return ret_val; |
| 2754 | } |
| 2755 | |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2756 | /* Page 800 works differently than the rest so it has its own func */ |
| 2757 | if (page == BM_WUC_PAGE) { |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2758 | ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, |
| 2759 | true, page_set); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2760 | goto out; |
| 2761 | } |
| 2762 | |
| 2763 | if (page > 0 && page < HV_INTC_FC_PAGE_START) { |
| 2764 | ret_val = e1000_access_phy_debug_regs_hv(hw, offset, |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 2765 | data, true); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2766 | goto out; |
| 2767 | } |
| 2768 | |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2769 | if (!page_set) { |
| 2770 | if (page == HV_INTC_FC_PAGE_START) |
| 2771 | page = 0; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2772 | |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2773 | if (reg > MAX_PHY_MULTI_PAGE_REG) { |
| 2774 | /* Page is shifted left, PHY expects (page x 32) */ |
| 2775 | ret_val = e1000_set_page_igp(hw, |
| 2776 | (page << IGP_PAGE_SHIFT)); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2777 | |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2778 | hw->phy.addr = phy_addr; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2779 | |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2780 | if (ret_val) |
| 2781 | goto out; |
| 2782 | } |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2783 | } |
| 2784 | |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2785 | e_dbg("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page, |
| 2786 | page << IGP_PAGE_SHIFT, reg); |
| 2787 | |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 2788 | ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, data); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2789 | out: |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2790 | if (!locked) |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 2791 | hw->phy.ops.release(hw); |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2792 | |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2793 | return ret_val; |
| 2794 | } |
| 2795 | |
| 2796 | /** |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2797 | * e1000_read_phy_reg_hv - Read HV PHY register |
| 2798 | * @hw: pointer to the HW structure |
| 2799 | * @offset: register offset to be read |
| 2800 | * @data: pointer to the read data |
| 2801 | * |
| 2802 | * Acquires semaphore then reads the PHY register at offset and stores |
| 2803 | * the retrieved information in data. Release the acquired semaphore |
| 2804 | * before exiting. |
| 2805 | **/ |
| 2806 | s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data) |
| 2807 | { |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2808 | return __e1000_read_phy_reg_hv(hw, offset, data, false, false); |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2809 | } |
| 2810 | |
| 2811 | /** |
| 2812 | * e1000_read_phy_reg_hv_locked - Read HV PHY register |
| 2813 | * @hw: pointer to the HW structure |
| 2814 | * @offset: register offset to be read |
| 2815 | * @data: pointer to the read data |
| 2816 | * |
| 2817 | * Reads the PHY register at offset and stores the retrieved information |
| 2818 | * in data. Assumes semaphore already acquired. |
| 2819 | **/ |
| 2820 | s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data) |
| 2821 | { |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2822 | return __e1000_read_phy_reg_hv(hw, offset, data, true, false); |
| 2823 | } |
| 2824 | |
| 2825 | /** |
| 2826 | * e1000_read_phy_reg_page_hv - Read HV PHY register |
| 2827 | * @hw: pointer to the HW structure |
| 2828 | * @offset: register offset to write to |
| 2829 | * @data: data to write at register offset |
| 2830 | * |
| 2831 | * Reads the PHY register at offset and stores the retrieved information |
| 2832 | * in data. Assumes semaphore already acquired and page already set. |
| 2833 | **/ |
| 2834 | s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data) |
| 2835 | { |
| 2836 | return __e1000_read_phy_reg_hv(hw, offset, data, true, true); |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2837 | } |
| 2838 | |
| 2839 | /** |
| 2840 | * __e1000_write_phy_reg_hv - Write HV PHY register |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2841 | * @hw: pointer to the HW structure |
| 2842 | * @offset: register offset to write to |
| 2843 | * @data: data to write at register offset |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2844 | * @locked: semaphore has already been acquired or not |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2845 | * |
| 2846 | * Acquires semaphore, if necessary, then writes the data to PHY register |
| 2847 | * at the offset. Release any acquired semaphores before exiting. |
| 2848 | **/ |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2849 | static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data, |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2850 | bool locked, bool page_set) |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2851 | { |
| 2852 | s32 ret_val; |
| 2853 | u16 page = BM_PHY_REG_PAGE(offset); |
| 2854 | u16 reg = BM_PHY_REG_NUM(offset); |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2855 | u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2856 | |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2857 | if (!locked) { |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 2858 | ret_val = hw->phy.ops.acquire(hw); |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2859 | if (ret_val) |
| 2860 | return ret_val; |
| 2861 | } |
| 2862 | |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2863 | /* Page 800 works differently than the rest so it has its own func */ |
| 2864 | if (page == BM_WUC_PAGE) { |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2865 | ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, |
| 2866 | false, page_set); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2867 | goto out; |
| 2868 | } |
| 2869 | |
| 2870 | if (page > 0 && page < HV_INTC_FC_PAGE_START) { |
| 2871 | ret_val = e1000_access_phy_debug_regs_hv(hw, offset, |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 2872 | &data, false); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2873 | goto out; |
| 2874 | } |
| 2875 | |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2876 | if (!page_set) { |
| 2877 | if (page == HV_INTC_FC_PAGE_START) |
| 2878 | page = 0; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2879 | |
Bruce Allan | e921eb1 | 2012-11-28 09:28:37 +0000 | [diff] [blame] | 2880 | /* Workaround MDIO accesses being disabled after entering IEEE |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2881 | * Power Down (when bit 11 of the PHY Control register is set) |
| 2882 | */ |
| 2883 | if ((hw->phy.type == e1000_phy_82578) && |
| 2884 | (hw->phy.revision >= 1) && |
| 2885 | (hw->phy.addr == 2) && |
Bruce Allan | 04499ec | 2012-04-13 00:08:31 +0000 | [diff] [blame] | 2886 | !(MAX_PHY_REG_ADDRESS & reg) && (data & (1 << 11))) { |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2887 | u16 data2 = 0x7EFF; |
| 2888 | ret_val = e1000_access_phy_debug_regs_hv(hw, |
| 2889 | (1 << 6) | 0x3, |
| 2890 | &data2, false); |
| 2891 | if (ret_val) |
| 2892 | goto out; |
| 2893 | } |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2894 | |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2895 | if (reg > MAX_PHY_MULTI_PAGE_REG) { |
| 2896 | /* Page is shifted left, PHY expects (page x 32) */ |
| 2897 | ret_val = e1000_set_page_igp(hw, |
| 2898 | (page << IGP_PAGE_SHIFT)); |
| 2899 | |
| 2900 | hw->phy.addr = phy_addr; |
| 2901 | |
| 2902 | if (ret_val) |
| 2903 | goto out; |
| 2904 | } |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2905 | } |
| 2906 | |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2907 | e_dbg("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page, |
| 2908 | page << IGP_PAGE_SHIFT, reg); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2909 | |
| 2910 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 2911 | data); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2912 | |
| 2913 | out: |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2914 | if (!locked) |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 2915 | hw->phy.ops.release(hw); |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2916 | |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2917 | return ret_val; |
| 2918 | } |
| 2919 | |
| 2920 | /** |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2921 | * e1000_write_phy_reg_hv - Write HV PHY register |
| 2922 | * @hw: pointer to the HW structure |
| 2923 | * @offset: register offset to write to |
| 2924 | * @data: data to write at register offset |
| 2925 | * |
| 2926 | * Acquires semaphore then writes the data to PHY register at the offset. |
| 2927 | * Release the acquired semaphores before exiting. |
| 2928 | **/ |
| 2929 | s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data) |
| 2930 | { |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2931 | return __e1000_write_phy_reg_hv(hw, offset, data, false, false); |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2932 | } |
| 2933 | |
| 2934 | /** |
| 2935 | * e1000_write_phy_reg_hv_locked - Write HV PHY register |
| 2936 | * @hw: pointer to the HW structure |
| 2937 | * @offset: register offset to write to |
| 2938 | * @data: data to write at register offset |
| 2939 | * |
| 2940 | * Writes the data to PHY register at the offset. Assumes semaphore |
| 2941 | * already acquired. |
| 2942 | **/ |
| 2943 | s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data) |
| 2944 | { |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2945 | return __e1000_write_phy_reg_hv(hw, offset, data, true, false); |
| 2946 | } |
| 2947 | |
| 2948 | /** |
| 2949 | * e1000_write_phy_reg_page_hv - Write HV PHY register |
| 2950 | * @hw: pointer to the HW structure |
| 2951 | * @offset: register offset to write to |
| 2952 | * @data: data to write at register offset |
| 2953 | * |
| 2954 | * Writes the data to PHY register at the offset. Assumes semaphore |
| 2955 | * already acquired and page already set. |
| 2956 | **/ |
| 2957 | s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data) |
| 2958 | { |
| 2959 | return __e1000_write_phy_reg_hv(hw, offset, data, true, true); |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2960 | } |
| 2961 | |
| 2962 | /** |
Uwe Kleine-König | b595076 | 2010-11-01 15:38:34 -0400 | [diff] [blame] | 2963 | * e1000_get_phy_addr_for_hv_page - Get PHY address based on page |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2964 | * @page: page to be accessed |
| 2965 | **/ |
| 2966 | static u32 e1000_get_phy_addr_for_hv_page(u32 page) |
| 2967 | { |
| 2968 | u32 phy_addr = 2; |
| 2969 | |
| 2970 | if (page >= HV_INTC_FC_PAGE_START) |
| 2971 | phy_addr = 1; |
| 2972 | |
| 2973 | return phy_addr; |
| 2974 | } |
| 2975 | |
| 2976 | /** |
| 2977 | * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers |
| 2978 | * @hw: pointer to the HW structure |
| 2979 | * @offset: register offset to be read or written |
| 2980 | * @data: pointer to the data to be read or written |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2981 | * @read: determines if operation is read or write |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2982 | * |
Bruce Allan | 5ccdcec | 2009-10-26 11:24:02 +0000 | [diff] [blame] | 2983 | * Reads the PHY register at offset and stores the retreived information |
| 2984 | * in data. Assumes semaphore already acquired. Note that the procedure |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 2985 | * to access these regs uses the address port and data port to read/write. |
| 2986 | * These accesses done with PHY address 2 and without using pages. |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2987 | **/ |
| 2988 | static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, |
Bruce Allan | 66501f5 | 2013-02-20 04:05:55 +0000 | [diff] [blame] | 2989 | u16 *data, bool read) |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2990 | { |
| 2991 | s32 ret_val; |
Bruce Allan | 70806a7 | 2013-01-05 05:08:37 +0000 | [diff] [blame] | 2992 | u32 addr_reg; |
| 2993 | u32 data_reg; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2994 | |
| 2995 | /* This takes care of the difference with desktop vs mobile phy */ |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 2996 | addr_reg = ((hw->phy.type == e1000_phy_82578) ? |
| 2997 | I82578_ADDR_REG : I82577_ADDR_REG); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2998 | data_reg = addr_reg + 1; |
| 2999 | |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3000 | /* All operations in this function are phy address 2 */ |
| 3001 | hw->phy.addr = 2; |
| 3002 | |
| 3003 | /* masking with 0x3F to remove the page from offset */ |
| 3004 | ret_val = e1000e_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F); |
| 3005 | if (ret_val) { |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 3006 | e_dbg("Could not write the Address Offset port register\n"); |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 3007 | return ret_val; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3008 | } |
| 3009 | |
| 3010 | /* Read or write the data value next */ |
| 3011 | if (read) |
| 3012 | ret_val = e1000e_read_phy_reg_mdic(hw, data_reg, data); |
| 3013 | else |
| 3014 | ret_val = e1000e_write_phy_reg_mdic(hw, data_reg, *data); |
| 3015 | |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 3016 | if (ret_val) |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 3017 | e_dbg("Could not access the Data port register\n"); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3018 | |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3019 | return ret_val; |
| 3020 | } |
| 3021 | |
| 3022 | /** |
| 3023 | * e1000_link_stall_workaround_hv - Si workaround |
| 3024 | * @hw: pointer to the HW structure |
| 3025 | * |
| 3026 | * This function works around a Si bug where the link partner can get |
| 3027 | * a link up indication before the PHY does. If small packets are sent |
| 3028 | * by the link partner they can be placed in the packet buffer without |
| 3029 | * being properly accounted for by the PHY and will stall preventing |
| 3030 | * further packets from being received. The workaround is to clear the |
| 3031 | * packet buffer after the PHY detects link up. |
| 3032 | **/ |
| 3033 | s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw) |
| 3034 | { |
| 3035 | s32 ret_val = 0; |
| 3036 | u16 data; |
| 3037 | |
| 3038 | if (hw->phy.type != e1000_phy_82578) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 3039 | return 0; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3040 | |
Bruce Allan | e65fa87 | 2009-07-01 13:27:31 +0000 | [diff] [blame] | 3041 | /* Do not apply workaround if in PHY loopback bit 14 set */ |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 3042 | e1e_rphy(hw, MII_BMCR, &data); |
| 3043 | if (data & BMCR_LOOPBACK) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 3044 | return 0; |
Bruce Allan | e65fa87 | 2009-07-01 13:27:31 +0000 | [diff] [blame] | 3045 | |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3046 | /* check if link is up and at 1Gbps */ |
Bruce Allan | 482fed8 | 2011-01-06 14:29:49 +0000 | [diff] [blame] | 3047 | ret_val = e1e_rphy(hw, BM_CS_STATUS, &data); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3048 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 3049 | return ret_val; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3050 | |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 3051 | data &= (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED | |
| 3052 | BM_CS_STATUS_SPEED_MASK); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3053 | |
Bruce Allan | 3d3a167 | 2012-02-23 03:13:18 +0000 | [diff] [blame] | 3054 | if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED | |
| 3055 | BM_CS_STATUS_SPEED_1000)) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 3056 | return 0; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3057 | |
Bruce Allan | bb9c5ee | 2012-02-23 03:31:29 +0000 | [diff] [blame] | 3058 | msleep(200); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3059 | |
| 3060 | /* flush the packets in the fifo buffer */ |
Bruce Allan | c063f60 | 2013-01-12 07:27:53 +0000 | [diff] [blame] | 3061 | ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL, |
| 3062 | (HV_MUX_DATA_CTRL_GEN_TO_MAC | |
| 3063 | HV_MUX_DATA_CTRL_FORCE_SPEED)); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3064 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 3065 | return ret_val; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3066 | |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 3067 | return e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3068 | } |
| 3069 | |
| 3070 | /** |
| 3071 | * e1000_check_polarity_82577 - Checks the polarity. |
| 3072 | * @hw: pointer to the HW structure |
| 3073 | * |
| 3074 | * Success returns 0, Failure returns -E1000_ERR_PHY (-2) |
| 3075 | * |
| 3076 | * Polarity is determined based on the PHY specific status register. |
| 3077 | **/ |
| 3078 | s32 e1000_check_polarity_82577(struct e1000_hw *hw) |
| 3079 | { |
| 3080 | struct e1000_phy_info *phy = &hw->phy; |
| 3081 | s32 ret_val; |
| 3082 | u16 data; |
| 3083 | |
Bruce Allan | 482fed8 | 2011-01-06 14:29:49 +0000 | [diff] [blame] | 3084 | ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3085 | |
| 3086 | if (!ret_val) |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 3087 | phy->cable_polarity = ((data & I82577_PHY_STATUS2_REV_POLARITY) |
| 3088 | ? e1000_rev_polarity_reversed |
| 3089 | : e1000_rev_polarity_normal); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3090 | |
| 3091 | return ret_val; |
| 3092 | } |
| 3093 | |
| 3094 | /** |
| 3095 | * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY |
| 3096 | * @hw: pointer to the HW structure |
| 3097 | * |
Bruce Allan | eab50ff | 2010-05-10 15:01:30 +0000 | [diff] [blame] | 3098 | * Calls the PHY setup function to force speed and duplex. |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3099 | **/ |
| 3100 | s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw) |
| 3101 | { |
| 3102 | struct e1000_phy_info *phy = &hw->phy; |
| 3103 | s32 ret_val; |
| 3104 | u16 phy_data; |
| 3105 | bool link; |
| 3106 | |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 3107 | ret_val = e1e_rphy(hw, MII_BMCR, &phy_data); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3108 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 3109 | return ret_val; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3110 | |
| 3111 | e1000e_phy_force_speed_duplex_setup(hw, &phy_data); |
| 3112 | |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 3113 | ret_val = e1e_wphy(hw, MII_BMCR, phy_data); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3114 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 3115 | return ret_val; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3116 | |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3117 | udelay(1); |
| 3118 | |
| 3119 | if (phy->autoneg_wait_to_complete) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 3120 | e_dbg("Waiting for forced speed/duplex link on 82577 phy\n"); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3121 | |
Bruce Allan | 3d3a167 | 2012-02-23 03:13:18 +0000 | [diff] [blame] | 3122 | ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, |
| 3123 | 100000, &link); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3124 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 3125 | return ret_val; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3126 | |
| 3127 | if (!link) |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 3128 | e_dbg("Link taking longer than expected.\n"); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3129 | |
| 3130 | /* Try once more */ |
Bruce Allan | 3d3a167 | 2012-02-23 03:13:18 +0000 | [diff] [blame] | 3131 | ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, |
| 3132 | 100000, &link); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3133 | } |
| 3134 | |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3135 | return ret_val; |
| 3136 | } |
| 3137 | |
| 3138 | /** |
| 3139 | * e1000_get_phy_info_82577 - Retrieve I82577 PHY information |
| 3140 | * @hw: pointer to the HW structure |
| 3141 | * |
| 3142 | * Read PHY status to determine if link is up. If link is up, then |
| 3143 | * set/determine 10base-T extended distance and polarity correction. Read |
| 3144 | * PHY port status to determine MDI/MDIx and speed. Based on the speed, |
| 3145 | * determine on the cable length, local and remote receiver. |
| 3146 | **/ |
| 3147 | s32 e1000_get_phy_info_82577(struct e1000_hw *hw) |
| 3148 | { |
| 3149 | struct e1000_phy_info *phy = &hw->phy; |
| 3150 | s32 ret_val; |
| 3151 | u16 data; |
| 3152 | bool link; |
| 3153 | |
| 3154 | ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); |
| 3155 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 3156 | return ret_val; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3157 | |
| 3158 | if (!link) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 3159 | e_dbg("Phy info is only valid if link is up\n"); |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 3160 | return -E1000_ERR_CONFIG; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3161 | } |
| 3162 | |
| 3163 | phy->polarity_correction = true; |
| 3164 | |
| 3165 | ret_val = e1000_check_polarity_82577(hw); |
| 3166 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 3167 | return ret_val; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3168 | |
Bruce Allan | 482fed8 | 2011-01-06 14:29:49 +0000 | [diff] [blame] | 3169 | ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3170 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 3171 | return ret_val; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3172 | |
Bruce Allan | 04499ec | 2012-04-13 00:08:31 +0000 | [diff] [blame] | 3173 | phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3174 | |
| 3175 | if ((data & I82577_PHY_STATUS2_SPEED_MASK) == |
| 3176 | I82577_PHY_STATUS2_SPEED_1000MBPS) { |
| 3177 | ret_val = hw->phy.ops.get_cable_length(hw); |
| 3178 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 3179 | return ret_val; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3180 | |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 3181 | ret_val = e1e_rphy(hw, MII_STAT1000, &data); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3182 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 3183 | return ret_val; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3184 | |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 3185 | phy->local_rx = (data & LPA_1000LOCALRXOK) |
| 3186 | ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3187 | |
Bruce Allan | c2ade1a | 2013-01-16 08:54:35 +0000 | [diff] [blame] | 3188 | phy->remote_rx = (data & LPA_1000REMRXOK) |
| 3189 | ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3190 | } else { |
| 3191 | phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; |
| 3192 | phy->local_rx = e1000_1000t_rx_status_undefined; |
| 3193 | phy->remote_rx = e1000_1000t_rx_status_undefined; |
| 3194 | } |
| 3195 | |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 3196 | return 0; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3197 | } |
| 3198 | |
| 3199 | /** |
| 3200 | * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY |
| 3201 | * @hw: pointer to the HW structure |
| 3202 | * |
| 3203 | * Reads the diagnostic status register and verifies result is valid before |
| 3204 | * placing it in the phy_cable_length field. |
| 3205 | **/ |
| 3206 | s32 e1000_get_cable_length_82577(struct e1000_hw *hw) |
| 3207 | { |
| 3208 | struct e1000_phy_info *phy = &hw->phy; |
| 3209 | s32 ret_val; |
| 3210 | u16 phy_data, length; |
| 3211 | |
Bruce Allan | 482fed8 | 2011-01-06 14:29:49 +0000 | [diff] [blame] | 3212 | ret_val = e1e_rphy(hw, I82577_PHY_DIAG_STATUS, &phy_data); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3213 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 3214 | return ret_val; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3215 | |
Bruce Allan | f0ff439 | 2013-02-20 04:05:39 +0000 | [diff] [blame] | 3216 | length = ((phy_data & I82577_DSTATUS_CABLE_LENGTH) >> |
| 3217 | I82577_DSTATUS_CABLE_LENGTH_SHIFT); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3218 | |
| 3219 | if (length == E1000_CABLE_LENGTH_UNDEFINED) |
Bruce Allan | 7dbbe5d | 2013-01-05 05:08:31 +0000 | [diff] [blame] | 3220 | return -E1000_ERR_PHY; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3221 | |
| 3222 | phy->cable_length = length; |
| 3223 | |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 3224 | return 0; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3225 | } |