Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2014 Advanced Micro Devices, Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | */ |
| 23 | |
| 24 | #ifndef __AMDGPU_IRQ_H__ |
| 25 | #define __AMDGPU_IRQ_H__ |
| 26 | |
Alex Deucher | 5f23236 | 2015-11-06 01:29:08 -0500 | [diff] [blame] | 27 | #include <linux/irqdomain.h> |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 28 | #include "amdgpu_ih.h" |
| 29 | |
| 30 | #define AMDGPU_MAX_IRQ_SRC_ID 0x100 |
Alex Deucher | d766e6a | 2016-03-29 18:28:50 -0400 | [diff] [blame] | 31 | #define AMDGPU_MAX_IRQ_CLIENT_ID 0x100 |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 32 | |
| 33 | struct amdgpu_device; |
| 34 | struct amdgpu_iv_entry; |
| 35 | |
| 36 | enum amdgpu_interrupt_state { |
| 37 | AMDGPU_IRQ_STATE_DISABLE, |
| 38 | AMDGPU_IRQ_STATE_ENABLE, |
| 39 | }; |
| 40 | |
| 41 | struct amdgpu_irq_src { |
| 42 | unsigned num_types; |
| 43 | atomic_t *enabled_types; |
| 44 | const struct amdgpu_irq_src_funcs *funcs; |
Alex Deucher | 0cf3be2 | 2015-07-28 14:24:53 -0400 | [diff] [blame] | 45 | void *data; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 46 | }; |
| 47 | |
Alex Deucher | d766e6a | 2016-03-29 18:28:50 -0400 | [diff] [blame] | 48 | struct amdgpu_irq_client { |
| 49 | struct amdgpu_irq_src **sources; |
| 50 | }; |
| 51 | |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 52 | /* provided by interrupt generating IP blocks */ |
| 53 | struct amdgpu_irq_src_funcs { |
| 54 | int (*set)(struct amdgpu_device *adev, struct amdgpu_irq_src *source, |
| 55 | unsigned type, enum amdgpu_interrupt_state state); |
| 56 | |
| 57 | int (*process)(struct amdgpu_device *adev, |
| 58 | struct amdgpu_irq_src *source, |
| 59 | struct amdgpu_iv_entry *entry); |
| 60 | }; |
| 61 | |
| 62 | struct amdgpu_irq { |
| 63 | bool installed; |
| 64 | spinlock_t lock; |
| 65 | /* interrupt sources */ |
Alex Deucher | d766e6a | 2016-03-29 18:28:50 -0400 | [diff] [blame] | 66 | struct amdgpu_irq_client client[AMDGPU_IH_CLIENTID_MAX]; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 67 | |
| 68 | /* status, etc. */ |
| 69 | bool msi_enabled; /* msi enabled */ |
| 70 | |
| 71 | /* interrupt ring */ |
| 72 | struct amdgpu_ih_ring ih; |
| 73 | const struct amdgpu_ih_funcs *ih_funcs; |
Alex Deucher | 5f23236 | 2015-11-06 01:29:08 -0500 | [diff] [blame] | 74 | |
| 75 | /* gen irq stuff */ |
| 76 | struct irq_domain *domain; /* GPU irq controller domain */ |
| 77 | unsigned virq[AMDGPU_MAX_IRQ_SRC_ID]; |
Chunming Zhou | 1015a1b | 2016-07-18 17:02:57 +0800 | [diff] [blame] | 78 | uint32_t srbm_soft_reset; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 79 | }; |
| 80 | |
| 81 | void amdgpu_irq_preinstall(struct drm_device *dev); |
| 82 | int amdgpu_irq_postinstall(struct drm_device *dev); |
| 83 | void amdgpu_irq_uninstall(struct drm_device *dev); |
| 84 | irqreturn_t amdgpu_irq_handler(int irq, void *arg); |
| 85 | |
| 86 | int amdgpu_irq_init(struct amdgpu_device *adev); |
| 87 | void amdgpu_irq_fini(struct amdgpu_device *adev); |
Alex Deucher | d766e6a | 2016-03-29 18:28:50 -0400 | [diff] [blame] | 88 | int amdgpu_irq_add_id(struct amdgpu_device *adev, |
| 89 | unsigned client_id, unsigned src_id, |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 90 | struct amdgpu_irq_src *source); |
| 91 | void amdgpu_irq_dispatch(struct amdgpu_device *adev, |
| 92 | struct amdgpu_iv_entry *entry); |
| 93 | int amdgpu_irq_update(struct amdgpu_device *adev, struct amdgpu_irq_src *src, |
| 94 | unsigned type); |
| 95 | int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src, |
| 96 | unsigned type); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 97 | int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src, |
| 98 | unsigned type); |
| 99 | bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src, |
| 100 | unsigned type); |
Chunming Zhou | 0eaeb07 | 2016-06-16 16:54:53 +0800 | [diff] [blame] | 101 | void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 102 | |
Alex Deucher | 5f23236 | 2015-11-06 01:29:08 -0500 | [diff] [blame] | 103 | int amdgpu_irq_add_domain(struct amdgpu_device *adev); |
| 104 | void amdgpu_irq_remove_domain(struct amdgpu_device *adev); |
| 105 | unsigned amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned src_id); |
| 106 | |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 107 | #endif |