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gerrit-public.fairphone.software / kernel / msm-4.19 / 54174a33da64536d6840ffa5ae9edc71cb9bf3a1 / . / arch / arm / boot / dts / tegra30.dtsi
blob: e9792ac036358af1d8c5be4fe3f14f45f0bbe7c1 [file] [log] [blame]
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]1/include/ "skeleton.dtsi"
2
3/ {
4 compatible = "nvidia,tegra30";
5 interrupt-parent = <&intc>;
6
Stephen Warrend17adfd2012-01-25 14:43:27 -0700[diff] [blame]7 pmc@7000f400 {
8 compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
9 reg = <0x7000e400 0x400>;
10 };
11
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]12 intc: interrupt-controller@50041000 {
13 compatible = "arm,cortex-a9-gic";
14 interrupt-controller;
15 #interrupt-cells = <3>;
16 reg = < 0x50041000 0x1000 >,
17 < 0x50040100 0x0100 >;
18 };
19
Stephen Warren583553b2012-02-27 18:26:36 -0700[diff] [blame]20 pmu {
21 compatible = "arm,cortex-a9-pmu";
22 interrupts = <0 144 0x04
23 0 145 0x04
24 0 146 0x04
25 0 147 0x04>;
26 };
27
Stephen Warren8051b752012-01-11 16:09:54 -0700[diff] [blame]28 apbdma: dma@6000a000 {
29 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
30 reg = <0x6000a000 0x1400>;
31 interrupts = < 0 104 0x04
32 0 105 0x04
33 0 106 0x04
34 0 107 0x04
35 0 108 0x04
36 0 109 0x04
37 0 110 0x04
38 0 111 0x04
39 0 112 0x04
40 0 113 0x04
41 0 114 0x04
42 0 115 0x04
43 0 116 0x04
44 0 117 0x04
45 0 118 0x04
46 0 119 0x04
47 0 128 0x04
48 0 129 0x04
49 0 130 0x04
50 0 131 0x04
51 0 132 0x04
52 0 133 0x04
53 0 134 0x04
54 0 135 0x04
55 0 136 0x04
56 0 137 0x04
57 0 138 0x04
58 0 139 0x04
59 0 140 0x04
60 0 141 0x04
61 0 142 0x04
62 0 143 0x04 >;
63 };
64
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]65 i2c@7000c000 {
66 #address-cells = <1>;
67 #size-cells = <0>;
68 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
69 reg = <0x7000C000 0x100>;
70 interrupts = < 0 38 0x04 >;
71 };
72
73 i2c@7000c400 {
74 #address-cells = <1>;
75 #size-cells = <0>;
76 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
77 reg = <0x7000C400 0x100>;
78 interrupts = < 0 84 0x04 >;
79 };
80
81 i2c@7000c500 {
82 #address-cells = <1>;
83 #size-cells = <0>;
84 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
85 reg = <0x7000C500 0x100>;
86 interrupts = < 0 92 0x04 >;
87 };
88
89 i2c@7000c700 {
90 #address-cells = <1>;
91 #size-cells = <0>;
92 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
93 reg = <0x7000c700 0x100>;
94 interrupts = < 0 120 0x04 >;
95 };
96
97 i2c@7000d000 {
98 #address-cells = <1>;
99 #size-cells = <0>;
100 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
101 reg = <0x7000D000 0x100>;
102 interrupts = < 0 53 0x04 >;
103 };
104
105 gpio: gpio@6000d000 {
106 compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio";
107 reg = < 0x6000d000 0x1000 >;
Stephen Warren636e50a2012-01-04 08:39:35 +0000[diff] [blame]108 interrupts = < 0 32 0x04
109 0 33 0x04
110 0 34 0x04
111 0 35 0x04
112 0 55 0x04
113 0 87 0x04
Stephen Warrenf8196b02012-01-04 08:39:36 +0000[diff] [blame]114 0 89 0x04
115 0 125 0x04 >;
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]116 #gpio-cells = <2>;
117 gpio-controller;
Stephen Warren6f74dc92012-01-04 08:39:37 +0000[diff] [blame]118 #interrupt-cells = <2>;
119 interrupt-controller;
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]120 };
121
122 serial@70006000 {
123 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
124 reg = <0x70006000 0x40>;
125 reg-shift = <2>;
126 interrupts = < 0 36 0x04 >;
127 };
128
129 serial@70006040 {
130 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
131 reg = <0x70006040 0x40>;
132 reg-shift = <2>;
133 interrupts = < 0 37 0x04 >;
134 };
135
136 serial@70006200 {
137 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
138 reg = <0x70006200 0x100>;
139 reg-shift = <2>;
140 interrupts = < 0 46 0x04 >;
141 };
142
143 serial@70006300 {
144 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
145 reg = <0x70006300 0x100>;
146 reg-shift = <2>;
147 interrupts = < 0 90 0x04 >;
148 };
149
150 serial@70006400 {
151 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
152 reg = <0x70006400 0x100>;
153 reg-shift = <2>;
154 interrupts = < 0 91 0x04 >;
155 };
156
157 sdhci@78000000 {
158 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
159 reg = <0x78000000 0x200>;
160 interrupts = < 0 14 0x04 >;
161 };
162
163 sdhci@78000200 {
164 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
165 reg = <0x78000200 0x200>;
166 interrupts = < 0 15 0x04 >;
167 };
168
169 sdhci@78000400 {
170 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
171 reg = <0x78000400 0x200>;
172 interrupts = < 0 19 0x04 >;
173 };
174
175 sdhci@78000600 {
176 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
177 reg = <0x78000600 0x200>;
178 interrupts = < 0 31 0x04 >;
179 };
180
181 pinmux: pinmux@70000000 {
182 compatible = "nvidia,tegra30-pinmux";
183 reg = < 0x70000868 0xd0 /* Pad control registers */
184 0x70003000 0x3e0 >; /* Mux registers */
185 };
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]186
187 ahub {
188 compatible = "nvidia,tegra30-ahub";
189 reg = <0x70080000 0x200 0x70080200 0x100>;
190 interrupts = < 0 103 0x04 >;
191 nvidia,dma-request-selector = <&apbdma 1>;
192
193 ranges;
194 #address-cells = <1>;
195 #size-cells = <1>;
196
197 tegra_i2s0: i2s@70080300 {
198 compatible = "nvidia,tegra30-i2s";
199 reg = <0x70080300 0x100>;
200 nvidia,ahub-cif-ids = <4 4>;
201 };
202
203 tegra_i2s1: i2s@70080400 {
204 compatible = "nvidia,tegra30-i2s";
205 reg = <0x70080400 0x100>;
206 nvidia,ahub-cif-ids = <5 5>;
207 };
208
209 tegra_i2s2: i2s@70080500 {
210 compatible = "nvidia,tegra30-i2s";
211 reg = <0x70080500 0x100>;
212 nvidia,ahub-cif-ids = <6 6>;
213 };
214
215 tegra_i2s3: i2s@70080600 {
216 compatible = "nvidia,tegra30-i2s";
217 reg = <0x70080600 0x100>;
218 nvidia,ahub-cif-ids = <7 7>;
219 };
220
221 tegra_i2s4: i2s@70080700 {
222 compatible = "nvidia,tegra30-i2s";
223 reg = <0x70080700 0x100>;
224 nvidia,ahub-cif-ids = <8 8>;
225 };
226 };
Hiroshi DOYU7868a9b2012-05-07 09:43:47 +0300[diff] [blame]227
228 ahb: ahb@6000c004 {
229 compatible = "nvidia,tegra30-ahb";
230 reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
231 };
hdoyu@nvidia.comecf43742012-05-09 21:42:33 +0000[diff] [blame]232
233 mc {
234 compatible = "nvidia,tegra30-mc";
235 reg = <0x7000f000 0x010
236 0x7000f03c 0x1b4
237 0x7000f200 0x028
238 0x7000f284 0x17c>;
239 interrupts = <0 77 0x04>;
240 };
hdoyu@nvidia.com54174a32012-05-09 21:50:21 +0000[diff] [blame^]241
242 smmu {
243 compatible = "nvidia,tegra30-smmu";
244 reg = <0x7000f010 0x02c
245 0x7000f1f0 0x010
246 0x7000f228 0x05c>;
247 nvidia,#asids = <4>; /* # of ASIDs */
248 dma-window = <0 0x40000000>; /* IOVA start & length */
249 nvidia,ahb = <&ahb>;
250 };
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]251};