blob: b58e1afdda7697e9a2e094c3f07bacc8a1621699 [file] [log] [blame]
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
Jerome Glisse771fe6b2009-06-05 14:42:42 +020031/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
Jerome Glissed39c3b82009-09-28 18:34:43 +020045/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
Arun Sharma600634972011-07-26 16:09:06 -070063#include <linux/atomic.h>
Jerome Glisse771fe6b2009-06-05 14:42:42 +020064#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
67
Jerome Glisse4c788672009-11-20 14:29:23 +010068#include <ttm/ttm_bo_api.h>
69#include <ttm/ttm_bo_driver.h>
70#include <ttm/ttm_placement.h>
71#include <ttm/ttm_module.h>
Thomas Hellstrom147666f2010-11-17 12:38:32 +000072#include <ttm/ttm_execbuf_util.h>
Jerome Glisse4c788672009-11-20 14:29:23 +010073
Dave Airliec2142712009-09-22 08:50:10 +100074#include "radeon_family.h"
Jerome Glisse771fe6b2009-06-05 14:42:42 +020075#include "radeon_mode.h"
76#include "radeon_reg.h"
Jerome Glisse771fe6b2009-06-05 14:42:42 +020077
78/*
79 * Modules parameters.
80 */
81extern int radeon_no_wb;
82extern int radeon_modeset;
83extern int radeon_dynclks;
84extern int radeon_r4xx_atom;
85extern int radeon_agpmode;
86extern int radeon_vram_limit;
87extern int radeon_gart_size;
88extern int radeon_benchmarking;
Michel Dänzerecc0b322009-07-21 11:23:57 +020089extern int radeon_testing;
Jerome Glisse771fe6b2009-06-05 14:42:42 +020090extern int radeon_connector_table;
Dave Airlie4ce001a2009-08-13 16:32:14 +100091extern int radeon_tv;
Christian Koenigdafc3bd2009-10-11 23:49:13 +020092extern int radeon_audio;
Alex Deucherf46c0122010-03-31 00:33:27 -040093extern int radeon_disp_priority;
Alex Deuchere2b0a8e2010-03-17 02:07:37 -040094extern int radeon_hw_i2c;
Alex Deucherd42dd572011-01-12 20:05:11 -050095extern int radeon_pcie_gen2;
Alex Deuchera18cee12011-11-01 14:20:30 -040096extern int radeon_msi;
Christian König3368ff02012-05-02 15:11:21 +020097extern int radeon_lockup_timeout;
Samuel Lia0a53aa2013-04-08 17:25:47 -040098extern int radeon_fastfb;
Alex Deucherda321c82013-04-12 13:55:22 -040099extern int radeon_dpm;
Alex Deucher1294d4a2013-07-16 15:58:50 -0400100extern int radeon_aspm;
Dave Airlie10ebc0b2012-09-17 14:40:31 +1000101extern int radeon_runtime_pm;
Alex Deucher363eb0b2014-01-08 17:55:08 -0500102extern int radeon_hard_reset;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200103
104/*
105 * Copy from radeon_drv.h so we don't have to include both and have conflicting
106 * symbol;
107 */
Jerome Glissebb635562012-05-09 15:34:46 +0200108#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
109#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
Jerome Glissee8217672010-02-15 21:36:13 +0100110/* RADEON_IB_POOL_SIZE must be a power of 2 */
Jerome Glissebb635562012-05-09 15:34:46 +0200111#define RADEON_IB_POOL_SIZE 16
112#define RADEON_DEBUGFS_MAX_COMPONENTS 32
113#define RADEONFB_CONN_LIMIT 4
114#define RADEON_BIOS_NUM_SCRATCH 8
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200115
Jerome Glissebb635562012-05-09 15:34:46 +0200116/* fence seq are set to this number when signaled */
117#define RADEON_FENCE_SIGNALED_SEQ 0LL
Alex Deucher1b370782011-11-17 20:13:28 -0500118
119/* internal ring indices */
120/* r1xx+ has gfx CP ring */
Christian Königd93f7932013-05-23 12:10:04 +0200121#define RADEON_RING_TYPE_GFX_INDEX 0
Alex Deucher1b370782011-11-17 20:13:28 -0500122
123/* cayman has 2 compute CP rings */
Christian Königd93f7932013-05-23 12:10:04 +0200124#define CAYMAN_RING_TYPE_CP1_INDEX 1
125#define CAYMAN_RING_TYPE_CP2_INDEX 2
Alex Deucher1b370782011-11-17 20:13:28 -0500126
Alex Deucher4d756582012-09-27 15:08:35 -0400127/* R600+ has an async dma ring */
128#define R600_RING_TYPE_DMA_INDEX 3
Alex Deucherf60cbd12012-12-04 15:27:33 -0500129/* cayman add a second async dma ring */
130#define CAYMAN_RING_TYPE_DMA1_INDEX 4
Alex Deucher4d756582012-09-27 15:08:35 -0400131
Christian Königf2ba57b2013-04-08 12:41:29 +0200132/* R600+ */
Christian Königd93f7932013-05-23 12:10:04 +0200133#define R600_RING_TYPE_UVD_INDEX 5
134
135/* TN+ */
136#define TN_RING_TYPE_VCE1_INDEX 6
137#define TN_RING_TYPE_VCE2_INDEX 7
138
139/* max number of rings */
140#define RADEON_NUM_RINGS 8
Christian Königf2ba57b2013-04-08 12:41:29 +0200141
Christian König1c61eae2014-02-18 01:50:22 -0700142/* number of hw syncs before falling back on blocking */
143#define RADEON_NUM_SYNCS 4
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200144
Christian König8f534922014-02-18 11:37:20 +0100145/* number of hw syncs before falling back on blocking */
146#define RADEON_NUM_SYNCS 4
147
Jerome Glisse721604a2012-01-05 22:11:05 -0500148/* hardcode those limit for now */
Christian Königca19f212012-09-11 16:09:59 +0200149#define RADEON_VA_IB_OFFSET (1 << 20)
Jerome Glissebb635562012-05-09 15:34:46 +0200150#define RADEON_VA_RESERVED_SIZE (8 << 20)
151#define RADEON_IB_VM_MAX_SIZE (64 << 10)
Jerome Glisse721604a2012-01-05 22:11:05 -0500152
Alex Deucher1a0041b2013-10-02 13:01:36 -0400153/* hard reset data */
154#define RADEON_ASIC_RESET_DATA 0x39d5e86b
155
Alex Deucherec46c762013-01-03 12:07:30 -0500156/* reset flags */
157#define RADEON_RESET_GFX (1 << 0)
158#define RADEON_RESET_COMPUTE (1 << 1)
159#define RADEON_RESET_DMA (1 << 2)
Alex Deucher9ff07442013-01-18 12:18:17 -0500160#define RADEON_RESET_CP (1 << 3)
161#define RADEON_RESET_GRBM (1 << 4)
162#define RADEON_RESET_DMA1 (1 << 5)
163#define RADEON_RESET_RLC (1 << 6)
164#define RADEON_RESET_SEM (1 << 7)
165#define RADEON_RESET_IH (1 << 8)
166#define RADEON_RESET_VMC (1 << 9)
167#define RADEON_RESET_MC (1 << 10)
168#define RADEON_RESET_DISPLAY (1 << 11)
Alex Deucherec46c762013-01-03 12:07:30 -0500169
Alex Deucher22c775c2013-07-23 09:41:05 -0400170/* CG block flags */
171#define RADEON_CG_BLOCK_GFX (1 << 0)
172#define RADEON_CG_BLOCK_MC (1 << 1)
173#define RADEON_CG_BLOCK_SDMA (1 << 2)
174#define RADEON_CG_BLOCK_UVD (1 << 3)
175#define RADEON_CG_BLOCK_VCE (1 << 4)
176#define RADEON_CG_BLOCK_HDP (1 << 5)
Alex Deuchere16866e2013-08-08 19:34:07 -0400177#define RADEON_CG_BLOCK_BIF (1 << 6)
Alex Deucher22c775c2013-07-23 09:41:05 -0400178
Alex Deucher64d8a722013-08-08 16:31:25 -0400179/* CG flags */
180#define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
181#define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
182#define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
183#define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
184#define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
185#define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
186#define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
187#define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
188#define RADEON_CG_SUPPORT_MC_LS (1 << 8)
189#define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
190#define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
191#define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
192#define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
193#define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
194#define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
195#define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
196#define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
197
198/* PG flags */
Alex Deucher2b19d172013-09-04 16:58:29 -0400199#define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
Alex Deucher64d8a722013-08-08 16:31:25 -0400200#define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
201#define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
202#define RADEON_PG_SUPPORT_UVD (1 << 3)
203#define RADEON_PG_SUPPORT_VCE (1 << 4)
204#define RADEON_PG_SUPPORT_CP (1 << 5)
205#define RADEON_PG_SUPPORT_GDS (1 << 6)
206#define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
207#define RADEON_PG_SUPPORT_SDMA (1 << 8)
208#define RADEON_PG_SUPPORT_ACP (1 << 9)
209#define RADEON_PG_SUPPORT_SAMU (1 << 10)
210
Alex Deucher9e05fa12013-01-24 10:06:33 -0500211/* max cursor sizes (in pixels) */
212#define CURSOR_WIDTH 64
213#define CURSOR_HEIGHT 64
214
215#define CIK_CURSOR_WIDTH 128
216#define CIK_CURSOR_HEIGHT 128
217
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200218/*
219 * Errata workarounds.
220 */
221enum radeon_pll_errata {
222 CHIP_ERRATA_R300_CG = 0x00000001,
223 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
224 CHIP_ERRATA_PLL_DELAY = 0x00000004
225};
226
227
228struct radeon_device;
229
230
231/*
232 * BIOS.
233 */
234bool radeon_get_bios(struct radeon_device *rdev);
235
Jerome Glisse9fc04b52012-01-23 11:52:15 -0500236/*
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000237 * Dummy page
238 */
239struct radeon_dummy_page {
240 struct page *page;
241 dma_addr_t addr;
242};
243int radeon_dummy_page_init(struct radeon_device *rdev);
244void radeon_dummy_page_fini(struct radeon_device *rdev);
245
246
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200247/*
248 * Clocks
249 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200250struct radeon_clock {
251 struct radeon_pll p1pll;
252 struct radeon_pll p2pll;
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500253 struct radeon_pll dcpll;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200254 struct radeon_pll spll;
255 struct radeon_pll mpll;
256 /* 10 Khz units */
257 uint32_t default_mclk;
258 uint32_t default_sclk;
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500259 uint32_t default_dispclk;
Alex Deucher4489cd622013-03-22 15:59:10 -0400260 uint32_t current_dispclk;
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500261 uint32_t dp_extclk;
Alex Deucherb20f9be2011-06-08 13:01:11 -0400262 uint32_t max_pixel_clock;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200263};
264
Rafał Miłecki74338742009-11-03 00:53:02 +0100265/*
266 * Power management
267 */
268int radeon_pm_init(struct radeon_device *rdev);
Alex Deucher914a8982013-12-19 11:37:22 -0500269int radeon_pm_late_init(struct radeon_device *rdev);
Alex Deucher29fb52c2010-03-11 10:01:17 -0500270void radeon_pm_fini(struct radeon_device *rdev);
Rafał Miłeckic913e232009-12-22 23:02:16 +0100271void radeon_pm_compute_clocks(struct radeon_device *rdev);
Alex Deucherce8f5372010-05-07 15:10:16 -0400272void radeon_pm_suspend(struct radeon_device *rdev);
273void radeon_pm_resume(struct radeon_device *rdev);
Alex Deucher56278a82009-12-28 13:58:44 -0500274void radeon_combios_get_power_modes(struct radeon_device *rdev);
275void radeon_atombios_get_power_modes(struct radeon_device *rdev);
Christian König7062ab62013-04-08 12:41:31 +0200276int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
277 u8 clock_type,
278 u32 clock,
279 bool strobe_mode,
280 struct atom_clock_dividers *dividers);
Alex Deuchereaa778a2013-02-13 16:38:25 -0500281int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
282 u32 clock,
283 bool strobe_mode,
284 struct atom_mpll_param *mpll_param);
Alex Deucher8a83ec52011-04-12 14:49:23 -0400285void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
Alex Deucherae5b0ab2013-06-24 10:50:34 -0400286int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
287 u16 voltage_level, u8 voltage_type,
288 u32 *gpio_value, u32 *gpio_mask);
289void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
290 u32 eng_clock, u32 mem_clock);
291int radeon_atom_get_voltage_step(struct radeon_device *rdev,
292 u8 voltage_type, u16 *voltage_step);
Alex Deucher4a6369e2013-04-12 14:04:10 -0400293int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
294 u16 voltage_id, u16 *voltage);
Alex Deucherbeb79f42013-02-19 17:14:43 -0500295int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
296 u16 *voltage,
297 u16 leakage_idx);
Alex Deuchercc8dbbb2013-08-14 01:03:41 -0400298int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
299 u16 *leakage_id);
300int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
301 u16 *vddc, u16 *vddci,
302 u16 virtual_voltage_id,
303 u16 vbios_voltage_id);
Alex Deucherae5b0ab2013-06-24 10:50:34 -0400304int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
305 u8 voltage_type,
306 u16 nominal_voltage,
307 u16 *true_voltage);
308int radeon_atom_get_min_voltage(struct radeon_device *rdev,
309 u8 voltage_type, u16 *min_voltage);
310int radeon_atom_get_max_voltage(struct radeon_device *rdev,
311 u8 voltage_type, u16 *max_voltage);
312int radeon_atom_get_voltage_table(struct radeon_device *rdev,
Alex Deucher65171942013-02-13 17:29:54 -0500313 u8 voltage_type, u8 voltage_mode,
Alex Deucherae5b0ab2013-06-24 10:50:34 -0400314 struct atom_voltage_table *voltage_table);
Alex Deucher58653ab2013-02-13 17:04:59 -0500315bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
316 u8 voltage_type, u8 voltage_mode);
Alex Deucherae5b0ab2013-06-24 10:50:34 -0400317void radeon_atom_update_memory_dll(struct radeon_device *rdev,
318 u32 mem_clock);
319void radeon_atom_set_ac_timing(struct radeon_device *rdev,
320 u32 mem_clock);
321int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
322 u8 module_index,
323 struct atom_mc_reg_table *reg_table);
324int radeon_atom_get_memory_info(struct radeon_device *rdev,
325 u8 module_index, struct atom_memory_info *mem_info);
326int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
327 bool gddr5, u8 module_index,
328 struct atom_memory_clock_range_table *mclk_range_table);
329int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
330 u16 voltage_id, u16 *voltage);
Alex Deucherf8920342010-06-30 12:02:03 -0400331void rs690_pm_info(struct radeon_device *rdev);
Jerome Glisse285484e2011-12-16 17:03:42 -0500332extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
333 unsigned *bankh, unsigned *mtaspect,
334 unsigned *tile_split);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000335
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200336/*
337 * Fences.
338 */
339struct radeon_fence_driver {
340 uint32_t scratch_reg;
Jerome Glisse30eb77f2011-11-20 20:45:34 +0000341 uint64_t gpu_addr;
342 volatile uint32_t *cpu_addr;
Christian König68e250b2012-05-10 15:57:31 +0200343 /* sync_seq is protected by ring emission lock */
344 uint64_t sync_seq[RADEON_NUM_RINGS];
Jerome Glissebb635562012-05-09 15:34:46 +0200345 atomic64_t last_seq;
Jerome Glisse0a0c7592009-12-11 20:36:19 +0100346 bool initialized;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200347};
348
349struct radeon_fence {
350 struct radeon_device *rdev;
351 struct kref kref;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200352 /* protected by radeon_fence.lock */
Jerome Glissebb635562012-05-09 15:34:46 +0200353 uint64_t seq;
Alex Deucher74652802011-08-25 13:39:48 -0400354 /* RB, DMA, etc. */
Jerome Glissebb635562012-05-09 15:34:46 +0200355 unsigned ring;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200356};
357
Jerome Glisse30eb77f2011-11-20 20:45:34 +0000358int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
359int radeon_fence_driver_init(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200360void radeon_fence_driver_fini(struct radeon_device *rdev);
Jerome Glisse76903b92012-12-17 10:29:06 -0500361void radeon_fence_driver_force_completion(struct radeon_device *rdev);
Christian König876dc9f2012-05-08 14:24:01 +0200362int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
Alex Deucher74652802011-08-25 13:39:48 -0400363void radeon_fence_process(struct radeon_device *rdev, int ring);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200364bool radeon_fence_signaled(struct radeon_fence *fence);
365int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
Christian König37615522014-02-18 15:58:31 +0100366int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
367int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
Jerome Glisse0085c9502012-05-09 15:34:55 +0200368int radeon_fence_wait_any(struct radeon_device *rdev,
369 struct radeon_fence **fences,
370 bool intr);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200371struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
372void radeon_fence_unref(struct radeon_fence **fence);
Jerome Glisse3b7a2b22012-05-09 15:34:47 +0200373unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
Christian König68e250b2012-05-10 15:57:31 +0200374bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
375void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
376static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
377 struct radeon_fence *b)
378{
379 if (!a) {
380 return b;
381 }
382
383 if (!b) {
384 return a;
385 }
386
387 BUG_ON(a->ring != b->ring);
388
389 if (a->seq > b->seq) {
390 return a;
391 } else {
392 return b;
393 }
394}
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200395
Christian Königee60e292012-08-09 16:21:08 +0200396static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
397 struct radeon_fence *b)
398{
399 if (!a) {
400 return false;
401 }
402
403 if (!b) {
404 return true;
405 }
406
407 BUG_ON(a->ring != b->ring);
408
409 return a->seq < b->seq;
410}
411
Dave Airliee024e112009-06-24 09:48:08 +1000412/*
413 * Tiling registers
414 */
415struct radeon_surface_reg {
Jerome Glisse4c788672009-11-20 14:29:23 +0100416 struct radeon_bo *bo;
Dave Airliee024e112009-06-24 09:48:08 +1000417};
418
419#define RADEON_GEM_MAX_SURFACES 8
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200420
421/*
Jerome Glisse4c788672009-11-20 14:29:23 +0100422 * TTM.
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200423 */
Jerome Glisse4c788672009-11-20 14:29:23 +0100424struct radeon_mman {
425 struct ttm_bo_global_ref bo_global_ref;
Dave Airlieba4420c2010-03-09 10:56:52 +1000426 struct drm_global_reference mem_global_ref;
Jerome Glisse4c788672009-11-20 14:29:23 +0100427 struct ttm_bo_device bdev;
Jerome Glisse0a0c7592009-12-11 20:36:19 +0100428 bool mem_global_referenced;
429 bool initialized;
Christian König2014b562013-12-18 21:07:39 +0100430
431#if defined(CONFIG_DEBUG_FS)
432 struct dentry *vram;
Christian Königdd66d202013-12-18 21:07:40 +0100433 struct dentry *gtt;
Christian König2014b562013-12-18 21:07:39 +0100434#endif
Jerome Glisse4c788672009-11-20 14:29:23 +0100435};
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200436
Jerome Glisse721604a2012-01-05 22:11:05 -0500437/* bo virtual address in a specific vm */
438struct radeon_bo_va {
Christian Könige971bd52012-09-11 16:10:04 +0200439 /* protected by bo being reserved */
Jerome Glisse721604a2012-01-05 22:11:05 -0500440 struct list_head bo_list;
Jerome Glisse721604a2012-01-05 22:11:05 -0500441 uint64_t soffset;
442 uint64_t eoffset;
443 uint32_t flags;
444 bool valid;
Christian Könige971bd52012-09-11 16:10:04 +0200445 unsigned ref_count;
446
447 /* protected by vm mutex */
448 struct list_head vm_list;
449
450 /* constant after initialization */
451 struct radeon_vm *vm;
452 struct radeon_bo *bo;
Jerome Glisse721604a2012-01-05 22:11:05 -0500453};
454
Jerome Glisse4c788672009-11-20 14:29:23 +0100455struct radeon_bo {
456 /* Protected by gem.mutex */
457 struct list_head list;
458 /* Protected by tbo.reserved */
Marek Olšákbda72d52014-03-02 00:56:17 +0100459 u32 initial_domain;
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100460 u32 placements[3];
461 struct ttm_placement placement;
Jerome Glisse4c788672009-11-20 14:29:23 +0100462 struct ttm_buffer_object tbo;
463 struct ttm_bo_kmap_obj kmap;
464 unsigned pin_count;
465 void *kptr;
466 u32 tiling_flags;
467 u32 pitch;
468 int surface_reg;
Jerome Glisse721604a2012-01-05 22:11:05 -0500469 /* list of all virtual address to which this bo
470 * is associated to
471 */
472 struct list_head va;
Jerome Glisse4c788672009-11-20 14:29:23 +0100473 /* Constant after initialization */
474 struct radeon_device *rdev;
Daniel Vetter441921d2011-02-18 17:59:16 +0100475 struct drm_gem_object gem_base;
Dave Airlie63bc6202012-05-31 13:52:53 +0100476
Jerome Glisse409851f2013-04-25 22:29:27 -0400477 struct ttm_bo_kmap_obj dma_buf_vmap;
478 pid_t pid;
Jerome Glisse4c788672009-11-20 14:29:23 +0100479};
Daniel Vetter7e4d15d2011-02-18 17:59:17 +0100480#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
Jerome Glisse4c788672009-11-20 14:29:23 +0100481
Jerome Glisse409851f2013-04-25 22:29:27 -0400482int radeon_gem_debugfs_init(struct radeon_device *rdev);
483
Jerome Glisseb15ba512011-11-15 11:48:34 -0500484/* sub-allocation manager, it has to be protected by another lock.
485 * By conception this is an helper for other part of the driver
486 * like the indirect buffer or semaphore, which both have their
487 * locking.
488 *
489 * Principe is simple, we keep a list of sub allocation in offset
490 * order (first entry has offset == 0, last entry has the highest
491 * offset).
492 *
493 * When allocating new object we first check if there is room at
494 * the end total_size - (last_object_offset + last_object_size) >=
495 * alloc_size. If so we allocate new object there.
496 *
497 * When there is not enough room at the end, we start waiting for
498 * each sub object until we reach object_offset+object_size >=
499 * alloc_size, this object then become the sub object we return.
500 *
501 * Alignment can't be bigger than page size.
502 *
503 * Hole are not considered for allocation to keep things simple.
504 * Assumption is that there won't be hole (all object on same
505 * alignment).
506 */
507struct radeon_sa_manager {
Christian Königbfb38d32012-07-11 21:07:57 +0200508 wait_queue_head_t wq;
Jerome Glisseb15ba512011-11-15 11:48:34 -0500509 struct radeon_bo *bo;
Christian Königc3b7fe82012-05-09 15:34:56 +0200510 struct list_head *hole;
511 struct list_head flist[RADEON_NUM_RINGS];
512 struct list_head olist;
Jerome Glisseb15ba512011-11-15 11:48:34 -0500513 unsigned size;
514 uint64_t gpu_addr;
515 void *cpu_ptr;
516 uint32_t domain;
Alex Deucher6c4f9782013-07-12 15:46:09 -0400517 uint32_t align;
Jerome Glisseb15ba512011-11-15 11:48:34 -0500518};
519
520struct radeon_sa_bo;
521
522/* sub-allocation buffer */
523struct radeon_sa_bo {
Christian Königc3b7fe82012-05-09 15:34:56 +0200524 struct list_head olist;
525 struct list_head flist;
Jerome Glisseb15ba512011-11-15 11:48:34 -0500526 struct radeon_sa_manager *manager;
Christian Könige6661a92012-05-09 15:34:52 +0200527 unsigned soffset;
528 unsigned eoffset;
Christian König557017a2012-05-09 15:34:54 +0200529 struct radeon_fence *fence;
Jerome Glisseb15ba512011-11-15 11:48:34 -0500530};
531
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200532/*
533 * GEM objects.
534 */
535struct radeon_gem {
Jerome Glisse4c788672009-11-20 14:29:23 +0100536 struct mutex mutex;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200537 struct list_head objects;
538};
539
540int radeon_gem_init(struct radeon_device *rdev);
541void radeon_gem_fini(struct radeon_device *rdev);
542int radeon_gem_object_create(struct radeon_device *rdev, int size,
Jerome Glisse4c788672009-11-20 14:29:23 +0100543 int alignment, int initial_domain,
544 bool discardable, bool kernel,
545 struct drm_gem_object **obj);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200546
Dave Airlieff72145b2011-02-07 12:16:14 +1000547int radeon_mode_dumb_create(struct drm_file *file_priv,
548 struct drm_device *dev,
549 struct drm_mode_create_dumb *args);
550int radeon_mode_dumb_mmap(struct drm_file *filp,
551 struct drm_device *dev,
552 uint32_t handle, uint64_t *offset_p);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200553
554/*
Jerome Glissec1341e52011-12-21 12:13:47 -0500555 * Semaphores.
556 */
Jerome Glissec1341e52011-12-21 12:13:47 -0500557struct radeon_semaphore {
Jerome Glissea8c05942012-05-09 15:34:57 +0200558 struct radeon_sa_bo *sa_bo;
559 signed waiters;
Jerome Glissec1341e52011-12-21 12:13:47 -0500560 uint64_t gpu_addr;
Christian König1654b812013-11-12 12:58:05 +0100561 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
Jerome Glissec1341e52011-12-21 12:13:47 -0500562};
563
Jerome Glissec1341e52011-12-21 12:13:47 -0500564int radeon_semaphore_create(struct radeon_device *rdev,
565 struct radeon_semaphore **semaphore);
Christian König1654b812013-11-12 12:58:05 +0100566bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
Jerome Glissec1341e52011-12-21 12:13:47 -0500567 struct radeon_semaphore *semaphore);
Christian König1654b812013-11-12 12:58:05 +0100568bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
Jerome Glissec1341e52011-12-21 12:13:47 -0500569 struct radeon_semaphore *semaphore);
Christian König1654b812013-11-12 12:58:05 +0100570void radeon_semaphore_sync_to(struct radeon_semaphore *semaphore,
571 struct radeon_fence *fence);
Christian König8f676c42012-05-02 15:11:18 +0200572int radeon_semaphore_sync_rings(struct radeon_device *rdev,
573 struct radeon_semaphore *semaphore,
Christian König1654b812013-11-12 12:58:05 +0100574 int waiting_ring);
Jerome Glissec1341e52011-12-21 12:13:47 -0500575void radeon_semaphore_free(struct radeon_device *rdev,
Christian König220907d2012-05-10 16:46:43 +0200576 struct radeon_semaphore **semaphore,
Jerome Glissea8c05942012-05-09 15:34:57 +0200577 struct radeon_fence *fence);
Jerome Glissec1341e52011-12-21 12:13:47 -0500578
579/*
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200580 * GART structures, functions & helpers
581 */
582struct radeon_mc;
583
Matt Turnera77f1712009-10-14 00:34:41 -0400584#define RADEON_GPU_PAGE_SIZE 4096
Jerome Glissed594e462010-02-17 21:54:29 +0000585#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
Alex Deucher003cefe2011-09-16 12:04:08 -0400586#define RADEON_GPU_PAGE_SHIFT 12
Jerome Glisse721604a2012-01-05 22:11:05 -0500587#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
Matt Turnera77f1712009-10-14 00:34:41 -0400588
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200589struct radeon_gart {
590 dma_addr_t table_addr;
Jerome Glissec9a1be92011-11-03 11:16:49 -0400591 struct radeon_bo *robj;
592 void *ptr;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200593 unsigned num_gpu_pages;
594 unsigned num_cpu_pages;
595 unsigned table_size;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200596 struct page **pages;
597 dma_addr_t *pages_addr;
598 bool ready;
599};
600
601int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
602void radeon_gart_table_ram_free(struct radeon_device *rdev);
603int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
604void radeon_gart_table_vram_free(struct radeon_device *rdev);
Jerome Glissec9a1be92011-11-03 11:16:49 -0400605int radeon_gart_table_vram_pin(struct radeon_device *rdev);
606void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200607int radeon_gart_init(struct radeon_device *rdev);
608void radeon_gart_fini(struct radeon_device *rdev);
609void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
610 int pages);
611int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
Konrad Rzeszutek Wilkc39d3512010-12-02 11:04:29 -0500612 int pages, struct page **pagelist,
613 dma_addr_t *dma_addr);
Jerome Glissec9a1be92011-11-03 11:16:49 -0400614void radeon_gart_restore(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200615
616
617/*
618 * GPU MC structures, functions & helpers
619 */
620struct radeon_mc {
621 resource_size_t aper_size;
622 resource_size_t aper_base;
623 resource_size_t agp_base;
Dave Airlie7a50f012009-07-21 20:39:30 +1000624 /* for some chips with <= 32MB we need to lie
625 * about vram size near mc fb location */
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000626 u64 mc_vram_size;
Jerome Glissed594e462010-02-17 21:54:29 +0000627 u64 visible_vram_size;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000628 u64 gtt_size;
629 u64 gtt_start;
630 u64 gtt_end;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000631 u64 vram_start;
632 u64 vram_end;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200633 unsigned vram_width;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000634 u64 real_vram_size;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200635 int vram_mtrr;
636 bool vram_is_ddr;
Jerome Glissed594e462010-02-17 21:54:29 +0000637 bool igp_sideport_enabled;
Alex Deucher8d369bb2010-07-15 10:51:10 -0400638 u64 gtt_base_align;
Alex Deucher9ed8b1f2013-04-08 11:13:01 -0400639 u64 mc_mask;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200640};
641
Alex Deucher06b64762010-01-05 11:27:29 -0500642bool radeon_combios_sideport_present(struct radeon_device *rdev);
643bool radeon_atombios_sideport_present(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200644
645/*
646 * GPU scratch registers structures, functions & helpers
647 */
648struct radeon_scratch {
649 unsigned num_reg;
Alex Deucher724c80e2010-08-27 18:25:25 -0400650 uint32_t reg_base;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200651 bool free[32];
652 uint32_t reg[32];
653};
654
655int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
656void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
657
Alex Deucher75efdee2013-03-04 12:47:46 -0500658/*
659 * GPU doorbell structures, functions & helpers
660 */
Andrew Lewyckyd5754ab2013-11-13 15:54:17 -0500661#define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
662
Alex Deucher75efdee2013-03-04 12:47:46 -0500663struct radeon_doorbell {
Alex Deucher75efdee2013-03-04 12:47:46 -0500664 /* doorbell mmio */
Andrew Lewyckyd5754ab2013-11-13 15:54:17 -0500665 resource_size_t base;
666 resource_size_t size;
667 u32 __iomem *ptr;
668 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
669 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)];
Alex Deucher75efdee2013-03-04 12:47:46 -0500670};
671
672int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
673void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200674
675/*
676 * IRQS.
677 */
Alex Deucher6f34be52010-11-21 10:59:01 -0500678
679struct radeon_unpin_work {
680 struct work_struct work;
681 struct radeon_device *rdev;
682 int crtc_id;
683 struct radeon_fence *fence;
684 struct drm_pending_vblank_event *event;
685 struct radeon_bo *old_rbo;
686 u64 new_crtc_base;
687};
688
689struct r500_irq_stat_regs {
690 u32 disp_int;
Alex Deucherf122c612012-03-30 08:59:57 -0400691 u32 hdmi0_status;
Alex Deucher6f34be52010-11-21 10:59:01 -0500692};
693
694struct r600_irq_stat_regs {
695 u32 disp_int;
696 u32 disp_int_cont;
697 u32 disp_int_cont2;
698 u32 d1grph_int;
699 u32 d2grph_int;
Alex Deucherf122c612012-03-30 08:59:57 -0400700 u32 hdmi0_status;
701 u32 hdmi1_status;
Alex Deucher6f34be52010-11-21 10:59:01 -0500702};
703
704struct evergreen_irq_stat_regs {
705 u32 disp_int;
706 u32 disp_int_cont;
707 u32 disp_int_cont2;
708 u32 disp_int_cont3;
709 u32 disp_int_cont4;
710 u32 disp_int_cont5;
711 u32 d1grph_int;
712 u32 d2grph_int;
713 u32 d3grph_int;
714 u32 d4grph_int;
715 u32 d5grph_int;
716 u32 d6grph_int;
Alex Deucherf122c612012-03-30 08:59:57 -0400717 u32 afmt_status1;
718 u32 afmt_status2;
719 u32 afmt_status3;
720 u32 afmt_status4;
721 u32 afmt_status5;
722 u32 afmt_status6;
Alex Deucher6f34be52010-11-21 10:59:01 -0500723};
724
Alex Deuchera59781b2012-11-09 10:45:57 -0500725struct cik_irq_stat_regs {
726 u32 disp_int;
727 u32 disp_int_cont;
728 u32 disp_int_cont2;
729 u32 disp_int_cont3;
730 u32 disp_int_cont4;
731 u32 disp_int_cont5;
732 u32 disp_int_cont6;
733};
734
Alex Deucher6f34be52010-11-21 10:59:01 -0500735union radeon_irq_stat_regs {
736 struct r500_irq_stat_regs r500;
737 struct r600_irq_stat_regs r600;
738 struct evergreen_irq_stat_regs evergreen;
Alex Deuchera59781b2012-11-09 10:45:57 -0500739 struct cik_irq_stat_regs cik;
Alex Deucher6f34be52010-11-21 10:59:01 -0500740};
741
Alex Deucherbe0949f2014-04-08 11:28:54 -0400742#define RADEON_MAX_HPD_PINS 7
Ilija Hadzic54bd5202011-10-26 15:43:58 -0400743#define RADEON_MAX_CRTCS 6
Alex Deucherb5306022013-07-31 16:51:33 -0400744#define RADEON_MAX_AFMT_BLOCKS 7
Ilija Hadzic54bd5202011-10-26 15:43:58 -0400745
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200746struct radeon_irq {
Christian Koenigfb982572012-05-17 01:33:30 +0200747 bool installed;
748 spinlock_t lock;
Christian Koenig736fc372012-05-17 19:52:00 +0200749 atomic_t ring_int[RADEON_NUM_RINGS];
Christian Koenigfb982572012-05-17 01:33:30 +0200750 bool crtc_vblank_int[RADEON_MAX_CRTCS];
Christian Koenig736fc372012-05-17 19:52:00 +0200751 atomic_t pflip[RADEON_MAX_CRTCS];
Christian Koenigfb982572012-05-17 01:33:30 +0200752 wait_queue_head_t vblank_queue;
753 bool hpd[RADEON_MAX_HPD_PINS];
Christian Koenigfb982572012-05-17 01:33:30 +0200754 bool afmt[RADEON_MAX_AFMT_BLOCKS];
755 union radeon_irq_stat_regs stat_regs;
Alex Deucher4a6369e2013-04-12 14:04:10 -0400756 bool dpm_thermal;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200757};
758
759int radeon_irq_kms_init(struct radeon_device *rdev);
760void radeon_irq_kms_fini(struct radeon_device *rdev);
Alex Deucher1b370782011-11-17 20:13:28 -0500761void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
762void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
Alex Deucher6f34be52010-11-21 10:59:01 -0500763void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
764void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
Christian Koenigfb982572012-05-17 01:33:30 +0200765void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
766void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
767void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
768void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200769
770/*
Christian Könige32eb502011-10-23 12:56:27 +0200771 * CP & rings.
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200772 */
Alex Deucher74652802011-08-25 13:39:48 -0400773
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200774struct radeon_ib {
Jerome Glisse68470ae2012-05-09 15:35:00 +0200775 struct radeon_sa_bo *sa_bo;
776 uint32_t length_dw;
777 uint64_t gpu_addr;
778 uint32_t *ptr;
Christian König876dc9f2012-05-08 14:24:01 +0200779 int ring;
Jerome Glisse68470ae2012-05-09 15:35:00 +0200780 struct radeon_fence *fence;
Christian König4bf3dd92012-08-06 18:57:44 +0200781 struct radeon_vm *vm;
Jerome Glisse68470ae2012-05-09 15:35:00 +0200782 bool is_const_ib;
783 struct radeon_semaphore *semaphore;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200784};
785
Christian Könige32eb502011-10-23 12:56:27 +0200786struct radeon_ring {
Jerome Glisse4c788672009-11-20 14:29:23 +0100787 struct radeon_bo *ring_obj;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200788 volatile uint32_t *ring;
Christian König5596a9d2011-10-13 12:48:45 +0200789 unsigned rptr_offs;
Christian König45df6802012-07-06 16:22:55 +0200790 unsigned rptr_save_reg;
Alex Deucher89d35802012-07-17 14:02:31 -0400791 u64 next_rptr_gpu_addr;
792 volatile u32 *next_rptr_cpu_addr;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200793 unsigned wptr;
794 unsigned wptr_old;
795 unsigned ring_size;
796 unsigned ring_free_dw;
797 int count_dw;
Christian Königaee4aa72014-02-18 15:24:06 +0100798 atomic_t last_rptr;
799 atomic64_t last_activity;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200800 uint64_t gpu_addr;
801 uint32_t align_mask;
802 uint32_t ptr_mask;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200803 bool ready;
Alex Deucher78c55602011-11-17 14:25:56 -0500804 u32 nop;
Alex Deucher8b25ed32012-07-17 14:02:30 -0400805 u32 idx;
Jerome Glisse5f0839c2013-01-11 15:19:43 -0500806 u64 last_semaphore_signal_addr;
807 u64 last_semaphore_wait_addr;
Alex Deucher963e81f2013-06-26 17:37:11 -0400808 /* for CIK queues */
809 u32 me;
810 u32 pipe;
811 u32 queue;
812 struct radeon_bo *mqd_obj;
Andrew Lewyckyd5754ab2013-11-13 15:54:17 -0500813 u32 doorbell_index;
Alex Deucher963e81f2013-06-26 17:37:11 -0400814 unsigned wptr_offs;
815};
816
817struct radeon_mec {
818 struct radeon_bo *hpd_eop_obj;
819 u64 hpd_eop_gpu_addr;
820 u32 num_pipe;
821 u32 num_mec;
822 u32 num_queue;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200823};
824
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500825/*
Jerome Glisse721604a2012-01-05 22:11:05 -0500826 * VM
827 */
Christian Königee60e292012-08-09 16:21:08 +0200828
Dmitry Cherkasovfa87e622012-09-17 19:36:19 +0200829/* maximum number of VMIDs */
Christian Königee60e292012-08-09 16:21:08 +0200830#define RADEON_NUM_VM 16
831
Dmitry Cherkasovfa87e622012-09-17 19:36:19 +0200832/* defines number of bits in page table versus page directory,
833 * a page is 4KB so we have 12 bits offset, 9 bits in the page
834 * table and the remaining 19 bits are in the page directory */
835#define RADEON_VM_BLOCK_SIZE 9
836
837/* number of entries in page table */
838#define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE)
839
Alex Deucher1c011032013-07-12 15:56:02 -0400840/* PTBs (Page Table Blocks) need to be aligned to 32K */
841#define RADEON_VM_PTB_ALIGN_SIZE 32768
842#define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
843#define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
844
Christian König24c16432013-10-30 11:51:09 -0400845#define R600_PTE_VALID (1 << 0)
846#define R600_PTE_SYSTEM (1 << 1)
847#define R600_PTE_SNOOPED (1 << 2)
848#define R600_PTE_READABLE (1 << 5)
849#define R600_PTE_WRITEABLE (1 << 6)
850
Christian König6d2f2942014-02-20 13:42:17 +0100851struct radeon_vm_pt {
852 struct radeon_bo *bo;
853 uint64_t addr;
854};
855
Jerome Glisse721604a2012-01-05 22:11:05 -0500856struct radeon_vm {
Jerome Glisse721604a2012-01-05 22:11:05 -0500857 struct list_head va;
Christian Königee60e292012-08-09 16:21:08 +0200858 unsigned id;
Christian König90a51a32012-10-09 13:31:17 +0200859
860 /* contains the page directory */
Christian König6d2f2942014-02-20 13:42:17 +0100861 struct radeon_bo *page_directory;
Christian König90a51a32012-10-09 13:31:17 +0200862 uint64_t pd_gpu_addr;
Christian König6d2f2942014-02-20 13:42:17 +0100863 unsigned max_pde_used;
Christian König90a51a32012-10-09 13:31:17 +0200864
865 /* array of page tables, one for each page directory entry */
Christian König6d2f2942014-02-20 13:42:17 +0100866 struct radeon_vm_pt *page_tables;
Christian König90a51a32012-10-09 13:31:17 +0200867
Jerome Glisse721604a2012-01-05 22:11:05 -0500868 struct mutex mutex;
869 /* last fence for cs using this vm */
870 struct radeon_fence *fence;
Christian König9b40e5d2012-08-08 12:22:43 +0200871 /* last flush or NULL if we still need to flush */
872 struct radeon_fence *last_flush;
Christian König593b2632014-01-23 14:24:15 +0100873 /* last use of vmid */
874 struct radeon_fence *last_id_use;
Jerome Glisse721604a2012-01-05 22:11:05 -0500875};
876
Jerome Glisse721604a2012-01-05 22:11:05 -0500877struct radeon_vm_manager {
Christian Königee60e292012-08-09 16:21:08 +0200878 struct radeon_fence *active[RADEON_NUM_VM];
Jerome Glisse721604a2012-01-05 22:11:05 -0500879 uint32_t max_pfn;
Jerome Glisse721604a2012-01-05 22:11:05 -0500880 /* number of VMIDs */
881 unsigned nvm;
882 /* vram base address for page table entry */
883 u64 vram_base_offset;
Alex Deucher67e915e2012-01-06 09:38:15 -0500884 /* is vm enabled? */
885 bool enabled;
Jerome Glisse721604a2012-01-05 22:11:05 -0500886};
887
888/*
889 * file private structure
890 */
891struct radeon_fpriv {
892 struct radeon_vm vm;
893};
894
895/*
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500896 * R6xx+ IH ring
897 */
898struct r600_ih {
Jerome Glisse4c788672009-11-20 14:29:23 +0100899 struct radeon_bo *ring_obj;
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500900 volatile uint32_t *ring;
901 unsigned rptr;
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500902 unsigned ring_size;
903 uint64_t gpu_addr;
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500904 uint32_t ptr_mask;
Christian Koenigc20dc362012-05-16 21:45:24 +0200905 atomic_t lock;
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500906 bool enabled;
907};
908
Alex Deucher347e7592012-03-20 17:18:21 -0400909/*
Alex Deucher2948f5e2013-04-12 13:52:52 -0400910 * RLC stuff
Alex Deucher347e7592012-03-20 17:18:21 -0400911 */
Alex Deucher2948f5e2013-04-12 13:52:52 -0400912#include "clearstate_defs.h"
913
914struct radeon_rlc {
Alex Deucher347e7592012-03-20 17:18:21 -0400915 /* for power gating */
916 struct radeon_bo *save_restore_obj;
917 uint64_t save_restore_gpu_addr;
Alex Deucher2948f5e2013-04-12 13:52:52 -0400918 volatile uint32_t *sr_ptr;
Alex Deucher1fd11772013-04-17 17:53:50 -0400919 const u32 *reg_list;
Alex Deucher2948f5e2013-04-12 13:52:52 -0400920 u32 reg_list_size;
Alex Deucher347e7592012-03-20 17:18:21 -0400921 /* for clear state */
922 struct radeon_bo *clear_state_obj;
923 uint64_t clear_state_gpu_addr;
Alex Deucher2948f5e2013-04-12 13:52:52 -0400924 volatile uint32_t *cs_ptr;
Alex Deucher1fd11772013-04-17 17:53:50 -0400925 const struct cs_section_def *cs_data;
Alex Deucher22c775c2013-07-23 09:41:05 -0400926 u32 clear_state_size;
927 /* for cp tables */
928 struct radeon_bo *cp_table_obj;
929 uint64_t cp_table_gpu_addr;
930 volatile uint32_t *cp_table_ptr;
931 u32 cp_table_size;
Alex Deucher347e7592012-03-20 17:18:21 -0400932};
933
Jerome Glisse69e130a2011-12-21 12:13:46 -0500934int radeon_ib_get(struct radeon_device *rdev, int ring,
Christian König4bf3dd92012-08-06 18:57:44 +0200935 struct radeon_ib *ib, struct radeon_vm *vm,
936 unsigned size);
Jerome Glissef2e39222012-05-09 15:35:02 +0200937void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
Christian König4ef72562012-07-13 13:06:00 +0200938int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
939 struct radeon_ib *const_ib);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200940int radeon_ib_pool_init(struct radeon_device *rdev);
941void radeon_ib_pool_fini(struct radeon_device *rdev);
Christian König7bd560e2012-05-02 15:11:12 +0200942int radeon_ib_ring_tests(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200943/* Ring access between begin & end cannot sleep */
Alex Deucher89d35802012-07-17 14:02:31 -0400944bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
945 struct radeon_ring *ring);
Christian Könige32eb502011-10-23 12:56:27 +0200946void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
947int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
948int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
949void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
950void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
Christian Königd6999bc2012-05-09 15:34:45 +0200951void radeon_ring_undo(struct radeon_ring *ring);
Christian Könige32eb502011-10-23 12:56:27 +0200952void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
953int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
Christian Königff212f22014-02-18 14:52:33 +0100954void radeon_ring_lockup_update(struct radeon_device *rdev,
955 struct radeon_ring *ring);
Christian König069211e2012-05-02 15:11:20 +0200956bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
Christian König55d7c222012-07-09 11:52:44 +0200957unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
958 uint32_t **data);
959int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
960 unsigned size, uint32_t *data);
Christian Könige32eb502011-10-23 12:56:27 +0200961int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
Alex Deucherea31bf62013-12-09 19:44:30 -0500962 unsigned rptr_offs, u32 nop);
Christian Könige32eb502011-10-23 12:56:27 +0200963void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200964
965
Alex Deucher4d756582012-09-27 15:08:35 -0400966/* r600 async dma */
967void r600_dma_stop(struct radeon_device *rdev);
968int r600_dma_resume(struct radeon_device *rdev);
969void r600_dma_fini(struct radeon_device *rdev);
970
Alex Deucher8c5fd7e2012-12-04 15:28:18 -0500971void cayman_dma_stop(struct radeon_device *rdev);
972int cayman_dma_resume(struct radeon_device *rdev);
973void cayman_dma_fini(struct radeon_device *rdev);
974
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200975/*
976 * CS.
977 */
978struct radeon_cs_reloc {
979 struct drm_gem_object *gobj;
Jerome Glisse4c788672009-11-20 14:29:23 +0100980 struct radeon_bo *robj;
Christian Königdf0af442014-03-03 12:38:08 +0100981 struct ttm_validate_buffer tv;
982 uint64_t gpu_offset;
983 unsigned domain;
984 unsigned alt_domain;
985 uint32_t tiling_flags;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200986 uint32_t handle;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200987};
988
989struct radeon_cs_chunk {
990 uint32_t chunk_id;
991 uint32_t length_dw;
992 uint32_t *kdata;
Jerome Glisse721604a2012-01-05 22:11:05 -0500993 void __user *user_ptr;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200994};
995
996struct radeon_cs_parser {
Jerome Glissec8c15ff2010-01-18 13:01:36 +0100997 struct device *dev;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200998 struct radeon_device *rdev;
999 struct drm_file *filp;
1000 /* chunks */
1001 unsigned nchunks;
1002 struct radeon_cs_chunk *chunks;
1003 uint64_t *chunks_array;
1004 /* IB */
1005 unsigned idx;
1006 /* relocations */
1007 unsigned nrelocs;
1008 struct radeon_cs_reloc *relocs;
1009 struct radeon_cs_reloc **relocs_ptr;
Christian Königdf0af442014-03-03 12:38:08 +01001010 struct radeon_cs_reloc *vm_bos;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001011 struct list_head validated;
Alex Deuchercf4ccd02011-11-18 10:19:47 -05001012 unsigned dma_reloc_idx;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001013 /* indices of various chunks */
1014 int chunk_ib_idx;
1015 int chunk_relocs_idx;
Jerome Glisse721604a2012-01-05 22:11:05 -05001016 int chunk_flags_idx;
Alex Deucherdfcf5f32012-03-20 17:18:14 -04001017 int chunk_const_ib_idx;
Jerome Glissef2e39222012-05-09 15:35:02 +02001018 struct radeon_ib ib;
1019 struct radeon_ib const_ib;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001020 void *track;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001021 unsigned family;
Marek Olšáke70f2242011-10-25 01:38:45 +02001022 int parser_error;
Jerome Glisse721604a2012-01-05 22:11:05 -05001023 u32 cs_flags;
1024 u32 ring;
1025 s32 priority;
Maarten Lankhorstecff6652013-06-27 13:48:17 +02001026 struct ww_acquire_ctx ticket;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001027};
1028
Maarten Lankhorst28a326c2013-10-09 14:36:57 +02001029static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1030{
1031 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
1032
1033 if (ibc->kdata)
1034 return ibc->kdata[idx];
1035 return p->ib.ptr[idx];
1036}
1037
Dave Airlie513bcb42009-09-23 16:56:27 +10001038
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001039struct radeon_cs_packet {
1040 unsigned idx;
1041 unsigned type;
1042 unsigned reg;
1043 unsigned opcode;
1044 int count;
1045 unsigned one_reg_wr;
1046};
1047
1048typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1049 struct radeon_cs_packet *pkt,
1050 unsigned idx, unsigned reg);
1051typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1052 struct radeon_cs_packet *pkt);
1053
1054
1055/*
1056 * AGP
1057 */
1058int radeon_agp_init(struct radeon_device *rdev);
Dave Airlie0ebf1712009-11-05 15:39:10 +10001059void radeon_agp_resume(struct radeon_device *rdev);
Jerome Glisse10b06122010-05-21 18:48:54 +02001060void radeon_agp_suspend(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001061void radeon_agp_fini(struct radeon_device *rdev);
1062
1063
1064/*
1065 * Writeback
1066 */
1067struct radeon_wb {
Jerome Glisse4c788672009-11-20 14:29:23 +01001068 struct radeon_bo *wb_obj;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001069 volatile uint32_t *wb;
1070 uint64_t gpu_addr;
Alex Deucher724c80e2010-08-27 18:25:25 -04001071 bool enabled;
Alex Deucherd0f8a852010-09-04 05:04:34 -04001072 bool use_event;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001073};
1074
Alex Deucher724c80e2010-08-27 18:25:25 -04001075#define RADEON_WB_SCRATCH_OFFSET 0
Alex Deucher89d35802012-07-17 14:02:31 -04001076#define RADEON_WB_RING0_NEXT_RPTR 256
Alex Deucher724c80e2010-08-27 18:25:25 -04001077#define RADEON_WB_CP_RPTR_OFFSET 1024
Alex Deucher0c88a022011-03-02 20:07:31 -05001078#define RADEON_WB_CP1_RPTR_OFFSET 1280
1079#define RADEON_WB_CP2_RPTR_OFFSET 1536
Alex Deucher4d756582012-09-27 15:08:35 -04001080#define R600_WB_DMA_RPTR_OFFSET 1792
Alex Deucher724c80e2010-08-27 18:25:25 -04001081#define R600_WB_IH_WPTR_OFFSET 2048
Alex Deucherf60cbd12012-12-04 15:27:33 -05001082#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
Alex Deucherd0f8a852010-09-04 05:04:34 -04001083#define R600_WB_EVENT_OFFSET 3072
Alex Deucher963e81f2013-06-26 17:37:11 -04001084#define CIK_WB_CP1_WPTR_OFFSET 3328
1085#define CIK_WB_CP2_WPTR_OFFSET 3584
Alex Deucher724c80e2010-08-27 18:25:25 -04001086
Jerome Glissec93bb852009-07-13 21:04:08 +02001087/**
1088 * struct radeon_pm - power management datas
1089 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1090 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1091 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1092 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1093 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1094 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1095 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1096 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1097 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
Lucas De Marchi25985ed2011-03-30 22:57:33 -03001098 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
Jerome Glissec93bb852009-07-13 21:04:08 +02001099 * @needed_bandwidth: current bandwidth needs
1100 *
1101 * It keeps track of various data needed to take powermanagement decision.
Lucas De Marchi25985ed2011-03-30 22:57:33 -03001102 * Bandwidth need is used to determine minimun clock of the GPU and memory.
Jerome Glissec93bb852009-07-13 21:04:08 +02001103 * Equation between gpu/memory clock and available bandwidth is hw dependent
1104 * (type of memory, bus size, efficiency, ...)
1105 */
Alex Deucherce8f5372010-05-07 15:10:16 -04001106
1107enum radeon_pm_method {
1108 PM_METHOD_PROFILE,
1109 PM_METHOD_DYNPM,
Alex Deucherda321c82013-04-12 13:55:22 -04001110 PM_METHOD_DPM,
Rafał Miłeckic913e232009-12-22 23:02:16 +01001111};
Alex Deucherce8f5372010-05-07 15:10:16 -04001112
1113enum radeon_dynpm_state {
1114 DYNPM_STATE_DISABLED,
1115 DYNPM_STATE_MINIMUM,
1116 DYNPM_STATE_PAUSED,
Rafael J. Wysocki3f53eb62010-06-17 23:02:27 +00001117 DYNPM_STATE_ACTIVE,
1118 DYNPM_STATE_SUSPENDED,
Alex Deucherce8f5372010-05-07 15:10:16 -04001119};
1120enum radeon_dynpm_action {
1121 DYNPM_ACTION_NONE,
1122 DYNPM_ACTION_MINIMUM,
1123 DYNPM_ACTION_DOWNCLOCK,
1124 DYNPM_ACTION_UPCLOCK,
1125 DYNPM_ACTION_DEFAULT
Rafał Miłeckic913e232009-12-22 23:02:16 +01001126};
Alex Deucher56278a82009-12-28 13:58:44 -05001127
1128enum radeon_voltage_type {
1129 VOLTAGE_NONE = 0,
1130 VOLTAGE_GPIO,
1131 VOLTAGE_VDDC,
1132 VOLTAGE_SW
1133};
1134
Alex Deucher0ec0e742009-12-23 13:21:58 -05001135enum radeon_pm_state_type {
Alex Deucherda321c82013-04-12 13:55:22 -04001136 /* not used for dpm */
Alex Deucher0ec0e742009-12-23 13:21:58 -05001137 POWER_STATE_TYPE_DEFAULT,
1138 POWER_STATE_TYPE_POWERSAVE,
Alex Deucherda321c82013-04-12 13:55:22 -04001139 /* user selectable states */
Alex Deucher0ec0e742009-12-23 13:21:58 -05001140 POWER_STATE_TYPE_BATTERY,
1141 POWER_STATE_TYPE_BALANCED,
1142 POWER_STATE_TYPE_PERFORMANCE,
Alex Deucherda321c82013-04-12 13:55:22 -04001143 /* internal states */
1144 POWER_STATE_TYPE_INTERNAL_UVD,
1145 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1146 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1147 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1148 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1149 POWER_STATE_TYPE_INTERNAL_BOOT,
1150 POWER_STATE_TYPE_INTERNAL_THERMAL,
1151 POWER_STATE_TYPE_INTERNAL_ACPI,
1152 POWER_STATE_TYPE_INTERNAL_ULV,
Alex Deucheredcaa5b2013-07-05 11:48:31 -04001153 POWER_STATE_TYPE_INTERNAL_3DPERF,
Alex Deucher0ec0e742009-12-23 13:21:58 -05001154};
1155
Alex Deucherce8f5372010-05-07 15:10:16 -04001156enum radeon_pm_profile_type {
1157 PM_PROFILE_DEFAULT,
1158 PM_PROFILE_AUTO,
1159 PM_PROFILE_LOW,
Alex Deucherc9e75b22010-06-02 17:56:01 -04001160 PM_PROFILE_MID,
Alex Deucherce8f5372010-05-07 15:10:16 -04001161 PM_PROFILE_HIGH,
1162};
1163
1164#define PM_PROFILE_DEFAULT_IDX 0
1165#define PM_PROFILE_LOW_SH_IDX 1
Alex Deucherc9e75b22010-06-02 17:56:01 -04001166#define PM_PROFILE_MID_SH_IDX 2
1167#define PM_PROFILE_HIGH_SH_IDX 3
1168#define PM_PROFILE_LOW_MH_IDX 4
1169#define PM_PROFILE_MID_MH_IDX 5
1170#define PM_PROFILE_HIGH_MH_IDX 6
1171#define PM_PROFILE_MAX 7
Alex Deucherce8f5372010-05-07 15:10:16 -04001172
1173struct radeon_pm_profile {
1174 int dpms_off_ps_idx;
1175 int dpms_on_ps_idx;
1176 int dpms_off_cm_idx;
1177 int dpms_on_cm_idx;
Alex Deucher516d0e42009-12-23 14:28:05 -05001178};
1179
Alex Deucher21a81222010-07-02 12:58:16 -04001180enum radeon_int_thermal_type {
1181 THERMAL_TYPE_NONE,
Alex Deucherda321c82013-04-12 13:55:22 -04001182 THERMAL_TYPE_EXTERNAL,
1183 THERMAL_TYPE_EXTERNAL_GPIO,
Alex Deucher21a81222010-07-02 12:58:16 -04001184 THERMAL_TYPE_RV6XX,
1185 THERMAL_TYPE_RV770,
Alex Deucherda321c82013-04-12 13:55:22 -04001186 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
Alex Deucher21a81222010-07-02 12:58:16 -04001187 THERMAL_TYPE_EVERGREEN,
Alex Deuchere33df252010-11-22 17:56:32 -05001188 THERMAL_TYPE_SUMO,
Alex Deucher4fddba12011-01-06 21:19:22 -05001189 THERMAL_TYPE_NI,
Alex Deucher14607d02012-03-20 17:18:09 -04001190 THERMAL_TYPE_SI,
Alex Deucherda321c82013-04-12 13:55:22 -04001191 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
Alex Deucher51150202012-12-18 22:07:14 -05001192 THERMAL_TYPE_CI,
Alex Deucher16fbe002013-04-22 21:41:26 -04001193 THERMAL_TYPE_KV,
Alex Deucher21a81222010-07-02 12:58:16 -04001194};
1195
Alex Deucher56278a82009-12-28 13:58:44 -05001196struct radeon_voltage {
1197 enum radeon_voltage_type type;
1198 /* gpio voltage */
1199 struct radeon_gpio_rec gpio;
1200 u32 delay; /* delay in usec from voltage drop to sclk change */
1201 bool active_high; /* voltage drop is active when bit is high */
1202 /* VDDC voltage */
1203 u8 vddc_id; /* index into vddc voltage table */
1204 u8 vddci_id; /* index into vddci voltage table */
1205 bool vddci_enabled;
1206 /* r6xx+ sw */
Alex Deucher2feea492011-04-12 14:49:24 -04001207 u16 voltage;
1208 /* evergreen+ vddci */
1209 u16 vddci;
Alex Deucher56278a82009-12-28 13:58:44 -05001210};
1211
Alex Deucherd7311172010-05-03 01:13:14 -04001212/* clock mode flags */
1213#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1214
Alex Deucher56278a82009-12-28 13:58:44 -05001215struct radeon_pm_clock_info {
1216 /* memory clock */
1217 u32 mclk;
1218 /* engine clock */
1219 u32 sclk;
1220 /* voltage info */
1221 struct radeon_voltage voltage;
Alex Deucherd7311172010-05-03 01:13:14 -04001222 /* standardized clock flags */
Alex Deucher56278a82009-12-28 13:58:44 -05001223 u32 flags;
1224};
1225
Alex Deuchera48b9b42010-04-22 14:03:55 -04001226/* state flags */
Alex Deucherd7311172010-05-03 01:13:14 -04001227#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
Alex Deuchera48b9b42010-04-22 14:03:55 -04001228
Alex Deucher56278a82009-12-28 13:58:44 -05001229struct radeon_power_state {
Alex Deucher0ec0e742009-12-23 13:21:58 -05001230 enum radeon_pm_state_type type;
Alex Deucher8f3f1c92011-11-04 10:09:43 -04001231 struct radeon_pm_clock_info *clock_info;
Alex Deucher56278a82009-12-28 13:58:44 -05001232 /* number of valid clock modes in this power state */
1233 int num_clock_modes;
Alex Deucher56278a82009-12-28 13:58:44 -05001234 struct radeon_pm_clock_info *default_clock_mode;
Alex Deuchera48b9b42010-04-22 14:03:55 -04001235 /* standardized state flags */
1236 u32 flags;
Alex Deucher79daedc2010-04-22 14:25:19 -04001237 u32 misc; /* vbios specific flags */
1238 u32 misc2; /* vbios specific flags */
1239 int pcie_lanes; /* pcie lanes */
Alex Deucher56278a82009-12-28 13:58:44 -05001240};
1241
Rafał Miłecki27459322010-02-11 22:16:36 +00001242/*
1243 * Some modes are overclocked by very low value, accept them
1244 */
1245#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1246
Alex Deucher2e9d4c02013-04-12 13:58:03 -04001247enum radeon_dpm_auto_throttle_src {
1248 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1249 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1250};
1251
1252enum radeon_dpm_event_src {
1253 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1254 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1255 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1256 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1257 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1258};
1259
Alex Deucher58bd2a82013-09-04 16:13:56 -04001260#define RADEON_MAX_VCE_LEVELS 6
1261
Alex Deucherb62d6282013-08-20 20:29:05 -04001262enum radeon_vce_level {
1263 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1264 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1265 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1266 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1267 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1268 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1269};
1270
Alex Deucherda321c82013-04-12 13:55:22 -04001271struct radeon_ps {
1272 u32 caps; /* vbios flags */
1273 u32 class; /* vbios flags */
1274 u32 class2; /* vbios flags */
1275 /* UVD clocks */
1276 u32 vclk;
1277 u32 dclk;
Alex Deucherc4453e62013-05-15 15:53:57 -04001278 /* VCE clocks */
1279 u32 evclk;
1280 u32 ecclk;
Alex Deucherb62d6282013-08-20 20:29:05 -04001281 bool vce_active;
1282 enum radeon_vce_level vce_level;
Alex Deucherda321c82013-04-12 13:55:22 -04001283 /* asic priv */
1284 void *ps_priv;
1285};
1286
1287struct radeon_dpm_thermal {
1288 /* thermal interrupt work */
1289 struct work_struct work;
1290 /* low temperature threshold */
1291 int min_temp;
1292 /* high temperature threshold */
1293 int max_temp;
1294 /* was interrupt low to high or high to low */
1295 bool high_to_low;
1296};
1297
Alex Deucherd22b7e42012-11-29 19:27:56 -05001298enum radeon_clk_action
1299{
1300 RADEON_SCLK_UP = 1,
1301 RADEON_SCLK_DOWN
1302};
1303
1304struct radeon_blacklist_clocks
1305{
1306 u32 sclk;
1307 u32 mclk;
1308 enum radeon_clk_action action;
1309};
1310
Alex Deucher61b7d602012-11-14 19:57:42 -05001311struct radeon_clock_and_voltage_limits {
1312 u32 sclk;
1313 u32 mclk;
Alex Deuchercdf6e802013-10-23 16:13:42 -04001314 u16 vddc;
1315 u16 vddci;
Alex Deucher61b7d602012-11-14 19:57:42 -05001316};
1317
1318struct radeon_clock_array {
1319 u32 count;
1320 u32 *values;
1321};
1322
1323struct radeon_clock_voltage_dependency_entry {
1324 u32 clk;
1325 u16 v;
1326};
1327
1328struct radeon_clock_voltage_dependency_table {
1329 u32 count;
1330 struct radeon_clock_voltage_dependency_entry *entries;
1331};
1332
Alex Deucheref976ec2013-05-06 11:31:04 -04001333union radeon_cac_leakage_entry {
1334 struct {
1335 u16 vddc;
1336 u32 leakage;
1337 };
1338 struct {
1339 u16 vddc1;
1340 u16 vddc2;
1341 u16 vddc3;
1342 };
Alex Deucher61b7d602012-11-14 19:57:42 -05001343};
1344
1345struct radeon_cac_leakage_table {
1346 u32 count;
Alex Deucheref976ec2013-05-06 11:31:04 -04001347 union radeon_cac_leakage_entry *entries;
Alex Deucher61b7d602012-11-14 19:57:42 -05001348};
1349
Alex Deucher929ee7a2013-03-20 12:30:25 -04001350struct radeon_phase_shedding_limits_entry {
1351 u16 voltage;
1352 u32 sclk;
1353 u32 mclk;
1354};
1355
1356struct radeon_phase_shedding_limits_table {
1357 u32 count;
1358 struct radeon_phase_shedding_limits_entry *entries;
1359};
1360
Alex Deucher84a9d9e2013-04-19 19:11:37 -04001361struct radeon_uvd_clock_voltage_dependency_entry {
1362 u32 vclk;
1363 u32 dclk;
1364 u16 v;
1365};
1366
1367struct radeon_uvd_clock_voltage_dependency_table {
1368 u8 count;
1369 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1370};
1371
Alex Deucherd29f0132013-05-09 16:37:28 -04001372struct radeon_vce_clock_voltage_dependency_entry {
1373 u32 ecclk;
1374 u32 evclk;
1375 u16 v;
1376};
1377
1378struct radeon_vce_clock_voltage_dependency_table {
1379 u8 count;
1380 struct radeon_vce_clock_voltage_dependency_entry *entries;
1381};
1382
Alex Deuchera5cb3182013-03-20 13:00:18 -04001383struct radeon_ppm_table {
1384 u8 ppm_design;
1385 u16 cpu_core_number;
1386 u32 platform_tdp;
1387 u32 small_ac_platform_tdp;
1388 u32 platform_tdc;
1389 u32 small_ac_platform_tdc;
1390 u32 apu_tdp;
1391 u32 dgpu_tdp;
1392 u32 dgpu_ulv_power;
1393 u32 tj_max;
1394};
1395
Alex Deucher58cb7632013-05-06 12:15:33 -04001396struct radeon_cac_tdp_table {
1397 u16 tdp;
1398 u16 configurable_tdp;
1399 u16 tdc;
1400 u16 battery_power_limit;
1401 u16 small_power_limit;
1402 u16 low_cac_leakage;
1403 u16 high_cac_leakage;
1404 u16 maximum_power_delivery_limit;
1405};
1406
Alex Deucher61b7d602012-11-14 19:57:42 -05001407struct radeon_dpm_dynamic_state {
1408 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1409 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1410 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
Alex Deucherdd621a22013-05-06 14:37:56 -04001411 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
Alex Deucher4489cd622013-03-22 15:59:10 -04001412 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
Alex Deucher84a9d9e2013-04-19 19:11:37 -04001413 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
Alex Deucherd29f0132013-05-09 16:37:28 -04001414 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
Alex Deucher94a914f2013-05-09 16:42:33 -04001415 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1416 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
Alex Deucher61b7d602012-11-14 19:57:42 -05001417 struct radeon_clock_array valid_sclk_values;
1418 struct radeon_clock_array valid_mclk_values;
1419 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1420 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1421 u32 mclk_sclk_ratio;
1422 u32 sclk_mclk_delta;
1423 u16 vddc_vddci_delta;
1424 u16 min_vddc_for_pcie_gen2;
1425 struct radeon_cac_leakage_table cac_leakage_table;
Alex Deucher929ee7a2013-03-20 12:30:25 -04001426 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
Alex Deuchera5cb3182013-03-20 13:00:18 -04001427 struct radeon_ppm_table *ppm_table;
Alex Deucher58cb7632013-05-06 12:15:33 -04001428 struct radeon_cac_tdp_table *cac_tdp_table;
Alex Deucher61b7d602012-11-14 19:57:42 -05001429};
1430
1431struct radeon_dpm_fan {
1432 u16 t_min;
1433 u16 t_med;
1434 u16 t_high;
1435 u16 pwm_min;
1436 u16 pwm_med;
1437 u16 pwm_high;
1438 u8 t_hyst;
1439 u32 cycle_delay;
1440 u16 t_max;
1441 bool ucode_fan_control;
1442};
1443
Alex Deucher32ce4652013-03-18 17:03:01 -04001444enum radeon_pcie_gen {
1445 RADEON_PCIE_GEN1 = 0,
1446 RADEON_PCIE_GEN2 = 1,
1447 RADEON_PCIE_GEN3 = 2,
1448 RADEON_PCIE_GEN_INVALID = 0xffff
1449};
1450
Alex Deucher70d01a52013-07-02 18:38:02 -04001451enum radeon_dpm_forced_level {
1452 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1453 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1454 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1455};
1456
Alex Deucher58bd2a82013-09-04 16:13:56 -04001457struct radeon_vce_state {
1458 /* vce clocks */
1459 u32 evclk;
1460 u32 ecclk;
1461 /* gpu clocks */
1462 u32 sclk;
1463 u32 mclk;
1464 u8 clk_idx;
1465 u8 pstate;
1466};
1467
Alex Deucherda321c82013-04-12 13:55:22 -04001468struct radeon_dpm {
1469 struct radeon_ps *ps;
1470 /* number of valid power states */
1471 int num_ps;
1472 /* current power state that is active */
1473 struct radeon_ps *current_ps;
1474 /* requested power state */
1475 struct radeon_ps *requested_ps;
1476 /* boot up power state */
1477 struct radeon_ps *boot_ps;
1478 /* default uvd power state */
1479 struct radeon_ps *uvd_ps;
Alex Deucher58bd2a82013-09-04 16:13:56 -04001480 /* vce requirements */
1481 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1482 enum radeon_vce_level vce_level;
Alex Deucherda321c82013-04-12 13:55:22 -04001483 enum radeon_pm_state_type state;
1484 enum radeon_pm_state_type user_state;
1485 u32 platform_caps;
1486 u32 voltage_response_time;
1487 u32 backbias_response_time;
1488 void *priv;
1489 u32 new_active_crtcs;
1490 int new_active_crtc_count;
1491 u32 current_active_crtcs;
1492 int current_active_crtc_count;
Alex Deucher61b7d602012-11-14 19:57:42 -05001493 struct radeon_dpm_dynamic_state dyn_state;
1494 struct radeon_dpm_fan fan;
1495 u32 tdp_limit;
1496 u32 near_tdp_limit;
Alex Deuchera9e61412013-06-25 17:56:16 -04001497 u32 near_tdp_limit_adjusted;
Alex Deucher61b7d602012-11-14 19:57:42 -05001498 u32 sq_ramping_threshold;
1499 u32 cac_leakage;
1500 u16 tdp_od_limit;
1501 u32 tdp_adjustment;
1502 u16 load_line_slope;
1503 bool power_control;
Alex Deucher5ca302f2012-11-30 10:56:57 -05001504 bool ac_power;
Alex Deucherda321c82013-04-12 13:55:22 -04001505 /* special states active */
1506 bool thermal_active;
Alex Deucher8a227552013-06-21 15:12:57 -04001507 bool uvd_active;
Alex Deucherb62d6282013-08-20 20:29:05 -04001508 bool vce_active;
Alex Deucherda321c82013-04-12 13:55:22 -04001509 /* thermal handling */
1510 struct radeon_dpm_thermal thermal;
Alex Deucher70d01a52013-07-02 18:38:02 -04001511 /* forced levels */
1512 enum radeon_dpm_forced_level forced_level;
Alex Deucherce3537d2013-07-24 12:12:49 -04001513 /* track UVD streams */
1514 unsigned sd;
1515 unsigned hd;
Alex Deucherda321c82013-04-12 13:55:22 -04001516};
1517
Alex Deucherce3537d2013-07-24 12:12:49 -04001518void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
Alex Deucher03afe6f2013-08-23 11:56:26 -04001519void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
Alex Deucherda321c82013-04-12 13:55:22 -04001520
Jerome Glissec93bb852009-07-13 21:04:08 +02001521struct radeon_pm {
Rafał Miłeckic913e232009-12-22 23:02:16 +01001522 struct mutex mutex;
Christian Königdb7fce32012-05-11 14:57:18 +02001523 /* write locked while reprogramming mclk */
1524 struct rw_semaphore mclk_lock;
Alex Deuchera48b9b42010-04-22 14:03:55 -04001525 u32 active_crtcs;
1526 int active_crtc_count;
Rafał Miłeckic913e232009-12-22 23:02:16 +01001527 int req_vblank;
Rafał Miłecki839461d2010-03-02 22:06:51 +01001528 bool vblank_sync;
Jerome Glissec93bb852009-07-13 21:04:08 +02001529 fixed20_12 max_bandwidth;
1530 fixed20_12 igp_sideport_mclk;
1531 fixed20_12 igp_system_mclk;
1532 fixed20_12 igp_ht_link_clk;
1533 fixed20_12 igp_ht_link_width;
1534 fixed20_12 k8_bandwidth;
1535 fixed20_12 sideport_bandwidth;
1536 fixed20_12 ht_bandwidth;
1537 fixed20_12 core_bandwidth;
1538 fixed20_12 sclk;
Alex Deucherf47299c2010-03-16 20:54:38 -04001539 fixed20_12 mclk;
Jerome Glissec93bb852009-07-13 21:04:08 +02001540 fixed20_12 needed_bandwidth;
Alex Deucher0975b162011-02-02 18:42:03 -05001541 struct radeon_power_state *power_state;
Alex Deucher56278a82009-12-28 13:58:44 -05001542 /* number of valid power states */
1543 int num_power_states;
Alex Deuchera48b9b42010-04-22 14:03:55 -04001544 int current_power_state_index;
1545 int current_clock_mode_index;
1546 int requested_power_state_index;
1547 int requested_clock_mode_index;
1548 int default_power_state_index;
1549 u32 current_sclk;
1550 u32 current_mclk;
Alex Deucher2feea492011-04-12 14:49:24 -04001551 u16 current_vddc;
1552 u16 current_vddci;
Alex Deucher9ace9f72011-01-06 21:19:26 -05001553 u32 default_sclk;
1554 u32 default_mclk;
Alex Deucher2feea492011-04-12 14:49:24 -04001555 u16 default_vddc;
1556 u16 default_vddci;
Alex Deucher29fb52c2010-03-11 10:01:17 -05001557 struct radeon_i2c_chan *i2c_bus;
Alex Deucherce8f5372010-05-07 15:10:16 -04001558 /* selected pm method */
1559 enum radeon_pm_method pm_method;
1560 /* dynpm power management */
1561 struct delayed_work dynpm_idle_work;
1562 enum radeon_dynpm_state dynpm_state;
1563 enum radeon_dynpm_action dynpm_planned_action;
1564 unsigned long dynpm_action_timeout;
1565 bool dynpm_can_upclock;
1566 bool dynpm_can_downclock;
1567 /* profile-based power management */
1568 enum radeon_pm_profile_type profile;
1569 int profile_index;
1570 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
Alex Deucher21a81222010-07-02 12:58:16 -04001571 /* internal thermal controller on rv6xx+ */
1572 enum radeon_int_thermal_type int_thermal_type;
1573 struct device *int_hwmon_dev;
Alex Deucherda321c82013-04-12 13:55:22 -04001574 /* dpm */
1575 bool dpm_enabled;
1576 struct radeon_dpm dpm;
Jerome Glissec93bb852009-07-13 21:04:08 +02001577};
1578
Alex Deuchera4c9e2e2011-11-04 10:09:41 -04001579int radeon_pm_get_type_index(struct radeon_device *rdev,
1580 enum radeon_pm_state_type ps_type,
1581 int instance);
Christian Königf2ba57b2013-04-08 12:41:29 +02001582/*
1583 * UVD
1584 */
1585#define RADEON_MAX_UVD_HANDLES 10
1586#define RADEON_UVD_STACK_SIZE (1024*1024)
1587#define RADEON_UVD_HEAP_SIZE (1024*1024)
1588
1589struct radeon_uvd {
1590 struct radeon_bo *vcpu_bo;
1591 void *cpu_addr;
1592 uint64_t gpu_addr;
Christian König9cc2e0e2013-07-12 10:18:09 -04001593 void *saved_bo;
Christian Königf2ba57b2013-04-08 12:41:29 +02001594 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1595 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
Alex Deucher85a129c2013-08-05 12:41:20 -04001596 unsigned img_size[RADEON_MAX_UVD_HANDLES];
Christian König55b51c82013-04-18 15:25:59 +02001597 struct delayed_work idle_work;
Christian Königf2ba57b2013-04-08 12:41:29 +02001598};
1599
1600int radeon_uvd_init(struct radeon_device *rdev);
1601void radeon_uvd_fini(struct radeon_device *rdev);
1602int radeon_uvd_suspend(struct radeon_device *rdev);
1603int radeon_uvd_resume(struct radeon_device *rdev);
1604int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1605 uint32_t handle, struct radeon_fence **fence);
1606int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1607 uint32_t handle, struct radeon_fence **fence);
1608void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1609void radeon_uvd_free_handles(struct radeon_device *rdev,
1610 struct drm_file *filp);
1611int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
Christian König55b51c82013-04-18 15:25:59 +02001612void radeon_uvd_note_usage(struct radeon_device *rdev);
Christian Königfacd1122013-04-29 11:55:02 +02001613int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1614 unsigned vclk, unsigned dclk,
1615 unsigned vco_min, unsigned vco_max,
1616 unsigned fb_factor, unsigned fb_mask,
1617 unsigned pd_min, unsigned pd_max,
1618 unsigned pd_even,
1619 unsigned *optimal_fb_div,
1620 unsigned *optimal_vclk_div,
1621 unsigned *optimal_dclk_div);
1622int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1623 unsigned cg_upll_func_cntl);
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001624
Christian Königd93f7932013-05-23 12:10:04 +02001625/*
1626 * VCE
1627 */
1628#define RADEON_MAX_VCE_HANDLES 16
1629#define RADEON_VCE_STACK_SIZE (1024*1024)
1630#define RADEON_VCE_HEAP_SIZE (4*1024*1024)
1631
1632struct radeon_vce {
1633 struct radeon_bo *vcpu_bo;
Christian Königd93f7932013-05-23 12:10:04 +02001634 uint64_t gpu_addr;
Christian König98ccc292014-01-23 09:50:49 -07001635 unsigned fw_version;
1636 unsigned fb_version;
Christian Königd93f7932013-05-23 12:10:04 +02001637 atomic_t handles[RADEON_MAX_VCE_HANDLES];
1638 struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
Alex Deucher03afe6f2013-08-23 11:56:26 -04001639 struct delayed_work idle_work;
Christian Königd93f7932013-05-23 12:10:04 +02001640};
1641
1642int radeon_vce_init(struct radeon_device *rdev);
1643void radeon_vce_fini(struct radeon_device *rdev);
1644int radeon_vce_suspend(struct radeon_device *rdev);
1645int radeon_vce_resume(struct radeon_device *rdev);
1646int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1647 uint32_t handle, struct radeon_fence **fence);
1648int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1649 uint32_t handle, struct radeon_fence **fence);
1650void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
Alex Deucher03afe6f2013-08-23 11:56:26 -04001651void radeon_vce_note_usage(struct radeon_device *rdev);
Christian Königd93f7932013-05-23 12:10:04 +02001652int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi);
1653int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1654bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1655 struct radeon_ring *ring,
1656 struct radeon_semaphore *semaphore,
1657 bool emit_wait);
1658void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1659void radeon_vce_fence_emit(struct radeon_device *rdev,
1660 struct radeon_fence *fence);
1661int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1662int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1663
Alex Deucherb5306022013-07-31 16:51:33 -04001664struct r600_audio_pin {
Rafał Miłeckia92553a2012-04-28 23:35:20 +02001665 int channels;
1666 int rate;
1667 int bits_per_sample;
1668 u8 status_bits;
1669 u8 category_code;
Alex Deucherb5306022013-07-31 16:51:33 -04001670 u32 offset;
1671 bool connected;
1672 u32 id;
1673};
1674
1675struct r600_audio {
1676 bool enabled;
1677 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1678 int num_pins;
Rafał Miłeckia92553a2012-04-28 23:35:20 +02001679};
1680
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001681/*
1682 * Benchmarking
1683 */
Ilija Hadzic638dd7d2011-10-12 23:29:39 -04001684void radeon_benchmark(struct radeon_device *rdev, int test_number);
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001685
1686
1687/*
Michel Dänzerecc0b322009-07-21 11:23:57 +02001688 * Testing
1689 */
1690void radeon_test_moves(struct radeon_device *rdev);
Christian König60a7e392011-09-27 12:31:00 +02001691void radeon_test_ring_sync(struct radeon_device *rdev,
Christian Könige32eb502011-10-23 12:56:27 +02001692 struct radeon_ring *cpA,
1693 struct radeon_ring *cpB);
Christian König60a7e392011-09-27 12:31:00 +02001694void radeon_test_syncing(struct radeon_device *rdev);
Michel Dänzerecc0b322009-07-21 11:23:57 +02001695
1696
1697/*
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001698 * Debugfs
1699 */
Christian König4d8bf9a2011-10-24 14:54:54 +02001700struct radeon_debugfs {
1701 struct drm_info_list *files;
1702 unsigned num_files;
1703};
1704
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001705int radeon_debugfs_add_files(struct radeon_device *rdev,
1706 struct drm_info_list *files,
1707 unsigned nfiles);
1708int radeon_debugfs_fence_init(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001709
Christian König76a0df82013-08-13 11:56:50 +02001710/*
1711 * ASIC ring specific functions.
1712 */
1713struct radeon_asic_ring {
1714 /* ring read/write ptr handling */
1715 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1716 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1717 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1718
1719 /* validating and patching of IBs */
1720 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1721 int (*cs_parse)(struct radeon_cs_parser *p);
1722
1723 /* command emmit functions */
1724 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1725 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
Christian König1654b812013-11-12 12:58:05 +01001726 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
Christian König76a0df82013-08-13 11:56:50 +02001727 struct radeon_semaphore *semaphore, bool emit_wait);
1728 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1729
1730 /* testing functions */
1731 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1732 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1733 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1734
1735 /* deprecated */
1736 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1737};
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001738
1739/*
1740 * ASIC specific functions.
1741 */
1742struct radeon_asic {
Jerome Glisse068a1172009-06-17 13:28:30 +02001743 int (*init)(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001744 void (*fini)(struct radeon_device *rdev);
1745 int (*resume)(struct radeon_device *rdev);
1746 int (*suspend)(struct radeon_device *rdev);
Dave Airlie28d52042009-09-21 14:33:58 +10001747 void (*vga_set_state)(struct radeon_device *rdev, bool state);
Jerome Glissea2d07b72010-03-09 14:45:11 +00001748 int (*asic_reset)(struct radeon_device *rdev);
Alex Deucher54e88e02012-02-23 18:10:29 -05001749 /* ioctl hw specific callback. Some hw might want to perform special
1750 * operation on specific ioctl. For instance on wait idle some hw
1751 * might want to perform and HDP flush through MMIO as it seems that
1752 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1753 * through ring.
1754 */
1755 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1756 /* check if 3D engine is idle */
1757 bool (*gui_idle)(struct radeon_device *rdev);
1758 /* wait for mc_idle */
1759 int (*mc_wait_for_idle)(struct radeon_device *rdev);
Alex Deucher454d2e22013-02-14 10:04:02 -05001760 /* get the reference clock */
1761 u32 (*get_xclk)(struct radeon_device *rdev);
Alex Deucherd0418892013-01-24 10:35:23 -05001762 /* get the gpu clock counter */
1763 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
Alex Deucher54e88e02012-02-23 18:10:29 -05001764 /* gart */
Alex Deucherc5b3b852012-02-23 17:53:46 -05001765 struct {
1766 void (*tlb_flush)(struct radeon_device *rdev);
1767 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1768 } gart;
Christian König05b07142012-08-06 20:21:10 +02001769 struct {
1770 int (*init)(struct radeon_device *rdev);
1771 void (*fini)(struct radeon_device *rdev);
Alex Deucher43f12142013-02-01 17:32:42 +01001772 void (*set_page)(struct radeon_device *rdev,
1773 struct radeon_ib *ib,
1774 uint64_t pe,
Christian Königdce34bf2012-09-17 19:36:18 +02001775 uint64_t addr, unsigned count,
1776 uint32_t incr, uint32_t flags);
Christian König05b07142012-08-06 20:21:10 +02001777 } vm;
Alex Deucher54e88e02012-02-23 18:10:29 -05001778 /* ring specific callbacks */
Christian König76a0df82013-08-13 11:56:50 +02001779 struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
Alex Deucher54e88e02012-02-23 18:10:29 -05001780 /* irqs */
Alex Deucherb35ea4a2012-02-23 17:53:43 -05001781 struct {
1782 int (*set)(struct radeon_device *rdev);
1783 int (*process)(struct radeon_device *rdev);
1784 } irq;
Alex Deucher54e88e02012-02-23 18:10:29 -05001785 /* displays */
Alex Deucherc79a49c2012-02-23 17:53:47 -05001786 struct {
1787 /* display watermarks */
1788 void (*bandwidth_update)(struct radeon_device *rdev);
1789 /* get frame count */
1790 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1791 /* wait for vblank */
1792 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
Alex Deucher37e9b6a2012-08-03 11:39:43 -04001793 /* set backlight level */
1794 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
Alex Deucher6d92f812012-09-14 09:59:26 -04001795 /* get backlight level */
1796 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
Alex Deuchera973bea2013-04-18 11:32:16 -04001797 /* audio callbacks */
1798 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1799 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
Alex Deucherc79a49c2012-02-23 17:53:47 -05001800 } display;
Alex Deucher54e88e02012-02-23 18:10:29 -05001801 /* copy functions for bo handling */
Alex Deucher27cd7762012-02-23 17:53:42 -05001802 struct {
1803 int (*blit)(struct radeon_device *rdev,
1804 uint64_t src_offset,
1805 uint64_t dst_offset,
1806 unsigned num_gpu_pages,
Christian König876dc9f2012-05-08 14:24:01 +02001807 struct radeon_fence **fence);
Alex Deucher27cd7762012-02-23 17:53:42 -05001808 u32 blit_ring_index;
1809 int (*dma)(struct radeon_device *rdev,
1810 uint64_t src_offset,
1811 uint64_t dst_offset,
1812 unsigned num_gpu_pages,
Christian König876dc9f2012-05-08 14:24:01 +02001813 struct radeon_fence **fence);
Alex Deucher27cd7762012-02-23 17:53:42 -05001814 u32 dma_ring_index;
1815 /* method used for bo copy */
1816 int (*copy)(struct radeon_device *rdev,
1817 uint64_t src_offset,
1818 uint64_t dst_offset,
1819 unsigned num_gpu_pages,
Christian König876dc9f2012-05-08 14:24:01 +02001820 struct radeon_fence **fence);
Alex Deucher27cd7762012-02-23 17:53:42 -05001821 /* ring used for bo copies */
1822 u32 copy_ring_index;
1823 } copy;
Alex Deucher54e88e02012-02-23 18:10:29 -05001824 /* surfaces */
Alex Deucher9e6f3d02012-02-23 17:53:49 -05001825 struct {
1826 int (*set_reg)(struct radeon_device *rdev, int reg,
1827 uint32_t tiling_flags, uint32_t pitch,
1828 uint32_t offset, uint32_t obj_size);
1829 void (*clear_reg)(struct radeon_device *rdev, int reg);
1830 } surface;
Alex Deucher54e88e02012-02-23 18:10:29 -05001831 /* hotplug detect */
Alex Deucher901ea572012-02-23 17:53:39 -05001832 struct {
1833 void (*init)(struct radeon_device *rdev);
1834 void (*fini)(struct radeon_device *rdev);
1835 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1836 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1837 } hpd;
Alex Deucherda321c82013-04-12 13:55:22 -04001838 /* static power management */
Alex Deuchera02fa392012-02-23 17:53:41 -05001839 struct {
1840 void (*misc)(struct radeon_device *rdev);
1841 void (*prepare)(struct radeon_device *rdev);
1842 void (*finish)(struct radeon_device *rdev);
1843 void (*init_profile)(struct radeon_device *rdev);
1844 void (*get_dynpm_state)(struct radeon_device *rdev);
Alex Deucher798bcf72012-02-23 17:53:48 -05001845 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1846 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1847 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1848 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1849 int (*get_pcie_lanes)(struct radeon_device *rdev);
1850 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1851 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
Alex Deucher73afc702013-04-08 12:41:30 +02001852 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
Alex Deucherb59b7332013-08-20 20:01:18 -04001853 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
Alex Deucher6bd1c382013-06-21 14:38:03 -04001854 int (*get_temperature)(struct radeon_device *rdev);
Alex Deuchera02fa392012-02-23 17:53:41 -05001855 } pm;
Alex Deucherda321c82013-04-12 13:55:22 -04001856 /* dynamic power management */
1857 struct {
1858 int (*init)(struct radeon_device *rdev);
1859 void (*setup_asic)(struct radeon_device *rdev);
1860 int (*enable)(struct radeon_device *rdev);
Alex Deucher914a8982013-12-19 11:37:22 -05001861 int (*late_enable)(struct radeon_device *rdev);
Alex Deucherda321c82013-04-12 13:55:22 -04001862 void (*disable)(struct radeon_device *rdev);
Alex Deucher84dd1922013-01-16 12:52:04 -05001863 int (*pre_set_power_state)(struct radeon_device *rdev);
Alex Deucherda321c82013-04-12 13:55:22 -04001864 int (*set_power_state)(struct radeon_device *rdev);
Alex Deucher84dd1922013-01-16 12:52:04 -05001865 void (*post_set_power_state)(struct radeon_device *rdev);
Alex Deucherda321c82013-04-12 13:55:22 -04001866 void (*display_configuration_changed)(struct radeon_device *rdev);
1867 void (*fini)(struct radeon_device *rdev);
1868 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1869 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1870 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
Alex Deucher1316b792013-06-28 09:28:39 -04001871 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
Alex Deucher70d01a52013-07-02 18:38:02 -04001872 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
Alex Deucher48783062013-07-08 11:35:06 -04001873 bool (*vblank_too_short)(struct radeon_device *rdev);
Alex Deucher9e9d9762013-07-31 18:13:23 -04001874 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
Alex Deucher1c71bda2013-09-09 19:11:52 -04001875 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
Alex Deucherda321c82013-04-12 13:55:22 -04001876 } dpm;
Alex Deucher6f34be52010-11-21 10:59:01 -05001877 /* pageflipping */
Alex Deucher0f9e0062012-02-23 17:53:40 -05001878 struct {
1879 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1880 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1881 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1882 } pflip;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001883};
1884
Jerome Glisse21f9a4372009-09-11 15:55:33 +02001885/*
1886 * Asic structures
1887 */
Dave Airlie551ebd82009-09-01 15:25:57 +10001888struct r100_asic {
Jerome Glisse225758d2010-03-09 14:45:10 +00001889 const unsigned *reg_safe_bm;
1890 unsigned reg_safe_bm_size;
1891 u32 hdp_cntl;
Dave Airlie551ebd82009-09-01 15:25:57 +10001892};
1893
Jerome Glisse21f9a4372009-09-11 15:55:33 +02001894struct r300_asic {
Jerome Glisse225758d2010-03-09 14:45:10 +00001895 const unsigned *reg_safe_bm;
1896 unsigned reg_safe_bm_size;
1897 u32 resync_scratch;
1898 u32 hdp_cntl;
Jerome Glisse21f9a4372009-09-11 15:55:33 +02001899};
1900
1901struct r600_asic {
Jerome Glisse225758d2010-03-09 14:45:10 +00001902 unsigned max_pipes;
1903 unsigned max_tile_pipes;
1904 unsigned max_simds;
1905 unsigned max_backends;
1906 unsigned max_gprs;
1907 unsigned max_threads;
1908 unsigned max_stack_entries;
1909 unsigned max_hw_contexts;
1910 unsigned max_gs_threads;
1911 unsigned sx_max_export_size;
1912 unsigned sx_max_export_pos_size;
1913 unsigned sx_max_export_smx_size;
1914 unsigned sq_num_cf_insts;
1915 unsigned tiling_nbanks;
1916 unsigned tiling_npipes;
1917 unsigned tiling_group_size;
Alex Deuchere7aeeba2010-06-04 13:10:12 -04001918 unsigned tile_config;
Alex Deuchere55b9422011-07-15 19:53:52 +00001919 unsigned backend_map;
Jerome Glisse21f9a4372009-09-11 15:55:33 +02001920};
1921
1922struct rv770_asic {
Jerome Glisse225758d2010-03-09 14:45:10 +00001923 unsigned max_pipes;
1924 unsigned max_tile_pipes;
1925 unsigned max_simds;
1926 unsigned max_backends;
1927 unsigned max_gprs;
1928 unsigned max_threads;
1929 unsigned max_stack_entries;
1930 unsigned max_hw_contexts;
1931 unsigned max_gs_threads;
1932 unsigned sx_max_export_size;
1933 unsigned sx_max_export_pos_size;
1934 unsigned sx_max_export_smx_size;
1935 unsigned sq_num_cf_insts;
1936 unsigned sx_num_of_sets;
1937 unsigned sc_prim_fifo_size;
1938 unsigned sc_hiz_tile_fifo_size;
1939 unsigned sc_earlyz_tile_fifo_fize;
1940 unsigned tiling_nbanks;
1941 unsigned tiling_npipes;
1942 unsigned tiling_group_size;
Alex Deuchere7aeeba2010-06-04 13:10:12 -04001943 unsigned tile_config;
Alex Deuchere55b9422011-07-15 19:53:52 +00001944 unsigned backend_map;
Jerome Glisse21f9a4372009-09-11 15:55:33 +02001945};
1946
Alex Deucher32fcdbf2010-03-24 13:33:47 -04001947struct evergreen_asic {
1948 unsigned num_ses;
1949 unsigned max_pipes;
1950 unsigned max_tile_pipes;
1951 unsigned max_simds;
1952 unsigned max_backends;
1953 unsigned max_gprs;
1954 unsigned max_threads;
1955 unsigned max_stack_entries;
1956 unsigned max_hw_contexts;
1957 unsigned max_gs_threads;
1958 unsigned sx_max_export_size;
1959 unsigned sx_max_export_pos_size;
1960 unsigned sx_max_export_smx_size;
1961 unsigned sq_num_cf_insts;
1962 unsigned sx_num_of_sets;
1963 unsigned sc_prim_fifo_size;
1964 unsigned sc_hiz_tile_fifo_size;
1965 unsigned sc_earlyz_tile_fifo_size;
1966 unsigned tiling_nbanks;
1967 unsigned tiling_npipes;
1968 unsigned tiling_group_size;
Alex Deuchere7aeeba2010-06-04 13:10:12 -04001969 unsigned tile_config;
Alex Deuchere55b9422011-07-15 19:53:52 +00001970 unsigned backend_map;
Alex Deucher32fcdbf2010-03-24 13:33:47 -04001971};
1972
Alex Deucherfecf1d02011-03-02 20:07:29 -05001973struct cayman_asic {
1974 unsigned max_shader_engines;
1975 unsigned max_pipes_per_simd;
1976 unsigned max_tile_pipes;
1977 unsigned max_simds_per_se;
1978 unsigned max_backends_per_se;
1979 unsigned max_texture_channel_caches;
1980 unsigned max_gprs;
1981 unsigned max_threads;
1982 unsigned max_gs_threads;
1983 unsigned max_stack_entries;
1984 unsigned sx_num_of_sets;
1985 unsigned sx_max_export_size;
1986 unsigned sx_max_export_pos_size;
1987 unsigned sx_max_export_smx_size;
1988 unsigned max_hw_contexts;
1989 unsigned sq_num_cf_insts;
1990 unsigned sc_prim_fifo_size;
1991 unsigned sc_hiz_tile_fifo_size;
1992 unsigned sc_earlyz_tile_fifo_size;
1993
1994 unsigned num_shader_engines;
1995 unsigned num_shader_pipes_per_simd;
1996 unsigned num_tile_pipes;
1997 unsigned num_simds_per_se;
1998 unsigned num_backends_per_se;
1999 unsigned backend_disable_mask_per_asic;
2000 unsigned backend_map;
2001 unsigned num_texture_channel_caches;
2002 unsigned mem_max_burst_length_bytes;
2003 unsigned mem_row_size_in_kb;
2004 unsigned shader_engine_tile_size;
2005 unsigned num_gpus;
2006 unsigned multi_gpu_tile_size;
2007
2008 unsigned tile_config;
Alex Deucherfecf1d02011-03-02 20:07:29 -05002009};
2010
Alex Deucher0a96d722012-03-20 17:18:11 -04002011struct si_asic {
2012 unsigned max_shader_engines;
Alex Deucher0a96d722012-03-20 17:18:11 -04002013 unsigned max_tile_pipes;
Alex Deucher1a8ca752012-06-01 18:58:22 -04002014 unsigned max_cu_per_sh;
2015 unsigned max_sh_per_se;
Alex Deucher0a96d722012-03-20 17:18:11 -04002016 unsigned max_backends_per_se;
2017 unsigned max_texture_channel_caches;
2018 unsigned max_gprs;
2019 unsigned max_gs_threads;
2020 unsigned max_hw_contexts;
2021 unsigned sc_prim_fifo_size_frontend;
2022 unsigned sc_prim_fifo_size_backend;
2023 unsigned sc_hiz_tile_fifo_size;
2024 unsigned sc_earlyz_tile_fifo_size;
2025
Alex Deucher0a96d722012-03-20 17:18:11 -04002026 unsigned num_tile_pipes;
Marek Olšák439a1cf2013-12-22 02:18:01 +01002027 unsigned backend_enable_mask;
Alex Deucher0a96d722012-03-20 17:18:11 -04002028 unsigned backend_disable_mask_per_asic;
2029 unsigned backend_map;
2030 unsigned num_texture_channel_caches;
2031 unsigned mem_max_burst_length_bytes;
2032 unsigned mem_row_size_in_kb;
2033 unsigned shader_engine_tile_size;
2034 unsigned num_gpus;
2035 unsigned multi_gpu_tile_size;
2036
2037 unsigned tile_config;
Jerome Glisse64d7b8b2013-04-09 11:17:08 -04002038 uint32_t tile_mode_array[32];
Alex Deucher0a96d722012-03-20 17:18:11 -04002039};
2040
Alex Deucher8cc1a532013-04-09 12:41:24 -04002041struct cik_asic {
2042 unsigned max_shader_engines;
2043 unsigned max_tile_pipes;
2044 unsigned max_cu_per_sh;
2045 unsigned max_sh_per_se;
2046 unsigned max_backends_per_se;
2047 unsigned max_texture_channel_caches;
2048 unsigned max_gprs;
2049 unsigned max_gs_threads;
2050 unsigned max_hw_contexts;
2051 unsigned sc_prim_fifo_size_frontend;
2052 unsigned sc_prim_fifo_size_backend;
2053 unsigned sc_hiz_tile_fifo_size;
2054 unsigned sc_earlyz_tile_fifo_size;
2055
2056 unsigned num_tile_pipes;
Marek Olšák439a1cf2013-12-22 02:18:01 +01002057 unsigned backend_enable_mask;
Alex Deucher8cc1a532013-04-09 12:41:24 -04002058 unsigned backend_disable_mask_per_asic;
2059 unsigned backend_map;
2060 unsigned num_texture_channel_caches;
2061 unsigned mem_max_burst_length_bytes;
2062 unsigned mem_row_size_in_kb;
2063 unsigned shader_engine_tile_size;
2064 unsigned num_gpus;
2065 unsigned multi_gpu_tile_size;
2066
2067 unsigned tile_config;
Alex Deucher39aee492013-04-10 13:41:25 -04002068 uint32_t tile_mode_array[32];
Michel Dänzer32f79a82013-11-18 18:26:00 +09002069 uint32_t macrotile_mode_array[16];
Alex Deucher8cc1a532013-04-09 12:41:24 -04002070};
2071
Jerome Glisse068a1172009-06-17 13:28:30 +02002072union radeon_asic_config {
2073 struct r300_asic r300;
Dave Airlie551ebd82009-09-01 15:25:57 +10002074 struct r100_asic r100;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002075 struct r600_asic r600;
2076 struct rv770_asic rv770;
Alex Deucher32fcdbf2010-03-24 13:33:47 -04002077 struct evergreen_asic evergreen;
Alex Deucherfecf1d02011-03-02 20:07:29 -05002078 struct cayman_asic cayman;
Alex Deucher0a96d722012-03-20 17:18:11 -04002079 struct si_asic si;
Alex Deucher8cc1a532013-04-09 12:41:24 -04002080 struct cik_asic cik;
Jerome Glisse068a1172009-06-17 13:28:30 +02002081};
2082
Daniel Vetter0a10c852010-03-11 21:19:14 +00002083/*
2084 * asic initizalization from radeon_asic.c
2085 */
2086void radeon_agp_disable(struct radeon_device *rdev);
2087int radeon_asic_init(struct radeon_device *rdev);
2088
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002089
2090/*
2091 * IOCTL.
2092 */
2093int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2094 struct drm_file *filp);
2095int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2096 struct drm_file *filp);
2097int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2098 struct drm_file *file_priv);
2099int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2100 struct drm_file *file_priv);
2101int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2102 struct drm_file *file_priv);
2103int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2104 struct drm_file *file_priv);
2105int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2106 struct drm_file *filp);
2107int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2108 struct drm_file *filp);
2109int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2110 struct drm_file *filp);
2111int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2112 struct drm_file *filp);
Jerome Glisse721604a2012-01-05 22:11:05 -05002113int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2114 struct drm_file *filp);
Marek Olšákbda72d52014-03-02 00:56:17 +01002115int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2116 struct drm_file *filp);
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002117int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
Dave Airliee024e112009-06-24 09:48:08 +10002118int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2119 struct drm_file *filp);
2120int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2121 struct drm_file *filp);
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002122
Alex Deucher16cdf042011-10-28 10:30:02 -04002123/* VRAM scratch page for HDP bug, default vram page */
2124struct r600_vram_scratch {
Alex Deucher87cbf8f2010-08-27 13:59:54 -04002125 struct radeon_bo *robj;
2126 volatile uint32_t *ptr;
Alex Deucher16cdf042011-10-28 10:30:02 -04002127 u64 gpu_addr;
Alex Deucher87cbf8f2010-08-27 13:59:54 -04002128};
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002129
Luca Tettamantifd64ca82012-08-16 11:11:18 -04002130/*
2131 * ACPI
2132 */
2133struct radeon_atif_notification_cfg {
2134 bool enabled;
2135 int command_code;
2136};
2137
2138struct radeon_atif_notifications {
2139 bool display_switch;
2140 bool expansion_mode_change;
2141 bool thermal_state;
2142 bool forced_power_state;
2143 bool system_power_state;
2144 bool display_conf_change;
2145 bool px_gfx_switch;
2146 bool brightness_change;
2147 bool dgpu_display_event;
2148};
2149
2150struct radeon_atif_functions {
2151 bool system_params;
2152 bool sbios_requests;
2153 bool select_active_disp;
2154 bool lid_state;
2155 bool get_tv_standard;
2156 bool set_tv_standard;
2157 bool get_panel_expansion_mode;
2158 bool set_panel_expansion_mode;
2159 bool temperature_change;
2160 bool graphics_device_types;
2161};
2162
2163struct radeon_atif {
2164 struct radeon_atif_notifications notifications;
2165 struct radeon_atif_functions functions;
2166 struct radeon_atif_notification_cfg notification_cfg;
Alex Deucher37e9b6a2012-08-03 11:39:43 -04002167 struct radeon_encoder *encoder_for_bl;
Luca Tettamantifd64ca82012-08-16 11:11:18 -04002168};
Michel Dänzer7a1619b2011-11-10 18:57:26 +01002169
Alex Deuchere3a15922012-08-16 11:13:43 -04002170struct radeon_atcs_functions {
2171 bool get_ext_state;
2172 bool pcie_perf_req;
2173 bool pcie_dev_rdy;
2174 bool pcie_bus_width;
2175};
2176
2177struct radeon_atcs {
2178 struct radeon_atcs_functions functions;
2179};
2180
Michel Dänzer7a1619b2011-11-10 18:57:26 +01002181/*
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002182 * Core structure, functions and helpers.
2183 */
2184typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2185typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2186
2187struct radeon_device {
Jerome Glisse9f022dd2009-09-11 15:35:22 +02002188 struct device *dev;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002189 struct drm_device *ddev;
2190 struct pci_dev *pdev;
Jerome Glissedee53e72012-07-02 12:45:19 -04002191 struct rw_semaphore exclusive_lock;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002192 /* ASIC */
Jerome Glisse068a1172009-06-17 13:28:30 +02002193 union radeon_asic_config config;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002194 enum radeon_family family;
2195 unsigned long flags;
2196 int usec_timeout;
2197 enum radeon_pll_errata pll_errata;
2198 int num_gb_pipes;
Alex Deucherf779b3e2009-08-19 19:11:39 -04002199 int num_z_pipes;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002200 int disp_priority;
2201 /* BIOS */
2202 uint8_t *bios;
2203 bool is_atom_bios;
2204 uint16_t bios_header_start;
Jerome Glisse4c788672009-11-20 14:29:23 +01002205 struct radeon_bo *stollen_vga_memory;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002206 /* Register mmio */
Dave Airlie4c9bc752009-06-29 18:29:12 +10002207 resource_size_t rmmio_base;
2208 resource_size_t rmmio_size;
Daniel Vetter2c385152012-12-02 14:06:15 +01002209 /* protects concurrent MM_INDEX/DATA based register access */
2210 spinlock_t mmio_idx_lock;
Alex Deucherfe781182013-09-03 18:19:42 -04002211 /* protects concurrent SMC based register access */
2212 spinlock_t smc_idx_lock;
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002213 /* protects concurrent PLL register access */
2214 spinlock_t pll_idx_lock;
2215 /* protects concurrent MC register access */
2216 spinlock_t mc_idx_lock;
2217 /* protects concurrent PCIE register access */
2218 spinlock_t pcie_idx_lock;
2219 /* protects concurrent PCIE_PORT register access */
2220 spinlock_t pciep_idx_lock;
2221 /* protects concurrent PIF register access */
2222 spinlock_t pif_idx_lock;
2223 /* protects concurrent CG register access */
2224 spinlock_t cg_idx_lock;
2225 /* protects concurrent UVD register access */
2226 spinlock_t uvd_idx_lock;
2227 /* protects concurrent RCU register access */
2228 spinlock_t rcu_idx_lock;
2229 /* protects concurrent DIDT register access */
2230 spinlock_t didt_idx_lock;
2231 /* protects concurrent ENDPOINT (audio) register access */
2232 spinlock_t end_idx_lock;
Benjamin Herrenschmidta0533fb2011-07-13 06:28:12 +00002233 void __iomem *rmmio;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002234 radeon_rreg_t mc_rreg;
2235 radeon_wreg_t mc_wreg;
2236 radeon_rreg_t pll_rreg;
2237 radeon_wreg_t pll_wreg;
Dave Airliede1b2892009-08-12 18:43:14 +10002238 uint32_t pcie_reg_mask;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002239 radeon_rreg_t pciep_rreg;
2240 radeon_wreg_t pciep_wreg;
Alex Deucher351a52a2010-06-30 11:52:50 -04002241 /* io port */
2242 void __iomem *rio_mem;
2243 resource_size_t rio_mem_size;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002244 struct radeon_clock clock;
2245 struct radeon_mc mc;
2246 struct radeon_gart gart;
2247 struct radeon_mode_info mode_info;
2248 struct radeon_scratch scratch;
Alex Deucher75efdee2013-03-04 12:47:46 -05002249 struct radeon_doorbell doorbell;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002250 struct radeon_mman mman;
Alex Deucher74652802011-08-25 13:39:48 -04002251 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
Jerome Glisse0085c9502012-05-09 15:34:55 +02002252 wait_queue_head_t fence_queue;
Christian Königd6999bc2012-05-09 15:34:45 +02002253 struct mutex ring_lock;
Christian Könige32eb502011-10-23 12:56:27 +02002254 struct radeon_ring ring[RADEON_NUM_RINGS];
Jerome Glissec507f7e2012-05-09 15:34:58 +02002255 bool ib_pool_ready;
2256 struct radeon_sa_manager ring_tmp_bo;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002257 struct radeon_irq irq;
2258 struct radeon_asic *asic;
2259 struct radeon_gem gem;
Jerome Glissec93bb852009-07-13 21:04:08 +02002260 struct radeon_pm pm;
Christian Königf2ba57b2013-04-08 12:41:29 +02002261 struct radeon_uvd uvd;
Christian Königd93f7932013-05-23 12:10:04 +02002262 struct radeon_vce vce;
Yang Zhaof657c2a2009-09-15 12:21:01 +10002263 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002264 struct radeon_wb wb;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002265 struct radeon_dummy_page dummy_page;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002266 bool shutdown;
2267 bool suspend;
Dave Airliead49f502009-07-10 22:36:26 +10002268 bool need_dma32;
Jerome Glisse733289c2009-09-16 15:24:21 +02002269 bool accel_working;
Samuel Lia0a53aa2013-04-08 17:25:47 -04002270 bool fastfb_working; /* IGP feature*/
Christian Königf9eaf9a2013-10-29 20:14:47 +01002271 bool needs_reset;
Dave Airliee024e112009-06-24 09:48:08 +10002272 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002273 const struct firmware *me_fw; /* all family ME firmware */
2274 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
Alex Deucherd8f60cf2009-12-01 13:43:46 -05002275 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
Alex Deucher0af62b02011-01-06 21:19:31 -05002276 const struct firmware *mc_fw; /* NI MC firmware */
Alex Deucher0f0de062012-03-20 17:18:17 -04002277 const struct firmware *ce_fw; /* SI CE firmware */
Alex Deucher02c81322012-12-18 21:43:07 -05002278 const struct firmware *mec_fw; /* CIK MEC firmware */
Alex Deucher21a93e12013-04-09 12:47:11 -04002279 const struct firmware *sdma_fw; /* CIK SDMA firmware */
Alex Deucher66229b22013-06-26 00:11:19 -04002280 const struct firmware *smc_fw; /* SMC firmware */
Christian König4ad9c1c2013-08-05 14:10:55 +02002281 const struct firmware *uvd_fw; /* UVD firmware */
Christian Königd93f7932013-05-23 12:10:04 +02002282 const struct firmware *vce_fw; /* VCE firmware */
Alex Deucher16cdf042011-10-28 10:30:02 -04002283 struct r600_vram_scratch vram_scratch;
Alex Deucher3e5cb982009-10-16 12:21:24 -04002284 int msi_enabled; /* msi enabled */
Alex Deucherd8f60cf2009-12-01 13:43:46 -05002285 struct r600_ih ih; /* r6/700 interrupt ring */
Alex Deucher2948f5e2013-04-12 13:52:52 -04002286 struct radeon_rlc rlc;
Alex Deucher963e81f2013-06-26 17:37:11 -04002287 struct radeon_mec mec;
Alex Deucherd4877cf2009-12-04 16:56:37 -05002288 struct work_struct hotplug_work;
Alex Deucherf122c612012-03-30 08:59:57 -04002289 struct work_struct audio_work;
Alex Deucher8f61b342013-06-14 09:13:52 -04002290 struct work_struct reset_work;
Alex Deucher18917b62010-02-01 16:02:25 -05002291 int num_crtc; /* number of crtcs */
Alex Deucher40bacf12009-12-23 03:23:21 -05002292 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
Alex Deucher948bee32013-05-14 12:08:35 -04002293 bool has_uvd;
Alex Deucherb5306022013-07-31 16:51:33 -04002294 struct r600_audio audio; /* audio stuff */
Alex Deucherce8f5372010-05-07 15:10:16 -04002295 struct notifier_block acpi_nb;
Marek Olšák9eba4a92011-01-05 05:46:48 +01002296 /* only one userspace can use Hyperz features or CMASK at a time */
Dave Airlieab9e1f52010-07-13 11:11:11 +10002297 struct drm_file *hyperz_filp;
Marek Olšák9eba4a92011-01-05 05:46:48 +01002298 struct drm_file *cmask_filp;
Alex Deucherf376b942010-08-05 21:21:16 -04002299 /* i2c buses */
2300 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
Christian König4d8bf9a2011-10-24 14:54:54 +02002301 /* debugfs */
2302 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2303 unsigned debugfs_count;
Jerome Glisse721604a2012-01-05 22:11:05 -05002304 /* virtual memory */
2305 struct radeon_vm_manager vm_manager;
Marek Olšák6759a0a2012-08-09 16:34:17 +02002306 struct mutex gpu_clock_mutex;
Marek Olšák67e8e3f2014-03-02 00:56:18 +01002307 /* memory stats */
2308 atomic64_t vram_usage;
2309 atomic64_t gtt_usage;
2310 atomic64_t num_bytes_moved;
Luca Tettamantifd64ca82012-08-16 11:11:18 -04002311 /* ACPI interface */
2312 struct radeon_atif atif;
Alex Deuchere3a15922012-08-16 11:13:43 -04002313 struct radeon_atcs atcs;
Alex Deucherf61d5b462013-08-06 12:40:16 -04002314 /* srbm instance registers */
2315 struct mutex srbm_mutex;
Alex Deucher64d8a722013-08-08 16:31:25 -04002316 /* clock, powergating flags */
2317 u32 cg_flags;
2318 u32 pg_flags;
Dave Airlie10ebc0b2012-09-17 14:40:31 +10002319
2320 struct dev_pm_domain vga_pm_domain;
2321 bool have_disp_power_ref;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002322};
2323
Alex Deucher90c4cde2014-04-10 22:29:01 -04002324bool radeon_is_px(struct drm_device *dev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002325int radeon_device_init(struct radeon_device *rdev,
2326 struct drm_device *ddev,
2327 struct pci_dev *pdev,
2328 uint32_t flags);
2329void radeon_device_fini(struct radeon_device *rdev);
2330int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2331
Daniel Vetter2ef9bdf2012-12-02 14:02:51 +01002332uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2333 bool always_indirect);
2334void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2335 bool always_indirect);
Andi Kleen6fcbef72011-10-13 16:08:42 -07002336u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2337void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
Alex Deucher351a52a2010-06-30 11:52:50 -04002338
Andrew Lewyckyd5754ab2013-11-13 15:54:17 -05002339u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2340void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
Alex Deucher75efdee2013-03-04 12:47:46 -05002341
Jerome Glisse4c788672009-11-20 14:29:23 +01002342/*
2343 * Cast helper
2344 */
2345#define to_radeon_fence(p) ((struct radeon_fence *)(p))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002346
2347/*
2348 * Registers read & write functions.
2349 */
Benjamin Herrenschmidta0533fb2011-07-13 06:28:12 +00002350#define RREG8(reg) readb((rdev->rmmio) + (reg))
2351#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2352#define RREG16(reg) readw((rdev->rmmio) + (reg))
2353#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
Daniel Vetter2ef9bdf2012-12-02 14:02:51 +01002354#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2355#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2356#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2357#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2358#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002359#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2360#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2361#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2362#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2363#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2364#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
Dave Airliede1b2892009-08-12 18:43:14 +10002365#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2366#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
Alex Deucher492d2b62012-10-25 16:06:59 -04002367#define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2368#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
Alex Deucher1d5d0c32012-04-20 12:39:49 -04002369#define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2370#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
Alex Deucherff82bbc2013-04-12 11:27:20 -04002371#define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2372#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
Alex Deucher46f95642013-04-12 11:49:51 -04002373#define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2374#define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
Alex Deucher792edd62013-02-14 18:18:12 -05002375#define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2376#define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2377#define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2378#define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
Alex Deucher93656cd2013-02-25 15:18:39 -05002379#define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2380#define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
Alex Deucher1d582342013-04-19 13:03:37 -04002381#define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2382#define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002383#define WREG32_P(reg, val, mask) \
2384 do { \
2385 uint32_t tmp_ = RREG32(reg); \
2386 tmp_ &= (mask); \
2387 tmp_ |= ((val) & ~(mask)); \
2388 WREG32(reg, tmp_); \
2389 } while (0)
Rafał Miłeckid5169fc2013-04-14 01:26:19 +02002390#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
Rafał Miłeckid43a93c2013-08-15 18:55:22 +02002391#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002392#define WREG32_PLL_P(reg, val, mask) \
2393 do { \
2394 uint32_t tmp_ = RREG32_PLL(reg); \
2395 tmp_ &= (mask); \
2396 tmp_ |= ((val) & ~(mask)); \
2397 WREG32_PLL(reg, tmp_); \
2398 } while (0)
Daniel Vetter2ef9bdf2012-12-02 14:02:51 +01002399#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
Alex Deucher351a52a2010-06-30 11:52:50 -04002400#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2401#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002402
Andrew Lewyckyd5754ab2013-11-13 15:54:17 -05002403#define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2404#define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
Alex Deucher75efdee2013-03-04 12:47:46 -05002405
Dave Airliede1b2892009-08-12 18:43:14 +10002406/*
2407 * Indirect registers accessor
2408 */
2409static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2410{
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002411 unsigned long flags;
Dave Airliede1b2892009-08-12 18:43:14 +10002412 uint32_t r;
2413
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002414 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
Dave Airliede1b2892009-08-12 18:43:14 +10002415 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2416 r = RREG32(RADEON_PCIE_DATA);
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002417 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
Dave Airliede1b2892009-08-12 18:43:14 +10002418 return r;
2419}
2420
2421static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2422{
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002423 unsigned long flags;
2424
2425 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
Dave Airliede1b2892009-08-12 18:43:14 +10002426 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2427 WREG32(RADEON_PCIE_DATA, (v));
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002428 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
Dave Airliede1b2892009-08-12 18:43:14 +10002429}
2430
Alex Deucher1d5d0c32012-04-20 12:39:49 -04002431static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2432{
Alex Deucherfe781182013-09-03 18:19:42 -04002433 unsigned long flags;
Alex Deucher1d5d0c32012-04-20 12:39:49 -04002434 u32 r;
2435
Alex Deucherfe781182013-09-03 18:19:42 -04002436 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
Alex Deucher1d5d0c32012-04-20 12:39:49 -04002437 WREG32(TN_SMC_IND_INDEX_0, (reg));
2438 r = RREG32(TN_SMC_IND_DATA_0);
Alex Deucherfe781182013-09-03 18:19:42 -04002439 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
Alex Deucher1d5d0c32012-04-20 12:39:49 -04002440 return r;
2441}
2442
2443static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2444{
Alex Deucherfe781182013-09-03 18:19:42 -04002445 unsigned long flags;
2446
2447 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
Alex Deucher1d5d0c32012-04-20 12:39:49 -04002448 WREG32(TN_SMC_IND_INDEX_0, (reg));
2449 WREG32(TN_SMC_IND_DATA_0, (v));
Alex Deucherfe781182013-09-03 18:19:42 -04002450 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
Alex Deucher1d5d0c32012-04-20 12:39:49 -04002451}
2452
Alex Deucherff82bbc2013-04-12 11:27:20 -04002453static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2454{
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002455 unsigned long flags;
Alex Deucherff82bbc2013-04-12 11:27:20 -04002456 u32 r;
2457
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002458 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
Alex Deucherff82bbc2013-04-12 11:27:20 -04002459 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2460 r = RREG32(R600_RCU_DATA);
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002461 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
Alex Deucherff82bbc2013-04-12 11:27:20 -04002462 return r;
2463}
2464
2465static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2466{
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002467 unsigned long flags;
2468
2469 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
Alex Deucherff82bbc2013-04-12 11:27:20 -04002470 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2471 WREG32(R600_RCU_DATA, (v));
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002472 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
Alex Deucherff82bbc2013-04-12 11:27:20 -04002473}
2474
Alex Deucher46f95642013-04-12 11:49:51 -04002475static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2476{
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002477 unsigned long flags;
Alex Deucher46f95642013-04-12 11:49:51 -04002478 u32 r;
2479
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002480 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
Alex Deucher46f95642013-04-12 11:49:51 -04002481 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2482 r = RREG32(EVERGREEN_CG_IND_DATA);
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002483 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
Alex Deucher46f95642013-04-12 11:49:51 -04002484 return r;
2485}
2486
2487static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2488{
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002489 unsigned long flags;
2490
2491 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
Alex Deucher46f95642013-04-12 11:49:51 -04002492 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2493 WREG32(EVERGREEN_CG_IND_DATA, (v));
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002494 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
Alex Deucher46f95642013-04-12 11:49:51 -04002495}
2496
Alex Deucher792edd62013-02-14 18:18:12 -05002497static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2498{
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002499 unsigned long flags;
Alex Deucher792edd62013-02-14 18:18:12 -05002500 u32 r;
2501
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002502 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
Alex Deucher792edd62013-02-14 18:18:12 -05002503 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2504 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002505 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
Alex Deucher792edd62013-02-14 18:18:12 -05002506 return r;
2507}
2508
2509static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2510{
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002511 unsigned long flags;
2512
2513 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
Alex Deucher792edd62013-02-14 18:18:12 -05002514 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2515 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002516 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
Alex Deucher792edd62013-02-14 18:18:12 -05002517}
2518
2519static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2520{
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002521 unsigned long flags;
Alex Deucher792edd62013-02-14 18:18:12 -05002522 u32 r;
2523
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002524 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
Alex Deucher792edd62013-02-14 18:18:12 -05002525 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2526 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002527 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
Alex Deucher792edd62013-02-14 18:18:12 -05002528 return r;
2529}
2530
2531static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2532{
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002533 unsigned long flags;
2534
2535 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
Alex Deucher792edd62013-02-14 18:18:12 -05002536 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2537 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002538 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
Alex Deucher792edd62013-02-14 18:18:12 -05002539}
2540
Alex Deucher93656cd2013-02-25 15:18:39 -05002541static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2542{
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002543 unsigned long flags;
Alex Deucher93656cd2013-02-25 15:18:39 -05002544 u32 r;
2545
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002546 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
Alex Deucher93656cd2013-02-25 15:18:39 -05002547 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2548 r = RREG32(R600_UVD_CTX_DATA);
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002549 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
Alex Deucher93656cd2013-02-25 15:18:39 -05002550 return r;
2551}
2552
2553static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2554{
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002555 unsigned long flags;
2556
2557 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
Alex Deucher93656cd2013-02-25 15:18:39 -05002558 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2559 WREG32(R600_UVD_CTX_DATA, (v));
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002560 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
Alex Deucher93656cd2013-02-25 15:18:39 -05002561}
2562
Alex Deucher1d582342013-04-19 13:03:37 -04002563
2564static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
2565{
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002566 unsigned long flags;
Alex Deucher1d582342013-04-19 13:03:37 -04002567 u32 r;
2568
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002569 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
Alex Deucher1d582342013-04-19 13:03:37 -04002570 WREG32(CIK_DIDT_IND_INDEX, (reg));
2571 r = RREG32(CIK_DIDT_IND_DATA);
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002572 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
Alex Deucher1d582342013-04-19 13:03:37 -04002573 return r;
2574}
2575
2576static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2577{
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002578 unsigned long flags;
2579
2580 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
Alex Deucher1d582342013-04-19 13:03:37 -04002581 WREG32(CIK_DIDT_IND_INDEX, (reg));
2582 WREG32(CIK_DIDT_IND_DATA, (v));
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002583 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
Alex Deucher1d582342013-04-19 13:03:37 -04002584}
2585
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002586void r100_pll_errata_after_index(struct radeon_device *rdev);
2587
2588
2589/*
2590 * ASICs helpers.
2591 */
Dave Airlieb995e432009-07-14 02:02:32 +10002592#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2593 (rdev->pdev->device == 0x5969))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002594#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2595 (rdev->family == CHIP_RV200) || \
2596 (rdev->family == CHIP_RS100) || \
2597 (rdev->family == CHIP_RS200) || \
2598 (rdev->family == CHIP_RV250) || \
2599 (rdev->family == CHIP_RV280) || \
2600 (rdev->family == CHIP_RS300))
2601#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2602 (rdev->family == CHIP_RV350) || \
2603 (rdev->family == CHIP_R350) || \
2604 (rdev->family == CHIP_RV380) || \
2605 (rdev->family == CHIP_R420) || \
2606 (rdev->family == CHIP_R423) || \
2607 (rdev->family == CHIP_RV410) || \
2608 (rdev->family == CHIP_RS400) || \
2609 (rdev->family == CHIP_RS480))
Alex Deucher3313e3d2011-01-06 18:49:34 -05002610#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2611 (rdev->ddev->pdev->device == 0x9443) || \
2612 (rdev->ddev->pdev->device == 0x944B) || \
2613 (rdev->ddev->pdev->device == 0x9506) || \
2614 (rdev->ddev->pdev->device == 0x9509) || \
2615 (rdev->ddev->pdev->device == 0x950F) || \
2616 (rdev->ddev->pdev->device == 0x689C) || \
2617 (rdev->ddev->pdev->device == 0x689D))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002618#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
Alex Deucher99999aa2010-11-16 12:09:41 -05002619#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2620 (rdev->family == CHIP_RS690) || \
2621 (rdev->family == CHIP_RS740) || \
2622 (rdev->family >= CHIP_R600))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002623#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2624#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
Alex Deucherbcc1c2a2010-01-12 17:54:34 -05002625#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
Alex Deucher633b9162011-01-06 21:19:11 -05002626#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2627 (rdev->flags & RADEON_IS_IGP))
Alex Deucher1fe18302011-01-06 21:19:12 -05002628#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
Alex Deucher8848f752012-03-20 17:18:28 -04002629#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2630#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2631 (rdev->flags & RADEON_IS_IGP))
Alex Deucher624d3522012-12-18 17:01:35 -05002632#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
Alex Deucherb5d9d722012-07-26 18:53:55 -04002633#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
Alex Deuchere2829172013-06-07 11:37:11 -04002634#define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
Alex Deucherbe0949f2014-04-08 11:28:54 -04002635#define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2636#define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
2637#define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002638
Alex Deucherdc50ba72013-06-26 00:33:35 -04002639#define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2640 (rdev->ddev->pdev->device == 0x6850) || \
2641 (rdev->ddev->pdev->device == 0x6858) || \
2642 (rdev->ddev->pdev->device == 0x6859) || \
2643 (rdev->ddev->pdev->device == 0x6840) || \
2644 (rdev->ddev->pdev->device == 0x6841) || \
2645 (rdev->ddev->pdev->device == 0x6842) || \
2646 (rdev->ddev->pdev->device == 0x6843))
2647
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002648/*
2649 * BIOS helpers.
2650 */
2651#define RBIOS8(i) (rdev->bios[i])
2652#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2653#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2654
2655int radeon_combios_init(struct radeon_device *rdev);
2656void radeon_combios_fini(struct radeon_device *rdev);
2657int radeon_atombios_init(struct radeon_device *rdev);
2658void radeon_atombios_fini(struct radeon_device *rdev);
2659
2660
2661/*
2662 * RING helpers.
2663 */
Andi Kleence580fa2011-10-13 16:08:47 -07002664#if DRM_DEBUG_CODE == 0
Christian Könige32eb502011-10-23 12:56:27 +02002665static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002666{
Christian Könige32eb502011-10-23 12:56:27 +02002667 ring->ring[ring->wptr++] = v;
2668 ring->wptr &= ring->ptr_mask;
2669 ring->count_dw--;
2670 ring->ring_free_dw--;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002671}
Andi Kleence580fa2011-10-13 16:08:47 -07002672#else
2673/* With debugging this is just too big to inline */
Christian Könige32eb502011-10-23 12:56:27 +02002674void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
Andi Kleence580fa2011-10-13 16:08:47 -07002675#endif
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002676
2677/*
2678 * ASICs macro.
2679 */
Jerome Glisse068a1172009-06-17 13:28:30 +02002680#define radeon_init(rdev) (rdev)->asic->init((rdev))
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002681#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2682#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2683#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
Christian König76a0df82013-08-13 11:56:50 +02002684#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
Dave Airlie28d52042009-09-21 14:33:58 +10002685#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
Jerome Glissea2d07b72010-03-09 14:45:11 +00002686#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
Alex Deucherc5b3b852012-02-23 17:53:46 -05002687#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2688#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
Christian König05b07142012-08-06 20:21:10 +02002689#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2690#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
Alex Deucher43f12142013-02-01 17:32:42 +01002691#define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
Christian König76a0df82013-08-13 11:56:50 +02002692#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2693#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2694#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2695#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2696#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2697#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2698#define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm))
2699#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2700#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2701#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
Alex Deucherb35ea4a2012-02-23 17:53:43 -05002702#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2703#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
Alex Deucherc79a49c2012-02-23 17:53:47 -05002704#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
Alex Deucher37e9b6a2012-08-03 11:39:43 -04002705#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
Alex Deucher6d92f812012-09-14 09:59:26 -04002706#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
Alex Deuchera973bea2013-04-18 11:32:16 -04002707#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2708#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
Christian König76a0df82013-08-13 11:56:50 +02002709#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2710#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
Alex Deucher27cd7762012-02-23 17:53:42 -05002711#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2712#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2713#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
2714#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2715#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2716#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
Alex Deucher798bcf72012-02-23 17:53:48 -05002717#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2718#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2719#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2720#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2721#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2722#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2723#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
Alex Deucher73afc702013-04-08 12:41:30 +02002724#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
Alex Deucherb59b7332013-08-20 20:01:18 -04002725#define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
Alex Deucher6bd1c382013-06-21 14:38:03 -04002726#define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
Alex Deucher9e6f3d02012-02-23 17:53:49 -05002727#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2728#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
Alex Deucherc79a49c2012-02-23 17:53:47 -05002729#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
Alex Deucher901ea572012-02-23 17:53:39 -05002730#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2731#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2732#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2733#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
Alex Deucherdef9ba92010-04-22 12:39:58 -04002734#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
Alex Deuchera02fa392012-02-23 17:53:41 -05002735#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2736#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2737#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2738#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2739#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
Alex Deucher69b62ad2012-08-03 11:50:54 -04002740#define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc))
2741#define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2742#define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc))
2743#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2744#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
Alex Deucher454d2e22013-02-14 10:04:02 -05002745#define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
Alex Deucherd0418892013-01-24 10:35:23 -05002746#define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
Alex Deucherda321c82013-04-12 13:55:22 -04002747#define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2748#define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2749#define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
Alex Deucher914a8982013-12-19 11:37:22 -05002750#define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
Alex Deucherda321c82013-04-12 13:55:22 -04002751#define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
Alex Deucher84dd1922013-01-16 12:52:04 -05002752#define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
Alex Deucherda321c82013-04-12 13:55:22 -04002753#define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
Alex Deucher84dd1922013-01-16 12:52:04 -05002754#define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
Alex Deucherda321c82013-04-12 13:55:22 -04002755#define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2756#define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2757#define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2758#define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2759#define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
Alex Deucher1316b792013-06-28 09:28:39 -04002760#define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
Alex Deucher70d01a52013-07-02 18:38:02 -04002761#define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
Alex Deucher48783062013-07-08 11:35:06 -04002762#define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
Alex Deucher9e9d9762013-07-31 18:13:23 -04002763#define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
Alex Deucher1c71bda2013-09-09 19:11:52 -04002764#define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002765
Jerome Glisse6cf8a3f2009-09-10 21:46:48 +02002766/* Common functions */
Jerome Glisse700a0cc2010-01-13 15:16:38 +01002767/* AGP */
Jerome Glisse90aca4d2010-03-09 14:45:12 +00002768extern int radeon_gpu_reset(struct radeon_device *rdev);
Alex Deucher1a0041b2013-10-02 13:01:36 -04002769extern void radeon_pci_config_reset(struct radeon_device *rdev);
Alex Deucher410a3412013-01-18 13:05:39 -05002770extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
Jerome Glisse700a0cc2010-01-13 15:16:38 +01002771extern void radeon_agp_disable(struct radeon_device *rdev);
Jerome Glisse21f9a4372009-09-11 15:55:33 +02002772extern int radeon_modeset_init(struct radeon_device *rdev);
2773extern void radeon_modeset_fini(struct radeon_device *rdev);
Jerome Glisse9f022dd2009-09-11 15:35:22 +02002774extern bool radeon_card_posted(struct radeon_device *rdev);
Alex Deucherf47299c2010-03-16 20:54:38 -04002775extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
Alex Deucherf46c0122010-03-31 00:33:27 -04002776extern void radeon_update_display_priority(struct radeon_device *rdev);
Dave Airlie72542d72009-12-01 14:06:31 +10002777extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
Jerome Glisse21f9a4372009-09-11 15:55:33 +02002778extern void radeon_scratch_init(struct radeon_device *rdev);
Alex Deucher724c80e2010-08-27 18:25:25 -04002779extern void radeon_wb_fini(struct radeon_device *rdev);
2780extern int radeon_wb_init(struct radeon_device *rdev);
2781extern void radeon_wb_disable(struct radeon_device *rdev);
Jerome Glisse21f9a4372009-09-11 15:55:33 +02002782extern void radeon_surface_init(struct radeon_device *rdev);
2783extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
Jerome Glisseca6ffc62009-10-01 10:20:52 +02002784extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
Jerome Glissed39c3b82009-09-28 18:34:43 +02002785extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
Jerome Glisse312ea8d2009-12-07 15:52:58 +01002786extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
Jerome Glissed03d8582009-12-14 21:02:09 +01002787extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
Jerome Glissed594e462010-02-17 21:54:29 +00002788extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2789extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
Dave Airlie10ebc0b2012-09-17 14:40:31 +10002790extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2791extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
Dave Airlie53595332011-03-14 09:47:24 +10002792extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
Alex Deucher2e1b65f2013-02-26 11:26:51 -05002793extern void radeon_program_register_sequence(struct radeon_device *rdev,
2794 const u32 *registers,
2795 const u32 array_size);
Jerome Glisse6cf8a3f2009-09-10 21:46:48 +02002796
Daniel Vetter3574dda2011-02-18 17:59:19 +01002797/*
Jerome Glisse721604a2012-01-05 22:11:05 -05002798 * vm
2799 */
2800int radeon_vm_manager_init(struct radeon_device *rdev);
2801void radeon_vm_manager_fini(struct radeon_device *rdev);
Christian König6d2f2942014-02-20 13:42:17 +01002802int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
Jerome Glisse721604a2012-01-05 22:11:05 -05002803void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
Christian Königdf0af442014-03-03 12:38:08 +01002804struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev,
2805 struct radeon_vm *vm,
2806 struct list_head *head);
Christian Königee60e292012-08-09 16:21:08 +02002807struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2808 struct radeon_vm *vm, int ring);
Christian Königfa688342014-02-20 10:47:05 +01002809void radeon_vm_flush(struct radeon_device *rdev,
2810 struct radeon_vm *vm,
2811 int ring);
Christian Königee60e292012-08-09 16:21:08 +02002812void radeon_vm_fence(struct radeon_device *rdev,
2813 struct radeon_vm *vm,
2814 struct radeon_fence *fence);
Christian Königdce34bf2012-09-17 19:36:18 +02002815uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
Christian König6d2f2942014-02-20 13:42:17 +01002816int radeon_vm_update_page_directory(struct radeon_device *rdev,
2817 struct radeon_vm *vm);
Christian König9c57a6b2013-11-25 15:42:11 +01002818int radeon_vm_bo_update(struct radeon_device *rdev,
2819 struct radeon_vm *vm,
2820 struct radeon_bo *bo,
2821 struct ttm_mem_reg *mem);
Jerome Glisse721604a2012-01-05 22:11:05 -05002822void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2823 struct radeon_bo *bo);
Christian König421ca7a2012-09-11 16:10:00 +02002824struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2825 struct radeon_bo *bo);
Christian Könige971bd52012-09-11 16:10:04 +02002826struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2827 struct radeon_vm *vm,
2828 struct radeon_bo *bo);
2829int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2830 struct radeon_bo_va *bo_va,
2831 uint64_t offset,
2832 uint32_t flags);
Jerome Glisse721604a2012-01-05 22:11:05 -05002833int radeon_vm_bo_rmv(struct radeon_device *rdev,
Christian Könige971bd52012-09-11 16:10:04 +02002834 struct radeon_bo_va *bo_va);
Jerome Glisse721604a2012-01-05 22:11:05 -05002835
Alex Deucherf122c612012-03-30 08:59:57 -04002836/* audio */
2837void r600_audio_update_hdmi(struct work_struct *work);
Alex Deucherb5306022013-07-31 16:51:33 -04002838struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2839struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
Alex Deucher832eafa2014-02-18 11:07:55 -05002840void r600_audio_enable(struct radeon_device *rdev,
2841 struct r600_audio_pin *pin,
2842 bool enable);
2843void dce6_audio_enable(struct radeon_device *rdev,
2844 struct r600_audio_pin *pin,
2845 bool enable);
Jerome Glisse721604a2012-01-05 22:11:05 -05002846
2847/*
Alex Deucher16cdf042011-10-28 10:30:02 -04002848 * R600 vram scratch functions
2849 */
2850int r600_vram_scratch_init(struct radeon_device *rdev);
2851void r600_vram_scratch_fini(struct radeon_device *rdev);
2852
2853/*
Jerome Glisse285484e2011-12-16 17:03:42 -05002854 * r600 cs checking helper
2855 */
2856unsigned r600_mip_minify(unsigned size, unsigned level);
2857bool r600_fmt_is_valid_color(u32 format);
2858bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2859int r600_fmt_get_blocksize(u32 format);
2860int r600_fmt_get_nblocksx(u32 format, u32 w);
2861int r600_fmt_get_nblocksy(u32 format, u32 h);
2862
2863/*
Daniel Vetter3574dda2011-02-18 17:59:19 +01002864 * r600 functions used by radeon_encoder.c
2865 */
Rafał Miłecki1b688d02012-04-30 15:44:54 +02002866struct radeon_hdmi_acr {
2867 u32 clock;
2868
2869 int n_32khz;
2870 int cts_32khz;
2871
2872 int n_44_1khz;
2873 int cts_44_1khz;
2874
2875 int n_48khz;
2876 int cts_48khz;
2877
2878};
2879
Rafał Miłeckie55d3e62012-05-06 17:29:44 +02002880extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2881
Alex Deucher416a2bd2012-05-31 19:00:25 -04002882extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2883 u32 tiling_pipe_num,
2884 u32 max_rb_num,
2885 u32 total_max_rb_num,
2886 u32 enabled_rb_mask);
Alex Deucherfe251e22010-03-24 13:36:43 -04002887
Rafał Miłeckie55d3e62012-05-06 17:29:44 +02002888/*
2889 * evergreen functions used by radeon_encoder.c
2890 */
2891
Alex Deucher0af62b02011-01-06 21:19:31 -05002892extern int ni_init_microcode(struct radeon_device *rdev);
Alex Deucher755d8192011-03-02 20:07:34 -05002893extern int ni_mc_load_microcode(struct radeon_device *rdev);
Alex Deucher0af62b02011-01-06 21:19:31 -05002894
Alex Deucherc4917072012-07-31 17:14:35 -04002895/* radeon_acpi.c */
2896#if defined(CONFIG_ACPI)
2897extern int radeon_acpi_init(struct radeon_device *rdev);
2898extern void radeon_acpi_fini(struct radeon_device *rdev);
Alex Deucherdc50ba72013-06-26 00:33:35 -04002899extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2900extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
Alex Deuchere37e6a02013-02-13 15:47:24 -05002901 u8 perf_req, bool advertise);
Alex Deucherdc50ba72013-06-26 00:33:35 -04002902extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
Alex Deucherc4917072012-07-31 17:14:35 -04002903#else
2904static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2905static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2906#endif
Alberto Miloned7a29522010-07-06 11:40:24 -04002907
Ilija Hadzicc38f34b2013-01-02 18:27:41 -05002908int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2909 struct radeon_cs_packet *pkt,
2910 unsigned idx);
Ilija Hadzic9ffb7a62013-01-02 18:27:42 -05002911bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
Ilija Hadzicc3ad63a2013-01-02 18:27:45 -05002912void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2913 struct radeon_cs_packet *pkt);
Ilija Hadzice9716992013-01-02 18:27:46 -05002914int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2915 struct radeon_cs_reloc **cs_reloc,
2916 int nomm);
Ilija Hadzic40592a12013-01-02 18:27:43 -05002917int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2918 uint32_t *vline_start_end,
2919 uint32_t *vline_status);
Ilija Hadzicc38f34b2013-01-02 18:27:41 -05002920
Jerome Glisse4c788672009-11-20 14:29:23 +01002921#include "radeon_object.h"
2922
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002923#endif