| Tony Lindgren | 54db6ee | 2012-10-24 14:26:18 -0700 | [diff] [blame^] | 1 | #include <plat/usb.h> |
| 2 | |
| 3 | /* AM35x */ |
| 4 | /* USB 2.0 PHY Control */ |
| 5 | #define CONF2_PHY_GPIOMODE (1 << 23) |
| 6 | #define CONF2_OTGMODE (3 << 14) |
| 7 | #define CONF2_NO_OVERRIDE (0 << 14) |
| 8 | #define CONF2_FORCE_HOST (1 << 14) |
| 9 | #define CONF2_FORCE_DEVICE (2 << 14) |
| 10 | #define CONF2_FORCE_HOST_VBUS_LOW (3 << 14) |
| 11 | #define CONF2_SESENDEN (1 << 13) |
| 12 | #define CONF2_VBDTCTEN (1 << 12) |
| 13 | #define CONF2_REFFREQ_24MHZ (2 << 8) |
| 14 | #define CONF2_REFFREQ_26MHZ (7 << 8) |
| 15 | #define CONF2_REFFREQ_13MHZ (6 << 8) |
| 16 | #define CONF2_REFFREQ (0xf << 8) |
| 17 | #define CONF2_PHYCLKGD (1 << 7) |
| 18 | #define CONF2_VBUSSENSE (1 << 6) |
| 19 | #define CONF2_PHY_PLLON (1 << 5) |
| 20 | #define CONF2_RESET (1 << 4) |
| 21 | #define CONF2_PHYPWRDN (1 << 3) |
| 22 | #define CONF2_OTGPWRDN (1 << 2) |
| 23 | #define CONF2_DATPOL (1 << 1) |
| 24 | |
| 25 | /* TI81XX specific definitions */ |
| 26 | #define USBCTRL0 0x620 |
| 27 | #define USBSTAT0 0x624 |
| 28 | |
| 29 | /* TI816X PHY controls bits */ |
| 30 | #define TI816X_USBPHY0_NORMAL_MODE (1 << 0) |
| 31 | #define TI816X_USBPHY_REFCLK_OSC (1 << 8) |
| 32 | |
| 33 | /* TI814X PHY controls bits */ |
| 34 | #define USBPHY_CM_PWRDN (1 << 0) |
| 35 | #define USBPHY_OTG_PWRDN (1 << 1) |
| 36 | #define USBPHY_CHGDET_DIS (1 << 2) |
| 37 | #define USBPHY_CHGDET_RSTRT (1 << 3) |
| 38 | #define USBPHY_SRCONDM (1 << 4) |
| 39 | #define USBPHY_SINKONDP (1 << 5) |
| 40 | #define USBPHY_CHGISINK_EN (1 << 6) |
| 41 | #define USBPHY_CHGVSRC_EN (1 << 7) |
| 42 | #define USBPHY_DMPULLUP (1 << 8) |
| 43 | #define USBPHY_DPPULLUP (1 << 9) |
| 44 | #define USBPHY_CDET_EXTCTL (1 << 10) |
| 45 | #define USBPHY_GPIO_MODE (1 << 12) |
| 46 | #define USBPHY_DPOPBUFCTL (1 << 13) |
| 47 | #define USBPHY_DMOPBUFCTL (1 << 14) |
| 48 | #define USBPHY_DPINPUT (1 << 15) |
| 49 | #define USBPHY_DMINPUT (1 << 16) |
| 50 | #define USBPHY_DPGPIO_PD (1 << 17) |
| 51 | #define USBPHY_DMGPIO_PD (1 << 18) |
| 52 | #define USBPHY_OTGVDET_EN (1 << 19) |
| 53 | #define USBPHY_OTGSESSEND_EN (1 << 20) |
| 54 | #define USBPHY_DATA_POLARITY (1 << 23) |
| 55 | |
| 56 | struct usbhs_omap_board_data { |
| 57 | enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS]; |
| 58 | |
| 59 | /* have to be valid if phy_reset is true and portx is in phy mode */ |
| 60 | int reset_gpio_port[OMAP3_HS_USB_PORTS]; |
| 61 | |
| 62 | /* Set this to true for ES2.x silicon */ |
| 63 | unsigned es2_compatibility:1; |
| 64 | |
| 65 | unsigned phy_reset:1; |
| 66 | |
| 67 | /* |
| 68 | * Regulators for USB PHYs. |
| 69 | * Each PHY can have a separate regulator. |
| 70 | */ |
| 71 | struct regulator *regulator[OMAP3_HS_USB_PORTS]; |
| 72 | }; |
| 73 | |
| 74 | extern void usb_musb_init(struct omap_musb_board_data *board_data); |
| 75 | extern void usbhs_init(const struct usbhs_omap_board_data *pdata); |
| 76 | |
| 77 | extern void am35x_musb_reset(void); |
| 78 | extern void am35x_musb_phy_power(u8 on); |
| 79 | extern void am35x_musb_clear_irq(void); |
| 80 | extern void am35x_set_mode(u8 musb_mode); |
| 81 | extern void ti81xx_musb_phy_power(u8 on); |
| 82 | |