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gerrit-public.fairphone.software / kernel / msm-4.19 / 55271024a735d0c3234e6ca7e0914b05aab7fbac / . / arch / powerpc / boot / dts / kmeter1.dts
blob: d8b5d12fb66306c79271fc1b02ecf76fa009aa4a [file] [log] [blame]
Heiko Schocher8159df72009-06-15 09:38:18 +0200[diff] [blame]1/*
2 * Keymile KMETER1 Device Tree Source
3 *
4 * 2008 DENX Software Engineering GmbH
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13
14/ {
15 model = "KMETER1";
16 compatible = "keymile,KMETER1";
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 aliases {
21 ethernet0 = &enet_piggy2;
22 ethernet1 = &enet_estar1;
23 ethernet2 = &enet_estar2;
24 ethernet3 = &enet_eth1;
25 ethernet4 = &enet_eth2;
26 ethernet5 = &enet_eth3;
27 ethernet6 = &enet_eth4;
28 serial0 = &serial0;
29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 PowerPC,8360@0 {
36 device_type = "cpu";
37 reg = <0x0>;
38 d-cache-line-size = <32>; // 32 bytes
39 i-cache-line-size = <32>; // 32 bytes
40 d-cache-size = <32768>; // L1, 32K
41 i-cache-size = <32768>; // L1, 32K
42 timebase-frequency = <0>; /* Filled in by U-Boot */
43 bus-frequency = <0>; /* Filled in by U-Boot */
44 clock-frequency = <0>; /* Filled in by U-Boot */
45 };
46 };
47
48 memory {
49 device_type = "memory";
50 reg = <0 0>; /* Filled in by U-Boot */
51 };
52
53 soc8360@e0000000 {
54 #address-cells = <1>;
55 #size-cells = <1>;
56 device_type = "soc";
57 compatible = "fsl,mpc8360-immr", "simple-bus";
58 ranges = <0x0 0xe0000000 0x00200000>;
59 reg = <0xe0000000 0x00000200>;
60 bus-frequency = <0>; /* Filled in by U-Boot */
61
Anton Vorontsov1f8a25d2009-09-16 01:44:02 +0400[diff] [blame]62 pmc: power@b00 {
63 compatible = "fsl,mpc8360-pmc", "fsl,mpc8349-pmc";
64 reg = <0xb00 0x100 0xa00 0x100>;
65 interrupts = <80 0x8>;
66 interrupt-parent = <&ipic>;
67 };
68
Heiko Schocher8159df72009-06-15 09:38:18 +0200[diff] [blame]69 i2c@3000 {
70 #address-cells = <1>;
71 #size-cells = <0>;
72 cell-index = <0>;
73 compatible = "fsl-i2c";
74 reg = <0x3000 0x100>;
75 interrupts = <14 0x8>;
76 interrupt-parent = <&ipic>;
77 dfsrr;
78 };
79
80 serial0: serial@4500 {
81 cell-index = <0>;
82 device_type = "serial";
83 compatible = "ns16550";
84 reg = <0x4500 0x100>;
85 clock-frequency = <264000000>;
86 interrupts = <9 0x8>;
87 interrupt-parent = <&ipic>;
88 };
89
90 dma@82a8 {
91 #address-cells = <1>;
92 #size-cells = <1>;
93 compatible = "fsl,mpc8360-dma", "fsl,elo-dma";
94 reg = <0x82a8 4>;
95 ranges = <0 0x8100 0x1a8>;
96 interrupt-parent = <&ipic>;
97 interrupts = <71 8>;
98 cell-index = <0>;
99 dma-channel@0 {
100 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
101 reg = <0 0x80>;
102 interrupt-parent = <&ipic>;
103 interrupts = <71 8>;
104 };
105 dma-channel@80 {
106 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
107 reg = <0x80 0x80>;
108 interrupt-parent = <&ipic>;
109 interrupts = <71 8>;
110 };
111 dma-channel@100 {
112 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
113 reg = <0x100 0x80>;
114 interrupt-parent = <&ipic>;
115 interrupts = <71 8>;
116 };
117 dma-channel@180 {
118 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
119 reg = <0x180 0x28>;
120 interrupt-parent = <&ipic>;
121 interrupts = <71 8>;
122 };
123 };
124
125 ipic: pic@700 {
126 #address-cells = <0>;
127 #interrupt-cells = <2>;
128 compatible = "fsl,pq2pro-pic", "fsl,ipic";
129 interrupt-controller;
130 reg = <0x700 0x100>;
131 };
132
133 par_io@1400 {
134 #address-cells = <1>;
135 #size-cells = <0>;
136 reg = <0x1400 0x100>;
137 compatible = "fsl,mpc8360-par_io";
138 num-ports = <7>;
139
140 pio_ucc1: ucc_pin@0 {
141 reg = <0>;
142
143 pio-map = <
144 /* port pin dir open_drain assignment has_irq */
145 0 1 3 0 2 0 /* MDIO */
146 0 2 1 0 1 0 /* MDC */
147
148 0 3 1 0 1 0 /* TxD0 */
149 0 4 1 0 1 0 /* TxD1 */
150 0 5 1 0 1 0 /* TxD2 */
151 0 6 1 0 1 0 /* TxD3 */
152 0 9 2 0 1 0 /* RxD0 */
153 0 10 2 0 1 0 /* RxD1 */
154 0 11 2 0 1 0 /* RxD2 */
155 0 12 2 0 1 0 /* RxD3 */
156 0 7 1 0 1 0 /* TX_EN */
157 0 8 1 0 1 0 /* TX_ER */
158 0 15 2 0 1 0 /* RX_DV */
159 0 16 2 0 1 0 /* RX_ER */
160 0 0 2 0 1 0 /* RX_CLK */
161 2 9 1 0 3 0 /* GTX_CLK - CLK10 */
162 2 8 2 0 1 0 /* GTX125 - CLK9 */
163 >;
164 };
165
166 pio_ucc2: ucc_pin@1 {
167 reg = <1>;
168
169 pio-map = <
170 /* port pin dir open_drain assignment has_irq */
171 0 1 3 0 2 0 /* MDIO */
172 0 2 1 0 1 0 /* MDC */
173
174 0 17 1 0 1 0 /* TxD0 */
175 0 18 1 0 1 0 /* TxD1 */
176 0 19 1 0 1 0 /* TxD2 */
177 0 20 1 0 1 0 /* TxD3 */
178 0 23 2 0 1 0 /* RxD0 */
179 0 24 2 0 1 0 /* RxD1 */
180 0 25 2 0 1 0 /* RxD2 */
181 0 26 2 0 1 0 /* RxD3 */
182 0 21 1 0 1 0 /* TX_EN */
183 0 22 1 0 1 0 /* TX_ER */
184 0 29 2 0 1 0 /* RX_DV */
185 0 30 2 0 1 0 /* RX_ER */
186 0 31 2 0 1 0 /* RX_CLK */
187 2 2 1 0 2 0 /* GTX_CLK - CLK3 */
188 2 3 2 0 1 0 /* GTX125 - CLK4 */
189 >;
190 };
191
192 pio_ucc4: ucc_pin@3 {
193 reg = <3>;
194
195 pio-map = <
196 /* port pin dir open_drain assignment has_irq */
197 0 1 3 0 2 0 /* MDIO */
198 0 2 1 0 1 0 /* MDC */
199
200 1 14 1 0 1 0 /* TxD0 (PB14, out, f1) */
201 1 15 1 0 1 0 /* TxD1 (PB15, out, f1) */
202 1 20 2 0 1 0 /* RxD0 (PB20, in, f1) */
203 1 21 2 0 1 0 /* RxD1 (PB21, in, f1) */
204 1 18 1 0 1 0 /* TX_EN (PB18, out, f1) */
205 1 26 2 0 1 0 /* RX_DV (PB26, in, f1) */
206 1 27 2 0 1 0 /* RX_ER (PB27, in, f1) */
207
208 2 16 2 0 1 0 /* UCC4_RMII_CLK (CLK17) */
209 >;
210 };
211
212 pio_ucc5: ucc_pin@4 {
213 reg = <4>;
214
215 pio-map = <
216 /* port pin dir open_drain assignment has_irq */
217 0 1 3 0 2 0 /* MDIO */
218 0 2 1 0 1 0 /* MDC */
219
220 3 0 1 0 1 0 /* TxD0 (PD0, out, f1) */
221 3 1 1 0 1 0 /* TxD1 (PD1, out, f1) */
222 3 6 2 0 1 0 /* RxD0 (PD6, in, f1) */
223 3 7 2 0 1 0 /* RxD1 (PD7, in, f1) */
224 3 4 1 0 1 0 /* TX_EN (PD4, out, f1) */
225 3 12 2 0 1 0 /* RX_DV (PD12, in, f1) */
226 3 13 2 0 1 0 /* RX_ER (PD13, in, f1) */
227 >;
228 };
229
230 pio_ucc6: ucc_pin@5 {
231 reg = <5>;
232
233 pio-map = <
234 /* port pin dir open_drain assignment has_irq */
235 0 1 3 0 2 0 /* MDIO */
236 0 2 1 0 1 0 /* MDC */
237
238 3 14 1 0 1 0 /* TxD0 (PD14, out, f1) */
239 3 15 1 0 1 0 /* TxD1 (PD15, out, f1) */
240 3 20 2 0 1 0 /* RxD0 (PD20, in, f1) */
241 3 21 2 0 1 0 /* RxD1 (PD21, in, f1) */
242 3 18 1 0 1 0 /* TX_EN (PD18, out, f1) */
243 3 26 2 0 1 0 /* RX_DV (PD26, in, f1) */
244 3 27 2 0 1 0 /* RX_ER (PD27, in, f1) */
245 >;
246 };
247
248 pio_ucc7: ucc_pin@6 {
249 reg = <6>;
250
251 pio-map = <
252 /* port pin dir open_drain assignment has_irq */
253 0 1 3 0 2 0 /* MDIO */
254 0 2 1 0 1 0 /* MDC */
255
256 4 0 1 0 1 0 /* TxD0 (PE0, out, f1) */
257 4 1 1 0 1 0 /* TxD1 (PE1, out, f1) */
258 4 6 2 0 1 0 /* RxD0 (PE6, in, f1) */
259 4 7 2 0 1 0 /* RxD1 (PE7, in, f1) */
260 4 4 1 0 1 0 /* TX_EN (PE4, out, f1) */
261 4 12 2 0 1 0 /* RX_DV (PE12, in, f1) */
262 4 13 2 0 1 0 /* RX_ER (PE13, in, f1) */
263 >;
264 };
265
266 pio_ucc8: ucc_pin@7 {
267 reg = <7>;
268
269 pio-map = <
270 /* port pin dir open_drain assignment has_irq */
271 0 1 3 0 2 0 /* MDIO */
272 0 2 1 0 1 0 /* MDC */
273
274 4 14 1 0 2 0 /* TxD0 (PE14, out, f2) */
275 4 15 1 0 1 0 /* TxD1 (PE15, out, f1) */
276 4 20 2 0 1 0 /* RxD0 (PE20, in, f1) */
277 4 21 2 0 1 0 /* RxD1 (PE21, in, f1) */
278 4 18 1 0 1 0 /* TX_EN (PE18, out, f1) */
279 4 26 2 0 1 0 /* RX_DV (PE26, in, f1) */
280 4 27 2 0 1 0 /* RX_ER (PE27, in, f1) */
281
282 2 15 2 0 1 0 /* UCCx_RMII_CLK (CLK16) */
283 >;
284 };
285
286 };
287
288 qe@100000 {
289 #address-cells = <1>;
290 #size-cells = <1>;
291 compatible = "fsl,qe";
292 ranges = <0x0 0x100000 0x100000>;
293 reg = <0x100000 0x480>;
294 clock-frequency = <0>; /* Filled in by U-Boot */
295 brg-frequency = <0>; /* Filled in by U-Boot */
296 bus-frequency = <0>; /* Filled in by U-Boot */
297
298 muram@10000 {
299 #address-cells = <1>;
300 #size-cells = <1>;
301 compatible = "fsl,qe-muram", "fsl,cpm-muram";
302 ranges = <0x0 0x00010000 0x0000c000>;
303
304 data-only@0 {
305 compatible = "fsl,qe-muram-data",
306 "fsl,cpm-muram-data";
307 reg = <0x0 0xc000>;
308 };
309 };
310
311 /* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */
312 enet_estar1: ucc@2000 {
313 device_type = "network";
314 compatible = "ucc_geth";
315 cell-index = <1>;
316 reg = <0x2000 0x200>;
317 interrupts = <32>;
318 interrupt-parent = <&qeic>;
319 local-mac-address = [ 00 00 00 00 00 00 ];
320 rx-clock-name = "none";
321 tx-clock-name = "clk9";
322 phy-handle = <&phy_estar1>;
323 phy-connection-type = "rgmii-id";
324 pio-handle = <&pio_ucc1>;
325 };
326
327 /* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */
328 enet_estar2: ucc@3000 {
329 device_type = "network";
330 compatible = "ucc_geth";
331 cell-index = <2>;
332 reg = <0x3000 0x200>;
333 interrupts = <33>;
334 interrupt-parent = <&qeic>;
335 local-mac-address = [ 00 00 00 00 00 00 ];
336 rx-clock-name = "none";
337 tx-clock-name = "clk4";
338 phy-handle = <&phy_estar2>;
339 phy-connection-type = "rgmii-id";
340 pio-handle = <&pio_ucc2>;
341 };
342
343 /* Piggy2 (UCC4, MDIO 0x00, RMII) */
344 enet_piggy2: ucc@3200 {
345 device_type = "network";
346 compatible = "ucc_geth";
347 cell-index = <4>;
348 reg = <0x3200 0x200>;
349 interrupts = <35>;
350 interrupt-parent = <&qeic>;
351 local-mac-address = [ 00 00 00 00 00 00 ];
352 rx-clock-name = "none";
353 tx-clock-name = "clk17";
354 phy-handle = <&phy_piggy2>;
355 phy-connection-type = "rmii";
356 pio-handle = <&pio_ucc4>;
357 };
358
359 /* Eth-1 (UCC5, MDIO 0x08, RMII) */
360 enet_eth1: ucc@2400 {
361 device_type = "network";
362 compatible = "ucc_geth";
363 cell-index = <5>;
364 reg = <0x2400 0x200>;
365 interrupts = <40>;
366 interrupt-parent = <&qeic>;
367 local-mac-address = [ 00 00 00 00 00 00 ];
368 rx-clock-name = "none";
369 tx-clock-name = "clk16";
370 phy-handle = <&phy_eth1>;
371 phy-connection-type = "rmii";
372 pio-handle = <&pio_ucc5>;
373 };
374
375 /* Eth-2 (UCC6, MDIO 0x09, RMII) */
376 enet_eth2: ucc@3400 {
377 device_type = "network";
378 compatible = "ucc_geth";
379 cell-index = <6>;
380 reg = <0x3400 0x200>;
381 interrupts = <41>;
382 interrupt-parent = <&qeic>;
383 local-mac-address = [ 00 00 00 00 00 00 ];
384 rx-clock-name = "none";
385 tx-clock-name = "clk16";
386 phy-handle = <&phy_eth2>;
387 phy-connection-type = "rmii";
388 pio-handle = <&pio_ucc6>;
389 };
390
391 /* Eth-3 (UCC7, MDIO 0x0a, RMII) */
392 enet_eth3: ucc@2600 {
393 device_type = "network";
394 compatible = "ucc_geth";
395 cell-index = <7>;
396 reg = <0x2600 0x200>;
397 interrupts = <42>;
398 interrupt-parent = <&qeic>;
399 local-mac-address = [ 00 00 00 00 00 00 ];
400 rx-clock-name = "none";
401 tx-clock-name = "clk16";
402 phy-handle = <&phy_eth3>;
403 phy-connection-type = "rmii";
404 pio-handle = <&pio_ucc7>;
405 };
406
407 /* Eth-4 (UCC8, MDIO 0x0b, RMII) */
408 enet_eth4: ucc@3600 {
409 device_type = "network";
410 compatible = "ucc_geth";
411 cell-index = <8>;
412 reg = <0x3600 0x200>;
413 interrupts = <43>;
414 interrupt-parent = <&qeic>;
415 local-mac-address = [ 00 00 00 00 00 00 ];
416 rx-clock-name = "none";
417 tx-clock-name = "clk16";
418 phy-handle = <&phy_eth4>;
419 phy-connection-type = "rmii";
420 pio-handle = <&pio_ucc8>;
421 };
422
423 mdio@3320 {
424 #address-cells = <1>;
425 #size-cells = <0>;
426 reg = <0x3320 0x18>;
427 compatible = "fsl,ucc-mdio";
428
429 /* Piggy2 (UCC4, MDIO 0x00, RMII) */
430 phy_piggy2: ethernet-phy@00 {
431 reg = <0x0>;
432 };
433
434 /* Eth-1 (UCC5, MDIO 0x08, RMII) */
435 phy_eth1: ethernet-phy@08 {
436 reg = <0x08>;
437 };
438
439 /* Eth-2 (UCC6, MDIO 0x09, RMII) */
440 phy_eth2: ethernet-phy@09 {
441 reg = <0x09>;
442 };
443
444 /* Eth-3 (UCC7, MDIO 0x0a, RMII) */
445 phy_eth3: ethernet-phy@0a {
446 reg = <0x0a>;
447 };
448
449 /* Eth-4 (UCC8, MDIO 0x0b, RMII) */
450 phy_eth4: ethernet-phy@0b {
451 reg = <0x0b>;
452 };
453
454 /* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */
455 phy_estar1: ethernet-phy@10 {
456 interrupt-parent = <&ipic>;
457 interrupts = <17 0x8>;
458 reg = <0x10>;
459 };
460
461 /* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */
462 phy_estar2: ethernet-phy@11 {
463 interrupt-parent = <&ipic>;
464 interrupts = <18 0x8>;
465 reg = <0x11>;
466 };
467 };
468
469 qeic: interrupt-controller@80 {
470 interrupt-controller;
471 compatible = "fsl,qe-ic";
472 #address-cells = <0>;
473 #interrupt-cells = <1>;
474 reg = <0x80 0x80>;
475 interrupts = <32 8 33 8>;
476 interrupt-parent = <&ipic>;
477 };
478 };
479 };
480
481 localbus@e0005000 {
482 #address-cells = <2>;
483 #size-cells = <1>;
484 compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus",
485 "simple-bus";
486 reg = <0xe0005000 0xd8>;
487 ranges = <0 0 0xf0000000 0x04000000>; /* Filled in by U-Boot */
488
489 flash@f0000000,0 {
490 compatible = "cfi-flash";
491 /*
492 * The Intel P30 chip has 2 non-identical chips on
Daniel Mack3ad2f3f2010-02-03 08:01:28 +0800[diff] [blame]493 * one die, so we need to define 2 separate regions
Heiko Schocher8159df72009-06-15 09:38:18 +0200[diff] [blame]494 * that are scanned by physmap_of independantly.
495 */
496 reg = <0 0x00000000 0x02000000
497 0 0x02000000 0x02000000>; /* Filled in by U-Boot */
498 bank-width = <2>;
499 #address-cells = <1>;
500 #size-cells = <1>;
501 partition@0 {
502 label = "u-boot";
503 reg = <0 0x40000>;
504 };
505 partition@40000 {
506 label = "env";
507 reg = <0x40000 0x40000>;
508 };
509 partition@80000 {
510 label = "dtb";
511 reg = <0x80000 0x20000>;
512 };
513 partition@a0000 {
514 label = "kernel";
515 reg = <0xa0000 0x300000>;
516 };
517 partition@3a0000 {
518 label = "ramdisk";
519 reg = <0x3a0000 0x800000>;
520 };
521 partition@ba0000 {
522 label = "user";
523 reg = <0xba0000 0x3460000>;
524 };
525 };
526 };
527};