blob: befec7d12132a131e58bb54773f80914e9bca761 [file] [log] [blame]
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_OBJECT_H__
29#define __RADEON_OBJECT_H__
30
Jerome Glisse4c788672009-11-20 14:29:23 +010031#include <drm/radeon_drm.h>
32#include "radeon.h"
Jerome Glisse771fe6b2009-06-05 14:42:42 +020033
Jerome Glisse4c788672009-11-20 14:29:23 +010034/**
35 * radeon_mem_type_to_domain - return domain corresponding to mem_type
36 * @mem_type: ttm memory type
37 *
38 * Returns corresponding domain of the ttm mem_type
Jerome Glisse771fe6b2009-06-05 14:42:42 +020039 */
Jerome Glisse4c788672009-11-20 14:29:23 +010040static inline unsigned radeon_mem_type_to_domain(u32 mem_type)
41{
42 switch (mem_type) {
43 case TTM_PL_VRAM:
44 return RADEON_GEM_DOMAIN_VRAM;
45 case TTM_PL_TT:
46 return RADEON_GEM_DOMAIN_GTT;
47 case TTM_PL_SYSTEM:
48 return RADEON_GEM_DOMAIN_CPU;
49 default:
50 break;
51 }
52 return 0;
53}
54
Andi Kleence580fa2011-10-13 16:08:47 -070055int radeon_bo_reserve(struct radeon_bo *bo, bool no_wait);
Jerome Glisse4c788672009-11-20 14:29:23 +010056
57static inline void radeon_bo_unreserve(struct radeon_bo *bo)
58{
59 ttm_bo_unreserve(&bo->tbo);
60}
61
62/**
63 * radeon_bo_gpu_offset - return GPU offset of bo
64 * @bo: radeon object for which we query the offset
65 *
66 * Returns current GPU offset of the object.
67 *
68 * Note: object should either be pinned or reserved when calling this
Lucas De Marchi25985ed2011-03-30 22:57:33 -030069 * function, it might be useful to add check for this for debugging.
Jerome Glisse4c788672009-11-20 14:29:23 +010070 */
71static inline u64 radeon_bo_gpu_offset(struct radeon_bo *bo)
72{
73 return bo->tbo.offset;
74}
75
76static inline unsigned long radeon_bo_size(struct radeon_bo *bo)
77{
78 return bo->tbo.num_pages << PAGE_SHIFT;
79}
80
81static inline bool radeon_bo_is_reserved(struct radeon_bo *bo)
82{
83 return !!atomic_read(&bo->tbo.reserved);
84}
85
Jerome Glisse721604a2012-01-05 22:11:05 -050086static inline unsigned radeon_bo_ngpu_pages(struct radeon_bo *bo)
87{
88 return (bo->tbo.num_pages << PAGE_SHIFT) / RADEON_GPU_PAGE_SIZE;
89}
90
91static inline unsigned radeon_bo_gpu_page_alignment(struct radeon_bo *bo)
92{
93 return (bo->tbo.mem.page_alignment << PAGE_SHIFT) / RADEON_GPU_PAGE_SIZE;
94}
95
Jerome Glisse4c788672009-11-20 14:29:23 +010096/**
97 * radeon_bo_mmap_offset - return mmap offset of bo
98 * @bo: radeon object for which we query the offset
99 *
100 * Returns mmap offset of the object.
101 *
102 * Note: addr_space_offset is constant after ttm bo init thus isn't protected
103 * by any lock.
104 */
105static inline u64 radeon_bo_mmap_offset(struct radeon_bo *bo)
106{
107 return bo->tbo.addr_space_offset;
108}
109
Andi Kleence580fa2011-10-13 16:08:47 -0700110extern int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type,
Dave Airlie83f30d02011-10-27 18:15:10 +0200111 bool no_wait);
Jerome Glisse4c788672009-11-20 14:29:23 +0100112
113extern int radeon_bo_create(struct radeon_device *rdev,
Daniel Vetter441921d2011-02-18 17:59:16 +0100114 unsigned long size, int byte_align,
115 bool kernel, u32 domain,
116 struct radeon_bo **bo_ptr);
Jerome Glisse4c788672009-11-20 14:29:23 +0100117extern int radeon_bo_kmap(struct radeon_bo *bo, void **ptr);
118extern void radeon_bo_kunmap(struct radeon_bo *bo);
119extern void radeon_bo_unref(struct radeon_bo **bo);
120extern int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr);
Michel Dänzerc4353012012-03-14 17:12:41 +0100121extern int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain,
122 u64 max_offset, u64 *gpu_addr);
Jerome Glisse4c788672009-11-20 14:29:23 +0100123extern int radeon_bo_unpin(struct radeon_bo *bo);
124extern int radeon_bo_evict_vram(struct radeon_device *rdev);
125extern void radeon_bo_force_delete(struct radeon_device *rdev);
126extern int radeon_bo_init(struct radeon_device *rdev);
127extern void radeon_bo_fini(struct radeon_device *rdev);
128extern void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
129 struct list_head *head);
Jerome Glisse94429bb2010-02-15 21:36:33 +0100130extern int radeon_bo_list_validate(struct list_head *head);
Jerome Glisse4c788672009-11-20 14:29:23 +0100131extern int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
132 struct vm_area_struct *vma);
133extern int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
134 u32 tiling_flags, u32 pitch);
135extern void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
136 u32 *tiling_flags, u32 *pitch);
137extern int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
138 bool force_drop);
139extern void radeon_bo_move_notify(struct ttm_buffer_object *bo,
140 struct ttm_mem_reg *mem);
Jerome Glisse0a2d50e2010-04-09 14:39:24 +0200141extern int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
Dave Airlie550e2d92009-12-09 14:15:38 +1000142extern int radeon_bo_get_surface_reg(struct radeon_bo *bo);
Jerome Glisse721604a2012-01-05 22:11:05 -0500143extern struct radeon_bo_va *radeon_bo_va(struct radeon_bo *rbo,
144 struct radeon_vm *vm);
Jerome Glisseb15ba512011-11-15 11:48:34 -0500145
146/*
147 * sub allocation
148 */
Christian Königdd8bea22012-05-09 15:34:49 +0200149
150static inline uint64_t radeon_sa_bo_gpu_addr(struct radeon_sa_bo *sa_bo)
151{
Christian Könige6661a92012-05-09 15:34:52 +0200152 return sa_bo->manager->gpu_addr + sa_bo->soffset;
Christian Königdd8bea22012-05-09 15:34:49 +0200153}
154
155static inline void * radeon_sa_bo_cpu_addr(struct radeon_sa_bo *sa_bo)
156{
Christian Könige6661a92012-05-09 15:34:52 +0200157 return sa_bo->manager->cpu_ptr + sa_bo->soffset;
Christian Königdd8bea22012-05-09 15:34:49 +0200158}
159
Jerome Glisseb15ba512011-11-15 11:48:34 -0500160extern int radeon_sa_bo_manager_init(struct radeon_device *rdev,
161 struct radeon_sa_manager *sa_manager,
162 unsigned size, u32 domain);
163extern void radeon_sa_bo_manager_fini(struct radeon_device *rdev,
164 struct radeon_sa_manager *sa_manager);
165extern int radeon_sa_bo_manager_start(struct radeon_device *rdev,
166 struct radeon_sa_manager *sa_manager);
167extern int radeon_sa_bo_manager_suspend(struct radeon_device *rdev,
168 struct radeon_sa_manager *sa_manager);
169extern int radeon_sa_bo_new(struct radeon_device *rdev,
170 struct radeon_sa_manager *sa_manager,
Christian König2e0d9912012-05-09 15:34:53 +0200171 struct radeon_sa_bo **sa_bo,
Christian König557017a2012-05-09 15:34:54 +0200172 unsigned size, unsigned align, bool block);
Jerome Glisseb15ba512011-11-15 11:48:34 -0500173extern void radeon_sa_bo_free(struct radeon_device *rdev,
Christian König557017a2012-05-09 15:34:54 +0200174 struct radeon_sa_bo **sa_bo,
175 struct radeon_fence *fence);
Christian König711a9722012-05-09 15:34:51 +0200176#if defined(CONFIG_DEBUG_FS)
177extern void radeon_sa_bo_dump_debug_info(struct radeon_sa_manager *sa_manager,
178 struct seq_file *m);
179#endif
180
Jerome Glisseb15ba512011-11-15 11:48:34 -0500181
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200182#endif