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gerrit-public.fairphone.software / kernel / msm-4.19 / 5612ac83b9d7a32a7f2967d9f6f97e7f3428dfd2 / . / arch / arm / boot / dts / imx1-ads.dts
blob: 5ea28ee07cf457a65cfed24a7563296483355b5d [file] [log] [blame]
Alexander Shiyance253b52014-08-19 10:33:47 +0400[diff] [blame]1/*
2 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13#include "imx1.dtsi"
14
15/ {
16 model = "Freescale MX1 ADS";
17 compatible = "fsl,imx1ads", "fsl,imx1";
18
19 chosen {
20 stdout-path = &uart1;
21 };
22
23 memory {
24 reg = <0x08000000 0x04000000>;
25 };
26
27 clocks {
28 #address-cells = <1>;
29 #size-cells = <0>;
30
31 clk32 {
32 compatible = "fsl,imx-clk32", "fixed-clock";
33 #clock-cells = <0>;
34 clock-frequency = <32000>;
35 };
36 };
37};
38
39&cspi1 {
40 pinctrl-0 = <&pinctrl_cspi1>;
Alexander Shiyance253b52014-08-19 10:33:47 +0400[diff] [blame]41 cs-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>;
42 status = "okay";
43};
44
45&i2c {
46 pinctrl-names = "default";
47 pinctrl-0 = <&pinctrl_i2c>;
48 status = "okay";
49
50 extgpio0: pcf8575@22 {
51 compatible = "nxp,pcf8575";
52 reg = <0x22>;
53 gpio-controller;
54 #gpio-cells = <2>;
55 };
56
57 extgpio1: pcf8575@24 {
58 compatible = "nxp,pcf8575";
59 reg = <0x24>;
60 gpio-controller;
61 #gpio-cells = <2>;
62 };
63};
64
65&uart1 {
66 pinctrl-names = "default";
67 pinctrl-0 = <&pinctrl_uart1>;
Geert Uytterhoeven2e7c4162016-05-31 16:31:51 +0200[diff] [blame]68 uart-has-rtscts;
Alexander Shiyance253b52014-08-19 10:33:47 +0400[diff] [blame]69 status = "okay";
70};
71
72&uart2 {
73 pinctrl-names = "default";
74 pinctrl-0 = <&pinctrl_uart2>;
Geert Uytterhoeven2e7c4162016-05-31 16:31:51 +0200[diff] [blame]75 uart-has-rtscts;
Alexander Shiyance253b52014-08-19 10:33:47 +0400[diff] [blame]76 status = "okay";
77};
78
79&weim {
80 pinctrl-names = "default";
81 pinctrl-0 = <&pinctrl_weim>;
82 status = "okay";
83
84 nor: nor@0,0 {
85 compatible = "cfi-flash";
86 reg = <0 0x00000000 0x02000000>;
87 bank-width = <4>;
88 fsl,weim-cs-timing = <0x00003e00 0x00000801>;
89 #address-cells = <1>;
90 #size-cells = <1>;
91 };
92};
93
94&iomuxc {
95 imx1-ads {
96 pinctrl_cspi1: cspi1grp {
97 fsl,pins = <
98 MX1_PAD_SPI1_MISO__SPI1_MISO 0x0
99 MX1_PAD_SPI1_MOSI__SPI1_MOSI 0x0
100 MX1_PAD_SPI1_RDY__SPI1_RDY 0x0
101 MX1_PAD_SPI1_SCLK__SPI1_SCLK 0x0
102 MX1_PAD_SPI1_SS__GPIO3_15 0x0
103 >;
104 };
105
106 pinctrl_i2c: i2cgrp {
107 fsl,pins = <
108 MX1_PAD_I2C_SCL__I2C_SCL 0x0
109 MX1_PAD_I2C_SDA__I2C_SDA 0x0
110 >;
111 };
112
113 pinctrl_uart1: uart1grp {
114 fsl,pins = <
115 MX1_PAD_UART1_TXD__UART1_TXD 0x0
116 MX1_PAD_UART1_RXD__UART1_RXD 0x0
117 MX1_PAD_UART1_CTS__UART1_CTS 0x0
118 MX1_PAD_UART1_RTS__UART1_RTS 0x0
119 >;
120 };
121
122 pinctrl_uart2: uart2grp {
123 fsl,pins = <
124 MX1_PAD_UART2_TXD__UART2_TXD 0x0
125 MX1_PAD_UART2_RXD__UART2_RXD 0x0
126 MX1_PAD_UART2_CTS__UART2_CTS 0x0
127 MX1_PAD_UART2_RTS__UART2_RTS 0x0
128 >;
129 };
130
131 pinctrl_weim: weimgrp {
132 fsl,pins = <
133 MX1_PAD_A0__A0 0x0
134 MX1_PAD_A16__A16 0x0
135 MX1_PAD_A17__A17 0x0
136 MX1_PAD_A18__A18 0x0
137 MX1_PAD_A19__A19 0x0
138 MX1_PAD_A20__A20 0x0
139 MX1_PAD_A21__A21 0x0
140 MX1_PAD_A22__A22 0x0
141 MX1_PAD_A23__A23 0x0
142 MX1_PAD_A24__A24 0x0
143 MX1_PAD_BCLK__BCLK 0x0
144 MX1_PAD_CS4__CS4 0x0
145 MX1_PAD_DTACK__DTACK 0x0
146 MX1_PAD_ECB__ECB 0x0
147 MX1_PAD_LBA__LBA 0x0
148 >;
149 };
150 };
151};