arch/powerpc/boot/dts/fsl/mpc8569si-post.dtsi

/*
 * MPC8569 Silicon/SoC Device Tree Source (post include)
 *
 * Copyright 2011 Freescale Semiconductor Inc.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *     * Redistributions of source code must retain the above copyright
 *       notice, this list of conditions and the following disclaimer.
 *     * Redistributions in binary form must reproduce the above copyright
 *       notice, this list of conditions and the following disclaimer in the
 *       documentation and/or other materials provided with the distribution.
 *     * Neither the name of Freescale Semiconductor nor the
 *       names of its contributors may be used to endorse or promote products
 *       derived from this software without specific prior written permission.
 *
 *
 * ALTERNATIVELY, this software may be distributed under the terms of the
 * GNU General Public License ("GPL") as published by the Free Software
 * Foundation, either version 2 of that License or (at your option) any
 * later version.
 *
 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

&lbc {
	#address-cells = <2>;
	#size-cells = <1>;
	compatible = "fsl,mpc8569-elbc", "fsl,elbc", "simple-bus";
	interrupts = <19 2 0 0>;
	sleep = <&pmc 0x08000000>;
};

/* controller at 0xa000 */
&pci1 {
	compatible = "fsl,mpc8548-pcie";
	device_type = "pci";
	#size-cells = <2>;
	#address-cells = <3>;
	bus-range = <0 255>;
	clock-frequency = <33333333>;
	interrupts = <26 2 0 0>;
	sleep = <&pmc 0x20000000>;

	pcie@0 {
		reg = <0 0 0 0 0>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		device_type = "pci";
		interrupts = <26 2 0 0>;
		interrupt-map-mask = <0xf800 0 0 7>;
		interrupt-map = <
			/* IDSEL 0x0 */
			0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
			0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
			0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
			0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
			>;
	};
};

&rio {
	compatible = "fsl,srio";
	interrupts = <48 2 0 0>;
	#address-cells = <2>;
	#size-cells = <2>;
	fsl,srio-rmu-handle = <&rmu>;
	sleep = <&pmc 0x00080000>;
	ranges;

	port1 {
		#address-cells = <2>;
		#size-cells = <2>;
		cell-index = <1>;
	};

	port2 {
		#address-cells = <2>;
		#size-cells = <2>;
		cell-index = <2>;
	};
};

&soc {
	#address-cells = <1>;
	#size-cells = <1>;
	device_type = "soc";
	compatible = "fsl,mpc8569-immr", "simple-bus";
	bus-frequency = <0>;		// Filled out by uboot.

	ecm-law@0 {
		compatible = "fsl,ecm-law";
		reg = <0x0 0x1000>;
		fsl,num-laws = <10>;
	};

	ecm@1000 {
		compatible = "fsl,mpc8569-ecm", "fsl,ecm";
		reg = <0x1000 0x1000>;
		interrupts = <17 2 0 0>;
	};

	memory-controller@2000 {
		compatible = "fsl,mpc8569-memory-controller";
		reg = <0x2000 0x1000>;
		interrupts = <18 2 0 0>;
	};

	i2c-sleep-nexus {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		sleep = <&pmc 0x00000004>;
		ranges;

/include/ "pq3-i2c-0.dtsi"
/include/ "pq3-i2c-1.dtsi"

	};

	duart-sleep-nexus {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		sleep = <&pmc 0x00000002>;
		ranges;

/include/ "pq3-duart-0.dtsi"

	};

	L2: l2-cache-controller@20000 {
		compatible = "fsl,mpc8569-l2-cache-controller";
		reg = <0x20000 0x1000>;
		cache-line-size = <32>;	// 32 bytes
		cache-size = <0x80000>; // L2, 512K
		interrupts = <16 2 0 0>;
	};

/include/ "pq3-dma-0.dtsi"
/include/ "pq3-esdhc-0.dtsi"
	sdhc@2e000 {
		sleep = <&pmc 0x00200000>;
	};

	par_io@e0100 {
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0xe0100 0x100>;
		ranges = <0x0 0xe0100 0x100>;
		device_type = "par_io";
	};

/include/ "pq3-sec3.1-0.dtsi"
	crypto@30000 {
		sleep = <&pmc 0x01000000>;
	};

/include/ "pq3-mpic.dtsi"
/include/ "pq3-rmu-0.dtsi"
	rmu@d3000 {
		sleep = <&pmc 0x00040000>;
	};

	global-utilities@e0000 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "fsl,mpc8569-guts", "fsl,mpc8548-guts";
		reg = <0xe0000 0x1000>;
		ranges = <0 0xe0000 0x1000>;
		fsl,has-rstcr;

		pmc: power@70 {
			compatible = "fsl,mpc8569-pmc",
				     "fsl,mpc8548-pmc";
			reg = <0x70 0x20>;
		};
	};
};

&qe {
	#address-cells = <1>;
	#size-cells = <1>;
	device_type = "qe";
	compatible = "fsl,qe";
	sleep = <&pmc 0x00000800>;
	brg-frequency = <0>;
	bus-frequency = <0>;
	fsl,qe-num-riscs = <4>;
	fsl,qe-num-snums = <46>;

	qeic: interrupt-controller@80 {
		interrupt-controller;
		compatible = "fsl,qe-ic";
		#address-cells = <0>;
		#interrupt-cells = <1>;
		reg = <0x80 0x80>;
		interrupts = <46 2 0 0 46 2 0 0>; //high:30 low:30
		interrupt-parent = <&mpic>;
	};

	timer@440 {
		compatible = "fsl,mpc8569-qe-gtm",
			     "fsl,qe-gtm", "fsl,gtm";
		reg = <0x440 0x40>;
		interrupts = <12 13 14 15>;
		interrupt-parent = <&qeic>;
		/* Filled in by U-Boot */
		clock-frequency = <0>;
	};

	spi@4c0 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "fsl,mpc8569-qe-spi", "fsl,spi";
		reg = <0x4c0 0x40>;
		cell-index = <0>;
		interrupts = <2>;
		interrupt-parent = <&qeic>;
	};

	spi@500 {
		#address-cells = <1>;
		#size-cells = <0>;
		cell-index = <1>;
		compatible = "fsl,spi";
		reg = <0x500 0x40>;
		interrupts = <1>;
		interrupt-parent = <&qeic>;
	};

	usb@6c0 {
		compatible = "fsl,mpc8569-qe-usb",
			     "fsl,mpc8323-qe-usb";
		reg = <0x6c0 0x40 0x8b00 0x100>;
		interrupts = <11>;
		interrupt-parent = <&qeic>;
	};

	ucc@2000 {
		cell-index = <1>;
		reg = <0x2000 0x200>;
		interrupts = <32>;
		interrupt-parent = <&qeic>;
	};

	ucc@2200 {
		cell-index = <3>;
		reg = <0x2200 0x200>;
		interrupts = <34>;
		interrupt-parent = <&qeic>;
	};

	ucc@3000 {
		cell-index = <2>;
		reg = <0x3000 0x200>;
		interrupts = <33>;
		interrupt-parent = <&qeic>;
	};

	ucc@3200 {
		cell-index = <4>;
		reg = <0x3200 0x200>;
		interrupts = <35>;
		interrupt-parent = <&qeic>;
	};

	ucc@3400 {
		cell-index = <6>;
		reg = <0x3400 0x200>;
		interrupts = <41>;
		interrupt-parent = <&qeic>;
	};

	ucc@3600 {
		cell-index = <8>;
		reg = <0x3600 0x200>;
		interrupts = <43>;
		interrupt-parent = <&qeic>;
	};

	muram@10000 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "fsl,qe-muram", "fsl,cpm-muram";
		ranges = <0x0 0x10000 0x20000>;

		data-only@0 {
			compatible = "fsl,qe-muram-data",
				     "fsl,cpm-muram-data";
			reg = <0x0 0x20000>;
		};
	};
};