blob: 05641980dc5e7c86ede296ef01129be70fea653b [file] [log] [blame]
Andre Silvabd897822011-06-10 13:08:14 -03001/*
2 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#include <linux/init.h>
22#include <linux/clk.h>
23#include <linux/delay.h>
24#include <linux/gpio.h>
25#include <linux/smsc911x.h>
Fabio Estevamfd36dfb2012-04-02 10:39:43 -030026#include <linux/regulator/machine.h>
27#include <linux/regulator/fixed.h>
Andre Silvabd897822011-06-10 13:08:14 -030028
29#include <mach/common.h>
30#include <mach/hardware.h>
31#include <mach/iomux-mx53.h>
32
33#include <asm/mach-types.h>
34#include <asm/mach/arch.h>
35#include <asm/mach/time.h>
36
Andre Silvabd897822011-06-10 13:08:14 -030037#include "devices-imx53.h"
38
39#define ARD_ETHERNET_INT_B IMX_GPIO_NR(2, 31)
Andre Silvae3a58be2011-06-13 14:31:57 -030040#define ARD_SD1_CD IMX_GPIO_NR(1, 1)
41#define ARD_SD1_WP IMX_GPIO_NR(1, 9)
Fabio Estevamd23cb572011-06-25 13:28:53 -030042#define ARD_I2CPORTEXP_B IMX_GPIO_NR(2, 3)
Daiane Angolini2a90a692011-06-30 14:41:46 -030043#define ARD_VOLUMEDOWN IMX_GPIO_NR(4, 0)
44#define ARD_HOME IMX_GPIO_NR(5, 10)
45#define ARD_BACK IMX_GPIO_NR(5, 11)
46#define ARD_PROG IMX_GPIO_NR(5, 12)
47#define ARD_VOLUMEUP IMX_GPIO_NR(5, 13)
Andre Silvabd897822011-06-10 13:08:14 -030048
49static iomux_v3_cfg_t mx53_ard_pads[] = {
50 /* UART1 */
51 MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
52 MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
53 /* WEIM for CS1 */
54 MX53_PAD_EIM_EB3__GPIO2_31, /* ETHERNET_INT_B */
55 MX53_PAD_EIM_D16__EMI_WEIM_D_16,
56 MX53_PAD_EIM_D17__EMI_WEIM_D_17,
57 MX53_PAD_EIM_D18__EMI_WEIM_D_18,
58 MX53_PAD_EIM_D19__EMI_WEIM_D_19,
59 MX53_PAD_EIM_D20__EMI_WEIM_D_20,
60 MX53_PAD_EIM_D21__EMI_WEIM_D_21,
61 MX53_PAD_EIM_D22__EMI_WEIM_D_22,
62 MX53_PAD_EIM_D23__EMI_WEIM_D_23,
63 MX53_PAD_EIM_D24__EMI_WEIM_D_24,
64 MX53_PAD_EIM_D25__EMI_WEIM_D_25,
65 MX53_PAD_EIM_D26__EMI_WEIM_D_26,
66 MX53_PAD_EIM_D27__EMI_WEIM_D_27,
67 MX53_PAD_EIM_D28__EMI_WEIM_D_28,
68 MX53_PAD_EIM_D29__EMI_WEIM_D_29,
69 MX53_PAD_EIM_D30__EMI_WEIM_D_30,
70 MX53_PAD_EIM_D31__EMI_WEIM_D_31,
71 MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0,
72 MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1,
73 MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2,
74 MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3,
75 MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4,
76 MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5,
77 MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6,
78 MX53_PAD_EIM_OE__EMI_WEIM_OE,
79 MX53_PAD_EIM_RW__EMI_WEIM_RW,
80 MX53_PAD_EIM_CS1__EMI_WEIM_CS_1,
Andre Silvae3a58be2011-06-13 14:31:57 -030081 /* SDHC1 */
82 MX53_PAD_SD1_CMD__ESDHC1_CMD,
83 MX53_PAD_SD1_CLK__ESDHC1_CLK,
84 MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
85 MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
86 MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
87 MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
88 MX53_PAD_PATA_DATA8__ESDHC1_DAT4,
89 MX53_PAD_PATA_DATA9__ESDHC1_DAT5,
90 MX53_PAD_PATA_DATA10__ESDHC1_DAT6,
91 MX53_PAD_PATA_DATA11__ESDHC1_DAT7,
92 MX53_PAD_GPIO_1__GPIO1_1,
93 MX53_PAD_GPIO_9__GPIO1_9,
Andre Silva8dd7b812011-06-22 16:33:05 -030094 /* I2C2 */
95 MX53_PAD_EIM_EB2__I2C2_SCL,
96 MX53_PAD_KEY_ROW3__I2C2_SDA,
97 /* I2C3 */
98 MX53_PAD_GPIO_3__I2C3_SCL,
99 MX53_PAD_GPIO_16__I2C3_SDA,
Daiane Angolini2a90a692011-06-30 14:41:46 -0300100 /* GPIO */
101 MX53_PAD_DISP0_DAT16__GPIO5_10, /* home */
102 MX53_PAD_DISP0_DAT17__GPIO5_11, /* back */
103 MX53_PAD_DISP0_DAT18__GPIO5_12, /* prog */
104 MX53_PAD_DISP0_DAT19__GPIO5_13, /* vol up */
105 MX53_PAD_GPIO_10__GPIO4_0, /* vol down */
106};
107
108#define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake) \
109{ \
110 .gpio = gpio_num, \
111 .type = EV_KEY, \
112 .code = ev_code, \
113 .active_low = act_low, \
114 .desc = "btn " descr, \
115 .wakeup = wake, \
116}
117
118static struct gpio_keys_button ard_buttons[] = {
119 GPIO_BUTTON(ARD_HOME, KEY_HOME, 1, "home", 0),
120 GPIO_BUTTON(ARD_BACK, KEY_BACK, 1, "back", 0),
121 GPIO_BUTTON(ARD_PROG, KEY_PROGRAM, 1, "program", 0),
122 GPIO_BUTTON(ARD_VOLUMEUP, KEY_VOLUMEUP, 1, "volume-up", 0),
123 GPIO_BUTTON(ARD_VOLUMEDOWN, KEY_VOLUMEDOWN, 1, "volume-down", 0),
124};
125
126static const struct gpio_keys_platform_data ard_button_data __initconst = {
127 .buttons = ard_buttons,
128 .nbuttons = ARRAY_SIZE(ard_buttons),
Andre Silvabd897822011-06-10 13:08:14 -0300129};
130
131static struct resource ard_smsc911x_resources[] = {
132 {
133 .start = MX53_CS1_64MB_BASE_ADDR,
134 .end = MX53_CS1_64MB_BASE_ADDR + SZ_32M - 1,
135 .flags = IORESOURCE_MEM,
136 },
137 {
Shawn Guoe309fb12011-08-14 00:14:01 +0800138 .start = IMX_GPIO_TO_IRQ(ARD_ETHERNET_INT_B),
139 .end = IMX_GPIO_TO_IRQ(ARD_ETHERNET_INT_B),
Andre Silvabd897822011-06-10 13:08:14 -0300140 .flags = IORESOURCE_IRQ,
141 },
142};
143
144struct smsc911x_platform_config ard_smsc911x_config = {
145 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
146 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
147 .flags = SMSC911X_USE_32BIT,
148};
149
150static struct platform_device ard_smsc_lan9220_device = {
151 .name = "smsc911x",
152 .id = -1,
153 .num_resources = ARRAY_SIZE(ard_smsc911x_resources),
154 .resource = ard_smsc911x_resources,
155 .dev = {
156 .platform_data = &ard_smsc911x_config,
157 },
158};
159
Andre Silvae3a58be2011-06-13 14:31:57 -0300160static const struct esdhc_platform_data mx53_ard_sd1_data __initconst = {
161 .cd_gpio = ARD_SD1_CD,
162 .wp_gpio = ARD_SD1_WP,
163};
164
Andre Silva8dd7b812011-06-22 16:33:05 -0300165static struct imxi2c_platform_data mx53_ard_i2c2_data = {
166 .bitrate = 50000,
167};
168
169static struct imxi2c_platform_data mx53_ard_i2c3_data = {
170 .bitrate = 400000,
171};
172
Andre Silvabd897822011-06-10 13:08:14 -0300173static void __init mx53_ard_io_init(void)
174{
Andre Silvabd897822011-06-10 13:08:14 -0300175 gpio_request(ARD_ETHERNET_INT_B, "eth-int-b");
176 gpio_direction_input(ARD_ETHERNET_INT_B);
Andre Silva8dd7b812011-06-22 16:33:05 -0300177
178 gpio_request(ARD_I2CPORTEXP_B, "i2cptexp-rst");
179 gpio_direction_output(ARD_I2CPORTEXP_B, 1);
Andre Silvabd897822011-06-10 13:08:14 -0300180}
181
Andre Silva8dd7b812011-06-22 16:33:05 -0300182/* Config CS1 settings for ethernet controller */
Andre Silvabd897822011-06-10 13:08:14 -0300183static int weim_cs_config(void)
184{
185 u32 reg;
186 void __iomem *weim_base, *iomuxc_base;
187
188 weim_base = ioremap(MX53_WEIM_BASE_ADDR, SZ_4K);
189 if (!weim_base)
190 return -ENOMEM;
191
192 iomuxc_base = ioremap(MX53_IOMUXC_BASE_ADDR, SZ_4K);
Julia Lawall945f82f2012-01-12 10:55:12 +0100193 if (!iomuxc_base) {
194 iounmap(weim_base);
Andre Silvabd897822011-06-10 13:08:14 -0300195 return -ENOMEM;
Julia Lawall945f82f2012-01-12 10:55:12 +0100196 }
Andre Silvabd897822011-06-10 13:08:14 -0300197
198 /* CS1 timings for LAN9220 */
199 writel(0x20001, (weim_base + 0x18));
200 writel(0x0, (weim_base + 0x1C));
201 writel(0x16000202, (weim_base + 0x20));
202 writel(0x00000002, (weim_base + 0x24));
203 writel(0x16002082, (weim_base + 0x28));
204 writel(0x00000000, (weim_base + 0x2C));
205 writel(0x00000000, (weim_base + 0x90));
206
207 /* specify 64 MB on CS1 and CS0 on GPR1 */
208 reg = readl(iomuxc_base + 0x4);
209 reg &= ~0x3F;
210 reg |= 0x1B;
211 writel(reg, (iomuxc_base + 0x4));
212
213 iounmap(iomuxc_base);
214 iounmap(weim_base);
215
216 return 0;
217}
218
Fabio Estevamfd36dfb2012-04-02 10:39:43 -0300219static struct regulator_consumer_supply dummy_supplies[] = {
220 REGULATOR_SUPPLY("vdd33a", "smsc911x"),
221 REGULATOR_SUPPLY("vddvario", "smsc911x"),
222};
223
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800224void __init imx53_ard_common_init(void)
225{
226 mxc_iomux_v3_setup_multiple_pads(mx53_ard_pads,
227 ARRAY_SIZE(mx53_ard_pads));
228 weim_cs_config();
229}
230
Andre Silvabd897822011-06-10 13:08:14 -0300231static struct platform_device *devices[] __initdata = {
232 &ard_smsc_lan9220_device,
233};
234
235static void __init mx53_ard_board_init(void)
236{
237 imx53_soc_init();
238 imx53_add_imx_uart(0, NULL);
239
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800240 imx53_ard_common_init();
Andre Silvabd897822011-06-10 13:08:14 -0300241 mx53_ard_io_init();
Fabio Estevamfd36dfb2012-04-02 10:39:43 -0300242 regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
Andre Silvabd897822011-06-10 13:08:14 -0300243 platform_add_devices(devices, ARRAY_SIZE(devices));
Andre Silvae3a58be2011-06-13 14:31:57 -0300244
245 imx53_add_sdhci_esdhc_imx(0, &mx53_ard_sd1_data);
Andre Silva40d32c82011-06-13 14:31:58 -0300246 imx53_add_imx2_wdt(0, NULL);
Andre Silva8dd7b812011-06-22 16:33:05 -0300247 imx53_add_imx_i2c(1, &mx53_ard_i2c2_data);
248 imx53_add_imx_i2c(2, &mx53_ard_i2c3_data);
Daiane Angolini2a90a692011-06-30 14:41:46 -0300249 imx_add_gpio_keys(&ard_button_data);
Richard Zhue97e3032011-09-28 15:41:55 +0800250 imx53_add_ahci_imx();
Andre Silvabd897822011-06-10 13:08:14 -0300251}
252
253static void __init mx53_ard_timer_init(void)
254{
255 mx53_clocks_init(32768, 24000000, 22579200, 0);
256}
257
258static struct sys_timer mx53_ard_timer = {
259 .init = mx53_ard_timer_init,
260};
261
262MACHINE_START(MX53_ARD, "Freescale MX53 ARD Board")
263 .map_io = mx53_map_io,
264 .init_early = imx53_init_early,
265 .init_irq = mx53_init_irq,
Sascha Hauerffa2ea32011-09-20 14:31:24 +0200266 .handle_irq = imx53_handle_irq,
Andre Silvabd897822011-06-10 13:08:14 -0300267 .timer = &mx53_ard_timer,
268 .init_machine = mx53_ard_board_init,
Russell King65ea7882011-11-06 17:12:08 +0000269 .restart = mxc_restart,
Andre Silvabd897822011-06-10 13:08:14 -0300270MACHINE_END