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Giuseppe CAVALLARO21d437c2010-01-06 23:07:20 +00001/*******************************************************************************
2 This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
3 DWC Ether MAC 10/100/1000 Universal version 3.41a has been used for
4 developing this code.
5
Giuseppe CAVALLARO56b106a2010-04-13 20:21:12 +00006 This contains the functions to handle the dma.
Giuseppe CAVALLARO21d437c2010-01-06 23:07:20 +00007
8 Copyright (C) 2007-2009 STMicroelectronics Ltd
9
10 This program is free software; you can redistribute it and/or modify it
11 under the terms and conditions of the GNU General Public License,
12 version 2, as published by the Free Software Foundation.
13
14 This program is distributed in the hope it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 more details.
18
19 You should have received a copy of the GNU General Public License along with
20 this program; if not, write to the Free Software Foundation, Inc.,
21 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
22
23 The full GNU General Public License is included in this distribution in
24 the file called "COPYING".
25
26 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
27*******************************************************************************/
28
29#include "dwmac1000.h"
30#include "dwmac_dma.h"
31
32static int dwmac1000_dma_init(unsigned long ioaddr, int pbl, u32 dma_tx,
33 u32 dma_rx)
34{
35 u32 value = readl(ioaddr + DMA_BUS_MODE);
36 /* DMA SW reset */
37 value |= DMA_BUS_MODE_SFT_RESET;
38 writel(value, ioaddr + DMA_BUS_MODE);
39 do {} while ((readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET));
40
41 value = /* DMA_BUS_MODE_FB | */ DMA_BUS_MODE_4PBL |
42 ((pbl << DMA_BUS_MODE_PBL_SHIFT) |
43 (pbl << DMA_BUS_MODE_RPBL_SHIFT));
44
45#ifdef CONFIG_STMMAC_DA
46 value |= DMA_BUS_MODE_DA; /* Rx has priority over tx */
47#endif
48 writel(value, ioaddr + DMA_BUS_MODE);
49
50 /* Mask interrupts by writing to CSR7 */
51 writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);
52
53 /* The base address of the RX/TX descriptor lists must be written into
54 * DMA CSR3 and CSR4, respectively. */
55 writel(dma_tx, ioaddr + DMA_TX_BASE_ADDR);
56 writel(dma_rx, ioaddr + DMA_RCV_BASE_ADDR);
57
58 return 0;
59}
60
61/* Transmit FIFO flush operation */
62static void dwmac1000_flush_tx_fifo(unsigned long ioaddr)
63{
64 u32 csr6 = readl(ioaddr + DMA_CONTROL);
65 writel((csr6 | DMA_CONTROL_FTF), ioaddr + DMA_CONTROL);
66
67 do {} while ((readl(ioaddr + DMA_CONTROL) & DMA_CONTROL_FTF));
68}
69
70static void dwmac1000_dma_operation_mode(unsigned long ioaddr, int txmode,
71 int rxmode)
72{
73 u32 csr6 = readl(ioaddr + DMA_CONTROL);
74
75 if (txmode == SF_DMA_MODE) {
Giuseppe CAVALLARO56b106a2010-04-13 20:21:12 +000076 CHIP_DBG(KERN_DEBUG "GMAC: enable TX store and forward mode\n");
Giuseppe CAVALLARO21d437c2010-01-06 23:07:20 +000077 /* Transmit COE type 2 cannot be done in cut-through mode. */
78 csr6 |= DMA_CONTROL_TSF;
79 /* Operating on second frame increase the performance
80 * especially when transmit store-and-forward is used.*/
81 csr6 |= DMA_CONTROL_OSF;
82 } else {
Giuseppe CAVALLARO56b106a2010-04-13 20:21:12 +000083 CHIP_DBG(KERN_DEBUG "GMAC: disabling TX store and forward mode"
Giuseppe CAVALLARO21d437c2010-01-06 23:07:20 +000084 " (threshold = %d)\n", txmode);
85 csr6 &= ~DMA_CONTROL_TSF;
86 csr6 &= DMA_CONTROL_TC_TX_MASK;
87 /* Set the transmit threshold */
88 if (txmode <= 32)
89 csr6 |= DMA_CONTROL_TTC_32;
90 else if (txmode <= 64)
91 csr6 |= DMA_CONTROL_TTC_64;
92 else if (txmode <= 128)
93 csr6 |= DMA_CONTROL_TTC_128;
94 else if (txmode <= 192)
95 csr6 |= DMA_CONTROL_TTC_192;
96 else
97 csr6 |= DMA_CONTROL_TTC_256;
98 }
99
100 if (rxmode == SF_DMA_MODE) {
Giuseppe CAVALLARO56b106a2010-04-13 20:21:12 +0000101 CHIP_DBG(KERN_DEBUG "GMAC: enable RX store and forward mode\n");
Giuseppe CAVALLARO21d437c2010-01-06 23:07:20 +0000102 csr6 |= DMA_CONTROL_RSF;
103 } else {
Giuseppe CAVALLARO56b106a2010-04-13 20:21:12 +0000104 CHIP_DBG(KERN_DEBUG "GMAC: disabling RX store and forward mode"
Giuseppe CAVALLARO21d437c2010-01-06 23:07:20 +0000105 " (threshold = %d)\n", rxmode);
106 csr6 &= ~DMA_CONTROL_RSF;
107 csr6 &= DMA_CONTROL_TC_RX_MASK;
108 if (rxmode <= 32)
109 csr6 |= DMA_CONTROL_RTC_32;
110 else if (rxmode <= 64)
111 csr6 |= DMA_CONTROL_RTC_64;
112 else if (rxmode <= 96)
113 csr6 |= DMA_CONTROL_RTC_96;
114 else
115 csr6 |= DMA_CONTROL_RTC_128;
116 }
117
118 writel(csr6, ioaddr + DMA_CONTROL);
119 return;
120}
121
122/* Not yet implemented --- no RMON module */
123static void dwmac1000_dma_diagnostic_fr(void *data,
124 struct stmmac_extra_stats *x, unsigned long ioaddr)
125{
126 return;
127}
128
129static void dwmac1000_dump_dma_regs(unsigned long ioaddr)
130{
131 int i;
132 pr_info(" DMA registers\n");
133 for (i = 0; i < 22; i++) {
134 if ((i < 9) || (i > 17)) {
135 int offset = i * 4;
136 pr_err("\t Reg No. %d (offset 0x%x): 0x%08x\n", i,
137 (DMA_BUS_MODE + offset),
138 readl(ioaddr + DMA_BUS_MODE + offset));
139 }
140 }
141 return;
142}
143
Giuseppe CAVALLARO21d437c2010-01-06 23:07:20 +0000144struct stmmac_dma_ops dwmac1000_dma_ops = {
145 .init = dwmac1000_dma_init,
146 .dump_regs = dwmac1000_dump_dma_regs,
147 .dma_mode = dwmac1000_dma_operation_mode,
148 .dma_diagnostic_fr = dwmac1000_dma_diagnostic_fr,
149 .enable_dma_transmission = dwmac_enable_dma_transmission,
150 .enable_dma_irq = dwmac_enable_dma_irq,
151 .disable_dma_irq = dwmac_disable_dma_irq,
152 .start_tx = dwmac_dma_start_tx,
153 .stop_tx = dwmac_dma_stop_tx,
154 .start_rx = dwmac_dma_start_rx,
155 .stop_rx = dwmac_dma_stop_rx,
156 .dma_interrupt = dwmac_dma_interrupt,
157};