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gerrit-public.fairphone.software / kernel / msm-4.19 / 570ef608591aa1c7f7cb615c2d33b30246179da1 / . / drivers / gpu / drm / i915 / intel_ringbuffer.h
blob: af09eaa84bed703703b5e2ba616762395544d244 [file] [log] [blame]
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800[diff] [blame]1#ifndef _INTEL_RINGBUFFER_H_
2#define _INTEL_RINGBUFFER_H_
3
4struct intel_hw_status_page {
5 void *page_addr;
6 unsigned int gfx_addr;
7 struct drm_gem_object *obj;
8};
9
Daniel Vetter870e86d2010-08-02 16:29:44 +0200[diff] [blame]10#define I915_READ_TAIL(ring) I915_READ(RING_TAIL(ring->mmio_base))
11#define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL(ring->mmio_base), val)
Daniel Vetter6c0e1c52010-08-02 16:33:33 +0200[diff] [blame]12#define I915_READ_START(ring) I915_READ(RING_START(ring->mmio_base))
13#define I915_WRITE_START(ring, val) I915_WRITE(RING_START(ring->mmio_base), val)
Daniel Vetter570ef602010-08-02 17:06:23 +0200[diff] [blame^]14#define I915_READ_HEAD(ring) I915_READ(RING_HEAD(ring->mmio_base))
15#define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD(ring->mmio_base), val)
Daniel Vetter870e86d2010-08-02 16:29:44 +0200[diff] [blame]16
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800[diff] [blame]17struct drm_i915_gem_execbuffer2;
18struct intel_ring_buffer {
19 const char *name;
Chris Wilson92204342010-09-18 11:02:01 +0100[diff] [blame]20 enum intel_ring_id {
21 RING_RENDER = 0x1,
22 RING_BSD = 0x2,
23 } id;
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800[diff] [blame]24 struct ring_regs {
25 u32 ctl;
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800[diff] [blame]26 } regs;
Daniel Vetter333e9fe2010-08-02 16:24:01 +0200[diff] [blame]27 u32 mmio_base;
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800[diff] [blame]28 unsigned long size;
29 unsigned int alignment;
30 void *virtual_start;
31 struct drm_device *dev;
32 struct drm_gem_object *gem_object;
33
34 unsigned int head;
35 unsigned int tail;
36 unsigned int space;
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800[diff] [blame]37 struct intel_hw_status_page status_page;
38
39 u32 irq_gem_seqno; /* last seq seem at irq time */
40 u32 waiting_gem_seqno;
41 int user_irq_refcount;
42 void (*user_irq_get)(struct drm_device *dev,
43 struct intel_ring_buffer *ring);
44 void (*user_irq_put)(struct drm_device *dev,
45 struct intel_ring_buffer *ring);
46 void (*setup_status_page)(struct drm_device *dev,
47 struct intel_ring_buffer *ring);
48
49 int (*init)(struct drm_device *dev,
50 struct intel_ring_buffer *ring);
51
Xiang, Haihaod46eefa2010-09-16 10:43:12 +0800[diff] [blame]52 void (*set_tail)(struct drm_device *dev,
Daniel Vetter870e86d2010-08-02 16:29:44 +0200[diff] [blame]53 struct intel_ring_buffer *ring,
54 u32 value);
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800[diff] [blame]55 unsigned int (*get_active_head)(struct drm_device *dev,
56 struct intel_ring_buffer *ring);
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800[diff] [blame]57 void (*flush)(struct drm_device *dev,
58 struct intel_ring_buffer *ring,
59 u32 invalidate_domains,
60 u32 flush_domains);
61 u32 (*add_request)(struct drm_device *dev,
62 struct intel_ring_buffer *ring,
63 struct drm_file *file_priv,
64 u32 flush_domains);
65 u32 (*get_gem_seqno)(struct drm_device *dev,
66 struct intel_ring_buffer *ring);
67 int (*dispatch_gem_execbuffer)(struct drm_device *dev,
68 struct intel_ring_buffer *ring,
69 struct drm_i915_gem_execbuffer2 *exec,
70 struct drm_clip_rect *cliprects,
71 uint64_t exec_offset);
72
73 /**
74 * List of objects currently involved in rendering from the
75 * ringbuffer.
76 *
77 * Includes buffers having the contents of their GPU caches
78 * flushed, not necessarily primitives. last_rendering_seqno
79 * represents when the rendering involved will be completed.
80 *
81 * A reference is held on the buffer while on this list.
82 */
83 struct list_head active_list;
84
85 /**
86 * List of breadcrumbs associated with GPU requests currently
87 * outstanding.
88 */
89 struct list_head request_list;
90
Daniel Vettera6910432010-02-02 17:08:37 +0100[diff] [blame]91 /**
92 * Do we have some not yet emitted requests outstanding?
93 */
94 bool outstanding_lazy_request;
95
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800[diff] [blame]96 wait_queue_head_t irq_queue;
97 drm_local_map_t map;
98};
99
100static inline u32
101intel_read_status_page(struct intel_ring_buffer *ring,
102 int reg)
103{
104 u32 *regs = ring->status_page.page_addr;
105 return regs[reg];
106}
107
108int intel_init_ring_buffer(struct drm_device *dev,
109 struct intel_ring_buffer *ring);
110void intel_cleanup_ring_buffer(struct drm_device *dev,
111 struct intel_ring_buffer *ring);
112int intel_wait_ring_buffer(struct drm_device *dev,
113 struct intel_ring_buffer *ring, int n);
114int intel_wrap_ring_buffer(struct drm_device *dev,
115 struct intel_ring_buffer *ring);
116void intel_ring_begin(struct drm_device *dev,
117 struct intel_ring_buffer *ring, int n);
Chris Wilsone898cd22010-08-04 15:18:14 +0100[diff] [blame]118
119static inline void intel_ring_emit(struct drm_device *dev,
120 struct intel_ring_buffer *ring,
121 unsigned int data)
122{
123 unsigned int *virt = ring->virtual_start + ring->tail;
124 *virt = data;
125 ring->tail += 4;
126}
127
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800[diff] [blame]128void intel_fill_struct(struct drm_device *dev,
129 struct intel_ring_buffer *ring,
130 void *data,
131 unsigned int len);
132void intel_ring_advance(struct drm_device *dev,
133 struct intel_ring_buffer *ring);
134
135u32 intel_ring_get_seqno(struct drm_device *dev,
136 struct intel_ring_buffer *ring);
137
Xiang, Haihao5c1143b2010-09-16 10:43:11 +0800[diff] [blame]138int intel_init_render_ring_buffer(struct drm_device *dev);
139int intel_init_bsd_ring_buffer(struct drm_device *dev);
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800[diff] [blame]140
141#endif /* _INTEL_RINGBUFFER_H_ */