blob: 78f7e919ab6f51397db0638938b0806ccfa6c069 [file] [log] [blame]
Stephen Warren1bd0bd42012-10-17 16:38:21 -06001#include "tegra20.dtsi"
Lucas Stachfc9c7132013-01-22 22:46:08 +01002
3/ {
4 model = "Toradex Colibri T20 512MB";
5 compatible = "toradex,colibri_t20-512", "nvidia,tegra20";
6
7 memory {
8 reg = <0x00000000 0x20000000>;
9 };
10
Stephen Warren58ecb232013-11-25 17:53:16 -070011 host1x@50000000 {
12 hdmi@54280000 {
Lucas Stachfc9c7132013-01-22 22:46:08 +010013 vdd-supply = <&hdmi_vdd_reg>;
14 pll-supply = <&hdmi_pll_reg>;
15
16 nvidia,ddc-i2c-bus = <&i2c_ddc>;
Stephen Warren3325f1b2013-02-12 17:25:15 -070017 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
18 GPIO_ACTIVE_HIGH>;
Lucas Stachfc9c7132013-01-22 22:46:08 +010019 };
20 };
21
Stephen Warren58ecb232013-11-25 17:53:16 -070022 pinmux@70000014 {
Lucas Stachfc9c7132013-01-22 22:46:08 +010023 pinctrl-names = "default";
24 pinctrl-0 = <&state_default>;
25
26 state_default: pinmux {
27 audio_refclk {
28 nvidia,pins = "cdev1";
29 nvidia,function = "plla_out";
30 nvidia,pull = <0>;
31 nvidia,tristate = <0>;
32 };
33 crt {
34 nvidia,pins = "crtp";
35 nvidia,function = "crt";
36 nvidia,pull = <0>;
37 nvidia,tristate = <1>;
38 };
39 dap3 {
40 nvidia,pins = "dap3";
41 nvidia,function = "dap3";
42 nvidia,pull = <0>;
43 nvidia,tristate = <0>;
44 };
45 displaya {
46 nvidia,pins = "ld0", "ld1", "ld2", "ld3",
47 "ld4", "ld5", "ld6", "ld7", "ld8",
48 "ld9", "ld10", "ld11", "ld12", "ld13",
49 "ld14", "ld15", "ld16", "ld17",
50 "lhs", "lpw0", "lpw2", "lsc0",
51 "lsc1", "lsck", "lsda", "lspi", "lvs";
52 nvidia,function = "displaya";
53 nvidia,tristate = <1>;
54 };
55 gpio_dte {
56 nvidia,pins = "dte";
57 nvidia,function = "rsvd1";
58 nvidia,pull = <0>;
59 nvidia,tristate = <0>;
60 };
61 gpio_gmi {
62 nvidia,pins = "ata", "atc", "atd", "ate",
63 "dap1", "dap2", "dap4", "gpu", "irrx",
64 "irtx", "spia", "spib", "spic";
65 nvidia,function = "gmi";
66 nvidia,pull = <0>;
67 nvidia,tristate = <0>;
68 };
69 gpio_pta {
70 nvidia,pins = "pta";
71 nvidia,function = "rsvd4";
72 nvidia,pull = <0>;
73 nvidia,tristate = <0>;
74 };
75 gpio_uac {
76 nvidia,pins = "uac";
77 nvidia,function = "rsvd2";
78 nvidia,pull = <0>;
79 nvidia,tristate = <0>;
80 };
81 hdint {
82 nvidia,pins = "hdint";
83 nvidia,function = "hdmi";
84 nvidia,tristate = <1>;
85 };
86 i2c1 {
87 nvidia,pins = "rm";
88 nvidia,function = "i2c1";
89 nvidia,pull = <0>;
90 nvidia,tristate = <1>;
91 };
92 i2c3 {
93 nvidia,pins = "dtf";
94 nvidia,function = "i2c3";
95 nvidia,pull = <0>;
96 nvidia,tristate = <1>;
97 };
98 i2cddc {
99 nvidia,pins = "ddc";
100 nvidia,function = "i2c2";
101 nvidia,pull = <2>;
102 nvidia,tristate = <1>;
103 };
104 i2cp {
105 nvidia,pins = "i2cp";
106 nvidia,function = "i2cp";
107 nvidia,pull = <0>;
108 nvidia,tristate = <0>;
109 };
110 irda {
111 nvidia,pins = "uad";
112 nvidia,function = "irda";
113 nvidia,pull = <0>;
114 nvidia,tristate = <1>;
115 };
116 nand {
117 nvidia,pins = "kbca", "kbcc", "kbcd",
118 "kbce", "kbcf";
119 nvidia,function = "nand";
120 nvidia,pull = <0>;
121 nvidia,tristate = <0>;
122 };
123 owc {
124 nvidia,pins = "owc";
125 nvidia,function = "owr";
126 nvidia,pull = <0>;
127 nvidia,tristate = <1>;
128 };
129 pmc {
130 nvidia,pins = "pmc";
131 nvidia,function = "pwr_on";
132 nvidia,tristate = <0>;
133 };
134 pwm {
135 nvidia,pins = "sdb", "sdc", "sdd";
136 nvidia,function = "pwm";
137 nvidia,tristate = <1>;
138 };
139 sdio4 {
140 nvidia,pins = "atb", "gma", "gme";
141 nvidia,function = "sdio4";
142 nvidia,pull = <0>;
143 nvidia,tristate = <1>;
144 };
145 spi1 {
146 nvidia,pins = "spid", "spie", "spif";
147 nvidia,function = "spi1";
148 nvidia,pull = <0>;
149 nvidia,tristate = <1>;
150 };
151 spi4 {
152 nvidia,pins = "slxa", "slxc", "slxd", "slxk";
153 nvidia,function = "spi4";
154 nvidia,pull = <0>;
155 nvidia,tristate = <1>;
156 };
157 uarta {
158 nvidia,pins = "sdio1";
159 nvidia,function = "uarta";
160 nvidia,pull = <0>;
161 nvidia,tristate = <1>;
162 };
163 uartd {
164 nvidia,pins = "gmc";
165 nvidia,function = "uartd";
166 nvidia,pull = <0>;
167 nvidia,tristate = <1>;
168 };
169 ulpi {
170 nvidia,pins = "uaa", "uab", "uda";
171 nvidia,function = "ulpi";
172 nvidia,pull = <0>;
173 nvidia,tristate = <0>;
174 };
175 ulpi_refclk {
176 nvidia,pins = "cdev2";
177 nvidia,function = "pllp_out4";
178 nvidia,pull = <0>;
179 nvidia,tristate = <0>;
180 };
181 usb_gpio {
182 nvidia,pins = "spig", "spih";
183 nvidia,function = "spi2_alt";
184 nvidia,pull = <0>;
185 nvidia,tristate = <0>;
186 };
187 vi {
188 nvidia,pins = "dta", "dtb", "dtc", "dtd";
189 nvidia,function = "vi";
190 nvidia,pull = <0>;
191 nvidia,tristate = <1>;
192 };
193 vi_sc {
194 nvidia,pins = "csus";
195 nvidia,function = "vi_sensor_clk";
196 nvidia,pull = <0>;
197 nvidia,tristate = <1>;
198 };
199 };
200 };
201
Stephen Warren57899052013-11-26 14:43:45 -0700202 ac97: ac97@70002000 {
203 status = "okay";
204 nvidia,codec-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
205 GPIO_ACTIVE_HIGH>;
206 nvidia,codec-sync-gpio = <&gpio TEGRA_GPIO(P, 0)
207 GPIO_ACTIVE_HIGH>;
208 };
209
Lucas Stachfc9c7132013-01-22 22:46:08 +0100210 i2c@7000c000 {
211 clock-frequency = <400000>;
212 };
213
214 i2c_ddc: i2c@7000c400 {
215 clock-frequency = <100000>;
216 };
217
218 i2c@7000c500 {
219 clock-frequency = <400000>;
220 };
221
222 i2c@7000d000 {
223 status = "okay";
224 clock-frequency = <400000>;
225
226 pmic: tps6586x@34 {
227 compatible = "ti,tps6586x";
228 reg = <0x34>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700229 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
Lucas Stachfc9c7132013-01-22 22:46:08 +0100230
231 ti,system-power-controller;
232
233 #gpio-cells = <2>;
234 gpio-controller;
235
236 sys-supply = <&vdd_5v0_reg>;
237 vin-sm0-supply = <&sys_reg>;
238 vin-sm1-supply = <&sys_reg>;
239 vin-sm2-supply = <&sys_reg>;
240 vinldo01-supply = <&sm2_reg>;
241 vinldo23-supply = <&sm2_reg>;
242 vinldo4-supply = <&sm2_reg>;
243 vinldo678-supply = <&sm2_reg>;
244 vinldo9-supply = <&sm2_reg>;
245
246 regulators {
247 #address-cells = <1>;
248 #size-cells = <0>;
249
250 sys_reg: regulator@0 {
251 reg = <0>;
252 regulator-compatible = "sys";
253 regulator-name = "vdd_sys";
254 regulator-always-on;
255 };
256
257 regulator@1 {
258 reg = <1>;
259 regulator-compatible = "sm0";
260 regulator-name = "vdd_sm0,vdd_core";
261 regulator-min-microvolt = <1275000>;
262 regulator-max-microvolt = <1275000>;
263 regulator-always-on;
264 };
265
266 regulator@2 {
267 reg = <2>;
268 regulator-compatible = "sm1";
269 regulator-name = "vdd_sm1,vdd_cpu";
270 regulator-min-microvolt = <1100000>;
271 regulator-max-microvolt = <1100000>;
272 regulator-always-on;
273 };
274
275 sm2_reg: regulator@3 {
276 reg = <3>;
277 regulator-compatible = "sm2";
278 regulator-name = "vdd_sm2,vin_ldo*";
279 regulator-min-microvolt = <3700000>;
280 regulator-max-microvolt = <3700000>;
281 regulator-always-on;
282 };
283
284 /* LDO0 is not connected to anything */
285
286 regulator@5 {
287 reg = <5>;
288 regulator-compatible = "ldo1";
289 regulator-name = "vdd_ldo1,avdd_pll*";
290 regulator-min-microvolt = <1100000>;
291 regulator-max-microvolt = <1100000>;
292 regulator-always-on;
293 };
294
295 regulator@6 {
296 reg = <6>;
297 regulator-compatible = "ldo2";
298 regulator-name = "vdd_ldo2,vdd_rtc";
299 regulator-min-microvolt = <1200000>;
300 regulator-max-microvolt = <1200000>;
301 };
302
303 /* LDO3 is not connected to anything */
304
305 regulator@8 {
306 reg = <8>;
307 regulator-compatible = "ldo4";
308 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
309 regulator-min-microvolt = <1800000>;
310 regulator-max-microvolt = <1800000>;
311 regulator-always-on;
312 };
313
314 ldo5_reg: regulator@9 {
315 reg = <9>;
316 regulator-compatible = "ldo5";
317 regulator-name = "vdd_ldo5,vdd_fuse";
318 regulator-min-microvolt = <3300000>;
319 regulator-max-microvolt = <3300000>;
320 regulator-always-on;
321 };
322
323 regulator@10 {
324 reg = <10>;
325 regulator-compatible = "ldo6";
326 regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
327 regulator-min-microvolt = <1800000>;
328 regulator-max-microvolt = <1800000>;
329 };
330
331 hdmi_vdd_reg: regulator@11 {
332 reg = <11>;
333 regulator-compatible = "ldo7";
334 regulator-name = "vdd_ldo7,avdd_hdmi";
335 regulator-min-microvolt = <3300000>;
336 regulator-max-microvolt = <3300000>;
337 };
338
339 hdmi_pll_reg: regulator@12 {
340 reg = <12>;
341 regulator-compatible = "ldo8";
342 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
343 regulator-min-microvolt = <1800000>;
344 regulator-max-microvolt = <1800000>;
345 };
346
347 regulator@13 {
348 reg = <13>;
349 regulator-compatible = "ldo9";
350 regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
351 regulator-min-microvolt = <2850000>;
352 regulator-max-microvolt = <2850000>;
353 regulator-always-on;
354 };
355
356 regulator@14 {
357 reg = <14>;
358 regulator-compatible = "ldo_rtc";
359 regulator-name = "vdd_rtc_out,vdd_cell";
360 regulator-min-microvolt = <3300000>;
361 regulator-max-microvolt = <3300000>;
362 regulator-always-on;
363 };
364 };
365 };
366
367 temperature-sensor@4c {
368 compatible = "national,lm95245";
369 reg = <0x4c>;
370 };
371 };
372
Stephen Warren58ecb232013-11-25 17:53:16 -0700373 pmc@7000e400 {
Joseph Lo47d2d632013-08-12 17:40:07 +0800374 nvidia,suspend-mode = <1>;
Joseph Loa44a0192013-04-03 19:31:52 +0800375 nvidia,cpu-pwr-good-time = <5000>;
376 nvidia,cpu-pwr-off-time = <5000>;
377 nvidia,core-pwr-good-time = <3845 3845>;
378 nvidia,core-pwr-off-time = <3875>;
379 nvidia,sys-clock-req-active-high;
380 };
381
Lucas Stachfc9c7132013-01-22 22:46:08 +0100382 memory-controller@7000f400 {
383 emc-table@83250 {
384 reg = <83250>;
385 compatible = "nvidia,tegra20-emc-table";
386 clock-frequency = <83250>;
387 nvidia,emc-registers = <0x00000005 0x00000011
388 0x00000004 0x00000002 0x00000004 0x00000004
389 0x00000001 0x0000000a 0x00000002 0x00000002
390 0x00000001 0x00000001 0x00000003 0x00000004
391 0x00000003 0x00000009 0x0000000c 0x0000025f
392 0x00000000 0x00000003 0x00000003 0x00000002
393 0x00000002 0x00000001 0x00000008 0x000000c8
394 0x00000003 0x00000005 0x00000003 0x0000000c
395 0x00000002 0x00000000 0x00000000 0x00000002
396 0x00000000 0x00000000 0x00000083 0x00520006
397 0x00000010 0x00000008 0x00000000 0x00000000
398 0x00000000 0x00000000 0x00000000 0x00000000>;
399 };
400 emc-table@133200 {
401 reg = <133200>;
402 compatible = "nvidia,tegra20-emc-table";
403 clock-frequency = <133200>;
404 nvidia,emc-registers = <0x00000008 0x00000019
405 0x00000006 0x00000002 0x00000004 0x00000004
406 0x00000001 0x0000000a 0x00000002 0x00000002
407 0x00000002 0x00000001 0x00000003 0x00000004
408 0x00000003 0x00000009 0x0000000c 0x0000039f
409 0x00000000 0x00000003 0x00000003 0x00000002
410 0x00000002 0x00000001 0x00000008 0x000000c8
411 0x00000003 0x00000007 0x00000003 0x0000000c
412 0x00000002 0x00000000 0x00000000 0x00000002
413 0x00000000 0x00000000 0x00000083 0x00510006
414 0x00000010 0x00000008 0x00000000 0x00000000
415 0x00000000 0x00000000 0x00000000 0x00000000>;
416 };
417 emc-table@166500 {
418 reg = <166500>;
419 compatible = "nvidia,tegra20-emc-table";
420 clock-frequency = <166500>;
421 nvidia,emc-registers = <0x0000000a 0x00000021
422 0x00000008 0x00000003 0x00000004 0x00000004
423 0x00000002 0x0000000a 0x00000003 0x00000003
424 0x00000002 0x00000001 0x00000003 0x00000004
425 0x00000003 0x00000009 0x0000000c 0x000004df
426 0x00000000 0x00000003 0x00000003 0x00000003
427 0x00000003 0x00000001 0x00000009 0x000000c8
428 0x00000003 0x00000009 0x00000004 0x0000000c
429 0x00000002 0x00000000 0x00000000 0x00000002
430 0x00000000 0x00000000 0x00000083 0x004f0006
431 0x00000010 0x00000008 0x00000000 0x00000000
432 0x00000000 0x00000000 0x00000000 0x00000000>;
433 };
434 emc-table@333000 {
435 reg = <333000>;
436 compatible = "nvidia,tegra20-emc-table";
437 clock-frequency = <333000>;
438 nvidia,emc-registers = <0x00000014 0x00000041
439 0x0000000f 0x00000005 0x00000004 0x00000005
440 0x00000003 0x0000000a 0x00000005 0x00000005
441 0x00000004 0x00000001 0x00000003 0x00000004
442 0x00000003 0x00000009 0x0000000c 0x000009ff
443 0x00000000 0x00000003 0x00000003 0x00000005
444 0x00000005 0x00000001 0x0000000e 0x000000c8
445 0x00000003 0x00000011 0x00000006 0x0000000c
446 0x00000002 0x00000000 0x00000000 0x00000002
447 0x00000000 0x00000000 0x00000083 0x00380006
448 0x00000010 0x00000008 0x00000000 0x00000000
449 0x00000000 0x00000000 0x00000000 0x00000000>;
450 };
451 };
452
Lucas Stachfc9c7132013-01-22 22:46:08 +0100453 usb@c5004000 {
454 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700455 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
456 GPIO_ACTIVE_LOW>;
Venu Byravarasu9dffe3b2013-05-16 19:42:56 +0530457 };
458
459 usb-phy@c5004000 {
Lucas Stacha1632ad2013-07-23 11:11:45 -0700460 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700461 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
462 GPIO_ACTIVE_LOW>;
Lucas Stachfc9c7132013-01-22 22:46:08 +0100463 };
464
465 sdhci@c8000600 {
Stephen Warren3325f1b2013-02-12 17:25:15 -0700466 cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
Lucas Stachfc9c7132013-01-22 22:46:08 +0100467 };
468
Joseph Lo7021d122013-04-03 19:31:27 +0800469 clocks {
470 compatible = "simple-bus";
471 #address-cells = <1>;
472 #size-cells = <0>;
473
Stephen Warren58ecb232013-11-25 17:53:16 -0700474 clk32k_in: clock@0 {
Joseph Lo7021d122013-04-03 19:31:27 +0800475 compatible = "fixed-clock";
476 reg=<0>;
477 #clock-cells = <0>;
478 clock-frequency = <32768>;
479 };
480 };
481
Lucas Stachfc9c7132013-01-22 22:46:08 +0100482 regulators {
483 compatible = "simple-bus";
484 #address-cells = <1>;
485 #size-cells = <0>;
486
487 vdd_5v0_reg: regulator@100 {
488 compatible = "regulator-fixed";
489 reg = <100>;
490 regulator-name = "vdd_5v0";
491 regulator-min-microvolt = <5000000>;
492 regulator-max-microvolt = <5000000>;
493 regulator-always-on;
494 };
495
496 regulator@101 {
497 compatible = "regulator-fixed";
498 reg = <101>;
499 regulator-name = "internal_usb";
500 regulator-min-microvolt = <5000000>;
501 regulator-max-microvolt = <5000000>;
502 enable-active-high;
503 regulator-boot-on;
504 regulator-always-on;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700505 gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
Lucas Stachfc9c7132013-01-22 22:46:08 +0100506 };
507 };
Stephen Warren57899052013-11-26 14:43:45 -0700508
509 sound {
510 compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
511 "nvidia,tegra-audio-wm9712";
512 nvidia,model = "Colibri T20 AC97 Audio";
513
514 nvidia,audio-routing =
515 "Headphone", "HPOUTL",
516 "Headphone", "HPOUTR",
517 "LineIn", "LINEINL",
518 "LineIn", "LINEINR",
519 "Mic", "MIC1";
520
521 nvidia,ac97-controller = <&ac97>;
522
523 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
524 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
525 <&tegra_car TEGRA20_CLK_CDEV1>;
526 clock-names = "pll_a", "pll_a_out0", "mclk";
527 };
Lucas Stachfc9c7132013-01-22 22:46:08 +0100528};