blob: 80172fc8bdd58460b2a1ebdcdb9a958fb21c8189 [file] [log] [blame]
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.c
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/types.h>
40#include <linux/netdevice.h>
41#include <linux/etherdevice.h>
42#include <linux/ethtool.h>
43#include <linux/slab.h>
44#include <linux/device.h>
45#include <linux/skbuff.h>
46#include <linux/if_vlan.h>
47#include <linux/if_bridge.h>
48#include <linux/workqueue.h>
49#include <linux/jiffies.h>
50#include <linux/bitops.h>
Ido Schimmel7f71eb42015-12-15 16:03:37 +010051#include <linux/list.h>
Ido Schimmel80bedf12016-06-20 23:03:59 +020052#include <linux/notifier.h>
Ido Schimmel90183b92016-04-06 17:10:08 +020053#include <linux/dcbnl.h>
Ido Schimmel99724c12016-07-04 08:23:14 +020054#include <linux/inetdevice.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020055#include <net/switchdev.h>
56#include <generated/utsrelease.h>
57
58#include "spectrum.h"
59#include "core.h"
60#include "reg.h"
61#include "port.h"
62#include "trap.h"
63#include "txheader.h"
64
65static const char mlxsw_sp_driver_name[] = "mlxsw_spectrum";
66static const char mlxsw_sp_driver_version[] = "1.0";
67
68/* tx_hdr_version
69 * Tx header version.
70 * Must be set to 1.
71 */
72MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
73
74/* tx_hdr_ctl
75 * Packet control type.
76 * 0 - Ethernet control (e.g. EMADs, LACP)
77 * 1 - Ethernet data
78 */
79MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
80
81/* tx_hdr_proto
82 * Packet protocol type. Must be set to 1 (Ethernet).
83 */
84MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
85
86/* tx_hdr_rx_is_router
87 * Packet is sent from the router. Valid for data packets only.
88 */
89MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
90
91/* tx_hdr_fid_valid
92 * Indicates if the 'fid' field is valid and should be used for
93 * forwarding lookup. Valid for data packets only.
94 */
95MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
96
97/* tx_hdr_swid
98 * Switch partition ID. Must be set to 0.
99 */
100MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
101
102/* tx_hdr_control_tclass
103 * Indicates if the packet should use the control TClass and not one
104 * of the data TClasses.
105 */
106MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
107
108/* tx_hdr_etclass
109 * Egress TClass to be used on the egress device on the egress port.
110 */
111MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
112
113/* tx_hdr_port_mid
114 * Destination local port for unicast packets.
115 * Destination multicast ID for multicast packets.
116 *
117 * Control packets are directed to a specific egress port, while data
118 * packets are transmitted through the CPU port (0) into the switch partition,
119 * where forwarding rules are applied.
120 */
121MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
122
123/* tx_hdr_fid
124 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
125 * set, otherwise calculated based on the packet's VID using VID to FID mapping.
126 * Valid for data packets only.
127 */
128MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
129
130/* tx_hdr_type
131 * 0 - Data packets
132 * 6 - Control packets
133 */
134MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
135
136static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
137 const struct mlxsw_tx_info *tx_info)
138{
139 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
140
141 memset(txhdr, 0, MLXSW_TXHDR_LEN);
142
143 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
144 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
145 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
146 mlxsw_tx_hdr_swid_set(txhdr, 0);
147 mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
148 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
149 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
150}
151
152static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
153{
154 char spad_pl[MLXSW_REG_SPAD_LEN];
155 int err;
156
157 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
158 if (err)
159 return err;
160 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
161 return 0;
162}
163
164static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
165 bool is_up)
166{
167 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
168 char paos_pl[MLXSW_REG_PAOS_LEN];
169
170 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
171 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
172 MLXSW_PORT_ADMIN_STATUS_DOWN);
173 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
174}
175
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200176static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
177 unsigned char *addr)
178{
179 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
180 char ppad_pl[MLXSW_REG_PPAD_LEN];
181
182 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
183 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
184 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
185}
186
187static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
188{
189 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
190 unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
191
192 ether_addr_copy(addr, mlxsw_sp->base_mac);
193 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
194 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
195}
196
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200197static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
198{
199 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
200 char pmtu_pl[MLXSW_REG_PMTU_LEN];
201 int max_mtu;
202 int err;
203
204 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
205 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
206 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
207 if (err)
208 return err;
209 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
210
211 if (mtu > max_mtu)
212 return -EINVAL;
213
214 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
215 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
216}
217
Ido Schimmelbe945352016-06-09 09:51:39 +0200218static int __mlxsw_sp_port_swid_set(struct mlxsw_sp *mlxsw_sp, u8 local_port,
219 u8 swid)
220{
221 char pspa_pl[MLXSW_REG_PSPA_LEN];
222
223 mlxsw_reg_pspa_pack(pspa_pl, swid, local_port);
224 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
225}
226
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200227static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
228{
229 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200230
Ido Schimmelbe945352016-06-09 09:51:39 +0200231 return __mlxsw_sp_port_swid_set(mlxsw_sp, mlxsw_sp_port->local_port,
232 swid);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200233}
234
235static int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port,
236 bool enable)
237{
238 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
239 char svpe_pl[MLXSW_REG_SVPE_LEN];
240
241 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
242 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
243}
244
245int mlxsw_sp_port_vid_to_fid_set(struct mlxsw_sp_port *mlxsw_sp_port,
246 enum mlxsw_reg_svfa_mt mt, bool valid, u16 fid,
247 u16 vid)
248{
249 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
250 char svfa_pl[MLXSW_REG_SVFA_LEN];
251
252 mlxsw_reg_svfa_pack(svfa_pl, mlxsw_sp_port->local_port, mt, valid,
253 fid, vid);
254 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svfa), svfa_pl);
255}
256
257static int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port,
258 u16 vid, bool learn_enable)
259{
260 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
261 char *spvmlr_pl;
262 int err;
263
264 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
265 if (!spvmlr_pl)
266 return -ENOMEM;
267 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
268 learn_enable);
269 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
270 kfree(spvmlr_pl);
271 return err;
272}
273
274static int
275mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
276{
277 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
278 char sspr_pl[MLXSW_REG_SSPR_LEN];
279
280 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
281 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
282}
283
Ido Schimmeld664b412016-06-09 09:51:40 +0200284static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
285 u8 local_port, u8 *p_module,
286 u8 *p_width, u8 *p_lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200287{
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200288 char pmlp_pl[MLXSW_REG_PMLP_LEN];
289 int err;
290
Ido Schimmel558c2d52016-02-26 17:32:29 +0100291 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200292 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
293 if (err)
294 return err;
Ido Schimmel558c2d52016-02-26 17:32:29 +0100295 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
296 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200297 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200298 return 0;
299}
300
Ido Schimmel18f1e702016-02-26 17:32:31 +0100301static int mlxsw_sp_port_module_map(struct mlxsw_sp *mlxsw_sp, u8 local_port,
302 u8 module, u8 width, u8 lane)
303{
304 char pmlp_pl[MLXSW_REG_PMLP_LEN];
305 int i;
306
307 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
308 mlxsw_reg_pmlp_width_set(pmlp_pl, width);
309 for (i = 0; i < width; i++) {
310 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
311 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */
312 }
313
314 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
315}
316
Ido Schimmel3e9b27b2016-02-26 17:32:28 +0100317static int mlxsw_sp_port_module_unmap(struct mlxsw_sp *mlxsw_sp, u8 local_port)
318{
319 char pmlp_pl[MLXSW_REG_PMLP_LEN];
320
321 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
322 mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
323 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
324}
325
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200326static int mlxsw_sp_port_open(struct net_device *dev)
327{
328 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
329 int err;
330
331 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
332 if (err)
333 return err;
334 netif_start_queue(dev);
335 return 0;
336}
337
338static int mlxsw_sp_port_stop(struct net_device *dev)
339{
340 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
341
342 netif_stop_queue(dev);
343 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
344}
345
346static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
347 struct net_device *dev)
348{
349 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
350 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
351 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
352 const struct mlxsw_tx_info tx_info = {
353 .local_port = mlxsw_sp_port->local_port,
354 .is_emad = false,
355 };
356 u64 len;
357 int err;
358
Jiri Pirko307c2432016-04-08 19:11:22 +0200359 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200360 return NETDEV_TX_BUSY;
361
362 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
363 struct sk_buff *skb_orig = skb;
364
365 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
366 if (!skb) {
367 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
368 dev_kfree_skb_any(skb_orig);
369 return NETDEV_TX_OK;
370 }
371 }
372
373 if (eth_skb_pad(skb)) {
374 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
375 return NETDEV_TX_OK;
376 }
377
378 mlxsw_sp_txhdr_construct(skb, &tx_info);
Nogah Frankel63dcdd32016-06-17 15:09:05 +0200379 /* TX header is consumed by HW on the way so we shouldn't count its
380 * bytes as being sent.
381 */
382 len = skb->len - MLXSW_TXHDR_LEN;
383
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200384 /* Due to a race we might fail here because of a full queue. In that
385 * unlikely case we simply drop the packet.
386 */
Jiri Pirko307c2432016-04-08 19:11:22 +0200387 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200388
389 if (!err) {
390 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
391 u64_stats_update_begin(&pcpu_stats->syncp);
392 pcpu_stats->tx_packets++;
393 pcpu_stats->tx_bytes += len;
394 u64_stats_update_end(&pcpu_stats->syncp);
395 } else {
396 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
397 dev_kfree_skb_any(skb);
398 }
399 return NETDEV_TX_OK;
400}
401
Jiri Pirkoc5b9b512015-12-03 12:12:22 +0100402static void mlxsw_sp_set_rx_mode(struct net_device *dev)
403{
404}
405
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200406static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
407{
408 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
409 struct sockaddr *addr = p;
410 int err;
411
412 if (!is_valid_ether_addr(addr->sa_data))
413 return -EADDRNOTAVAIL;
414
415 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
416 if (err)
417 return err;
418 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
419 return 0;
420}
421
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200422static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int pg_index, int mtu,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200423 bool pause_en, bool pfc_en, u16 delay)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200424{
425 u16 pg_size = 2 * MLXSW_SP_BYTES_TO_CELLS(mtu);
426
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200427 delay = pfc_en ? mlxsw_sp_pfc_delay_get(mtu, delay) :
428 MLXSW_SP_PAUSE_DELAY;
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200429
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200430 if (pause_en || pfc_en)
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200431 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, pg_index,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200432 pg_size + delay, pg_size);
433 else
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200434 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, pg_index, pg_size);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200435}
436
437int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200438 u8 *prio_tc, bool pause_en,
439 struct ieee_pfc *my_pfc)
Ido Schimmelff6551e2016-04-06 17:10:03 +0200440{
441 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200442 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
443 u16 delay = !!my_pfc ? my_pfc->delay : 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200444 char pbmc_pl[MLXSW_REG_PBMC_LEN];
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200445 int i, j, err;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200446
447 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
448 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
449 if (err)
450 return err;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200451
452 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
453 bool configure = false;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200454 bool pfc = false;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200455
456 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
457 if (prio_tc[j] == i) {
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200458 pfc = pfc_en & BIT(j);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200459 configure = true;
460 break;
461 }
462 }
463
464 if (!configure)
465 continue;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200466 mlxsw_sp_pg_buf_pack(pbmc_pl, i, mtu, pause_en, pfc, delay);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200467 }
468
Ido Schimmelff6551e2016-04-06 17:10:03 +0200469 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
470}
471
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200472static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200473 int mtu, bool pause_en)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200474{
475 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
476 bool dcb_en = !!mlxsw_sp_port->dcb.ets;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200477 struct ieee_pfc *my_pfc;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200478 u8 *prio_tc;
479
480 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200481 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200482
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200483 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200484 pause_en, my_pfc);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200485}
486
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200487static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
488{
489 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200490 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200491 int err;
492
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200493 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200494 if (err)
495 return err;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200496 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
497 if (err)
498 goto err_port_mtu_set;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200499 dev->mtu = mtu;
500 return 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200501
502err_port_mtu_set:
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200503 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
Ido Schimmelff6551e2016-04-06 17:10:03 +0200504 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200505}
506
507static struct rtnl_link_stats64 *
508mlxsw_sp_port_get_stats64(struct net_device *dev,
509 struct rtnl_link_stats64 *stats)
510{
511 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
512 struct mlxsw_sp_port_pcpu_stats *p;
513 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
514 u32 tx_dropped = 0;
515 unsigned int start;
516 int i;
517
518 for_each_possible_cpu(i) {
519 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
520 do {
521 start = u64_stats_fetch_begin_irq(&p->syncp);
522 rx_packets = p->rx_packets;
523 rx_bytes = p->rx_bytes;
524 tx_packets = p->tx_packets;
525 tx_bytes = p->tx_bytes;
526 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
527
528 stats->rx_packets += rx_packets;
529 stats->rx_bytes += rx_bytes;
530 stats->tx_packets += tx_packets;
531 stats->tx_bytes += tx_bytes;
532 /* tx_dropped is u32, updated without syncp protection. */
533 tx_dropped += p->tx_dropped;
534 }
535 stats->tx_dropped = tx_dropped;
536 return stats;
537}
538
539int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
540 u16 vid_end, bool is_member, bool untagged)
541{
542 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
543 char *spvm_pl;
544 int err;
545
546 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
547 if (!spvm_pl)
548 return -ENOMEM;
549
550 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
551 vid_end, is_member, untagged);
552 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
553 kfree(spvm_pl);
554 return err;
555}
556
557static int mlxsw_sp_port_vp_mode_trans(struct mlxsw_sp_port *mlxsw_sp_port)
558{
559 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
560 u16 vid, last_visited_vid;
561 int err;
562
563 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID) {
564 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, true, vid,
565 vid);
566 if (err) {
567 last_visited_vid = vid;
568 goto err_port_vid_to_fid_set;
569 }
570 }
571
572 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
573 if (err) {
574 last_visited_vid = VLAN_N_VID;
575 goto err_port_vid_to_fid_set;
576 }
577
578 return 0;
579
580err_port_vid_to_fid_set:
581 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, last_visited_vid)
582 mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, false, vid,
583 vid);
584 return err;
585}
586
587static int mlxsw_sp_port_vlan_mode_trans(struct mlxsw_sp_port *mlxsw_sp_port)
588{
589 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
590 u16 vid;
591 int err;
592
593 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
594 if (err)
595 return err;
596
597 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID) {
598 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, false,
599 vid, vid);
600 if (err)
601 return err;
602 }
603
604 return 0;
605}
606
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100607static struct mlxsw_sp_port *
Ido Schimmel0355b592016-06-20 23:04:13 +0200608mlxsw_sp_port_vport_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100609{
610 struct mlxsw_sp_port *mlxsw_sp_vport;
611
612 mlxsw_sp_vport = kzalloc(sizeof(*mlxsw_sp_vport), GFP_KERNEL);
613 if (!mlxsw_sp_vport)
614 return NULL;
615
616 /* dev will be set correctly after the VLAN device is linked
617 * with the real device. In case of bridge SELF invocation, dev
618 * will remain as is.
619 */
620 mlxsw_sp_vport->dev = mlxsw_sp_port->dev;
621 mlxsw_sp_vport->mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
622 mlxsw_sp_vport->local_port = mlxsw_sp_port->local_port;
623 mlxsw_sp_vport->stp_state = BR_STATE_FORWARDING;
Ido Schimmel272c4472015-12-15 16:03:47 +0100624 mlxsw_sp_vport->lagged = mlxsw_sp_port->lagged;
625 mlxsw_sp_vport->lag_id = mlxsw_sp_port->lag_id;
Ido Schimmel0355b592016-06-20 23:04:13 +0200626 mlxsw_sp_vport->vport.vid = vid;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100627
628 list_add(&mlxsw_sp_vport->vport.list, &mlxsw_sp_port->vports_list);
629
630 return mlxsw_sp_vport;
631}
632
633static void mlxsw_sp_port_vport_destroy(struct mlxsw_sp_port *mlxsw_sp_vport)
634{
635 list_del(&mlxsw_sp_vport->vport.list);
636 kfree(mlxsw_sp_vport);
637}
638
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200639int mlxsw_sp_port_add_vid(struct net_device *dev, __be16 __always_unused proto,
640 u16 vid)
641{
642 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100643 struct mlxsw_sp_port *mlxsw_sp_vport;
Ido Schimmel52697a92016-07-02 11:00:09 +0200644 bool untagged = vid == 1;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200645 int err;
646
647 /* VLAN 0 is added to HW filter when device goes up, but it is
648 * reserved in our case, so simply return.
649 */
650 if (!vid)
651 return 0;
652
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100653 if (mlxsw_sp_port_vport_find(mlxsw_sp_port, vid)) {
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200654 netdev_warn(dev, "VID=%d already configured\n", vid);
655 return 0;
656 }
657
Ido Schimmel0355b592016-06-20 23:04:13 +0200658 mlxsw_sp_vport = mlxsw_sp_port_vport_create(mlxsw_sp_port, vid);
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100659 if (!mlxsw_sp_vport) {
660 netdev_err(dev, "Failed to create vPort for VID=%d\n", vid);
Ido Schimmel0355b592016-06-20 23:04:13 +0200661 return -ENOMEM;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100662 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200663
664 /* When adding the first VLAN interface on a bridged port we need to
665 * transition all the active 802.1Q bridge VLANs to use explicit
666 * {Port, VID} to FID mappings and set the port's mode to Virtual mode.
667 */
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100668 if (list_is_singular(&mlxsw_sp_port->vports_list)) {
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200669 err = mlxsw_sp_port_vp_mode_trans(mlxsw_sp_port);
670 if (err) {
671 netdev_err(dev, "Failed to set to Virtual mode\n");
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100672 goto err_port_vp_mode_trans;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200673 }
674 }
675
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100676 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, false);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200677 if (err) {
678 netdev_err(dev, "Failed to disable learning for VID=%d\n", vid);
679 goto err_port_vid_learning_set;
680 }
681
Ido Schimmel52697a92016-07-02 11:00:09 +0200682 err = mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, true, untagged);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200683 if (err) {
684 netdev_err(dev, "Failed to set VLAN membership for VID=%d\n",
685 vid);
686 goto err_port_add_vid;
687 }
688
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200689 return 0;
690
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200691err_port_add_vid:
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100692 mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, true);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200693err_port_vid_learning_set:
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100694 if (list_is_singular(&mlxsw_sp_port->vports_list))
695 mlxsw_sp_port_vlan_mode_trans(mlxsw_sp_port);
696err_port_vp_mode_trans:
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100697 mlxsw_sp_port_vport_destroy(mlxsw_sp_vport);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200698 return err;
699}
700
Ido Schimmel32d863f2016-07-02 11:00:10 +0200701static int mlxsw_sp_port_kill_vid(struct net_device *dev,
702 __be16 __always_unused proto, u16 vid)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200703{
704 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100705 struct mlxsw_sp_port *mlxsw_sp_vport;
Ido Schimmel1c800752016-06-20 23:04:20 +0200706 struct mlxsw_sp_fid *f;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200707 int err;
708
709 /* VLAN 0 is removed from HW filter when device goes down, but
710 * it is reserved in our case, so simply return.
711 */
712 if (!vid)
713 return 0;
714
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100715 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
716 if (!mlxsw_sp_vport) {
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200717 netdev_warn(dev, "VID=%d does not exist\n", vid);
718 return 0;
719 }
720
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100721 err = mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, false, false);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200722 if (err) {
723 netdev_err(dev, "Failed to set VLAN membership for VID=%d\n",
724 vid);
725 return err;
726 }
727
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100728 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, true);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200729 if (err) {
730 netdev_err(dev, "Failed to enable learning for VID=%d\n", vid);
731 return err;
732 }
733
Ido Schimmel1c800752016-06-20 23:04:20 +0200734 /* Drop FID reference. If this was the last reference the
735 * resources will be freed.
736 */
737 f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
738 if (f && !WARN_ON(!f->leave))
739 f->leave(mlxsw_sp_vport);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200740
741 /* When removing the last VLAN interface on a bridged port we need to
742 * transition all active 802.1Q bridge VLANs to use VID to FID
743 * mappings and set port's mode to VLAN mode.
744 */
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100745 if (list_is_singular(&mlxsw_sp_port->vports_list)) {
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200746 err = mlxsw_sp_port_vlan_mode_trans(mlxsw_sp_port);
747 if (err) {
748 netdev_err(dev, "Failed to set to VLAN mode\n");
749 return err;
750 }
751 }
752
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100753 mlxsw_sp_port_vport_destroy(mlxsw_sp_vport);
754
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200755 return 0;
756}
757
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200758static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
759 size_t len)
760{
761 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmeld664b412016-06-09 09:51:40 +0200762 u8 module = mlxsw_sp_port->mapping.module;
763 u8 width = mlxsw_sp_port->mapping.width;
764 u8 lane = mlxsw_sp_port->mapping.lane;
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200765 int err;
766
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200767 if (!mlxsw_sp_port->split)
768 err = snprintf(name, len, "p%d", module + 1);
769 else
770 err = snprintf(name, len, "p%ds%d", module + 1,
771 lane / width);
772
773 if (err >= len)
774 return -EINVAL;
775
776 return 0;
777}
778
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200779static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
780 .ndo_open = mlxsw_sp_port_open,
781 .ndo_stop = mlxsw_sp_port_stop,
782 .ndo_start_xmit = mlxsw_sp_port_xmit,
Jiri Pirkoc5b9b512015-12-03 12:12:22 +0100783 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200784 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
785 .ndo_change_mtu = mlxsw_sp_port_change_mtu,
786 .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
787 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
788 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
Jiri Pirko6cf3c972016-07-05 11:27:39 +0200789 .ndo_neigh_construct = mlxsw_sp_router_neigh_construct,
790 .ndo_neigh_destroy = mlxsw_sp_router_neigh_destroy,
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200791 .ndo_fdb_add = switchdev_port_fdb_add,
792 .ndo_fdb_del = switchdev_port_fdb_del,
793 .ndo_fdb_dump = switchdev_port_fdb_dump,
794 .ndo_bridge_setlink = switchdev_port_bridge_setlink,
795 .ndo_bridge_getlink = switchdev_port_bridge_getlink,
796 .ndo_bridge_dellink = switchdev_port_bridge_dellink,
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200797 .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200798};
799
800static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
801 struct ethtool_drvinfo *drvinfo)
802{
803 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
804 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
805
806 strlcpy(drvinfo->driver, mlxsw_sp_driver_name, sizeof(drvinfo->driver));
807 strlcpy(drvinfo->version, mlxsw_sp_driver_version,
808 sizeof(drvinfo->version));
809 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
810 "%d.%d.%d",
811 mlxsw_sp->bus_info->fw_rev.major,
812 mlxsw_sp->bus_info->fw_rev.minor,
813 mlxsw_sp->bus_info->fw_rev.subminor);
814 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
815 sizeof(drvinfo->bus_info));
816}
817
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200818static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
819 struct ethtool_pauseparam *pause)
820{
821 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
822
823 pause->rx_pause = mlxsw_sp_port->link.rx_pause;
824 pause->tx_pause = mlxsw_sp_port->link.tx_pause;
825}
826
827static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
828 struct ethtool_pauseparam *pause)
829{
830 char pfcc_pl[MLXSW_REG_PFCC_LEN];
831
832 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
833 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
834 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
835
836 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
837 pfcc_pl);
838}
839
840static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
841 struct ethtool_pauseparam *pause)
842{
843 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
844 bool pause_en = pause->tx_pause || pause->rx_pause;
845 int err;
846
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200847 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
848 netdev_err(dev, "PFC already enabled on port\n");
849 return -EINVAL;
850 }
851
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200852 if (pause->autoneg) {
853 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
854 return -EINVAL;
855 }
856
857 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
858 if (err) {
859 netdev_err(dev, "Failed to configure port's headroom\n");
860 return err;
861 }
862
863 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
864 if (err) {
865 netdev_err(dev, "Failed to set PAUSE parameters\n");
866 goto err_port_pause_configure;
867 }
868
869 mlxsw_sp_port->link.rx_pause = pause->rx_pause;
870 mlxsw_sp_port->link.tx_pause = pause->tx_pause;
871
872 return 0;
873
874err_port_pause_configure:
875 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
876 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
877 return err;
878}
879
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200880struct mlxsw_sp_port_hw_stats {
881 char str[ETH_GSTRING_LEN];
882 u64 (*getter)(char *payload);
883};
884
Ido Schimmel7ed674b2016-07-19 15:35:53 +0200885static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200886 {
887 .str = "a_frames_transmitted_ok",
888 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
889 },
890 {
891 .str = "a_frames_received_ok",
892 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
893 },
894 {
895 .str = "a_frame_check_sequence_errors",
896 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
897 },
898 {
899 .str = "a_alignment_errors",
900 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
901 },
902 {
903 .str = "a_octets_transmitted_ok",
904 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
905 },
906 {
907 .str = "a_octets_received_ok",
908 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
909 },
910 {
911 .str = "a_multicast_frames_xmitted_ok",
912 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
913 },
914 {
915 .str = "a_broadcast_frames_xmitted_ok",
916 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
917 },
918 {
919 .str = "a_multicast_frames_received_ok",
920 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
921 },
922 {
923 .str = "a_broadcast_frames_received_ok",
924 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
925 },
926 {
927 .str = "a_in_range_length_errors",
928 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
929 },
930 {
931 .str = "a_out_of_range_length_field",
932 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
933 },
934 {
935 .str = "a_frame_too_long_errors",
936 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
937 },
938 {
939 .str = "a_symbol_error_during_carrier",
940 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
941 },
942 {
943 .str = "a_mac_control_frames_transmitted",
944 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
945 },
946 {
947 .str = "a_mac_control_frames_received",
948 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
949 },
950 {
951 .str = "a_unsupported_opcodes_received",
952 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
953 },
954 {
955 .str = "a_pause_mac_ctrl_frames_received",
956 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
957 },
958 {
959 .str = "a_pause_mac_ctrl_frames_xmitted",
960 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
961 },
962};
963
964#define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
965
Ido Schimmel7ed674b2016-07-19 15:35:53 +0200966static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = {
967 {
968 .str = "rx_octets_prio",
969 .getter = mlxsw_reg_ppcnt_rx_octets_get,
970 },
971 {
972 .str = "rx_frames_prio",
973 .getter = mlxsw_reg_ppcnt_rx_frames_get,
974 },
975 {
976 .str = "tx_octets_prio",
977 .getter = mlxsw_reg_ppcnt_tx_octets_get,
978 },
979 {
980 .str = "tx_frames_prio",
981 .getter = mlxsw_reg_ppcnt_tx_frames_get,
982 },
983 {
984 .str = "rx_pause_prio",
985 .getter = mlxsw_reg_ppcnt_rx_pause_get,
986 },
987 {
988 .str = "rx_pause_duration_prio",
989 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get,
990 },
991 {
992 .str = "tx_pause_prio",
993 .getter = mlxsw_reg_ppcnt_tx_pause_get,
994 },
995 {
996 .str = "tx_pause_duration_prio",
997 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get,
998 },
999};
1000
1001#define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats)
1002
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001003static u64 mlxsw_reg_ppcnt_tc_transmit_queue_bytes_get(char *ppcnt_pl)
1004{
1005 u64 transmit_queue = mlxsw_reg_ppcnt_tc_transmit_queue_get(ppcnt_pl);
1006
1007 return MLXSW_SP_CELLS_TO_BYTES(transmit_queue);
1008}
1009
1010static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = {
1011 {
1012 .str = "tc_transmit_queue_tc",
1013 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_bytes_get,
1014 },
1015 {
1016 .str = "tc_no_buffer_discard_uc_tc",
1017 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get,
1018 },
1019};
1020
1021#define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats)
1022
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001023#define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001024 (MLXSW_SP_PORT_HW_PRIO_STATS_LEN + \
1025 MLXSW_SP_PORT_HW_TC_STATS_LEN) * \
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001026 IEEE_8021QAZ_MAX_TCS)
1027
1028static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio)
1029{
1030 int i;
1031
1032 for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) {
1033 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
1034 mlxsw_sp_port_hw_prio_stats[i].str, prio);
1035 *p += ETH_GSTRING_LEN;
1036 }
1037}
1038
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001039static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc)
1040{
1041 int i;
1042
1043 for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) {
1044 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
1045 mlxsw_sp_port_hw_tc_stats[i].str, tc);
1046 *p += ETH_GSTRING_LEN;
1047 }
1048}
1049
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001050static void mlxsw_sp_port_get_strings(struct net_device *dev,
1051 u32 stringset, u8 *data)
1052{
1053 u8 *p = data;
1054 int i;
1055
1056 switch (stringset) {
1057 case ETH_SS_STATS:
1058 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
1059 memcpy(p, mlxsw_sp_port_hw_stats[i].str,
1060 ETH_GSTRING_LEN);
1061 p += ETH_GSTRING_LEN;
1062 }
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001063
1064 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
1065 mlxsw_sp_port_get_prio_strings(&p, i);
1066
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001067 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
1068 mlxsw_sp_port_get_tc_strings(&p, i);
1069
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001070 break;
1071 }
1072}
1073
Ido Schimmel3a66ee32015-11-27 13:45:55 +01001074static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
1075 enum ethtool_phys_id_state state)
1076{
1077 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1078 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1079 char mlcr_pl[MLXSW_REG_MLCR_LEN];
1080 bool active;
1081
1082 switch (state) {
1083 case ETHTOOL_ID_ACTIVE:
1084 active = true;
1085 break;
1086 case ETHTOOL_ID_INACTIVE:
1087 active = false;
1088 break;
1089 default:
1090 return -EOPNOTSUPP;
1091 }
1092
1093 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
1094 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
1095}
1096
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001097static int
1098mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats,
1099 int *p_len, enum mlxsw_reg_ppcnt_grp grp)
1100{
1101 switch (grp) {
1102 case MLXSW_REG_PPCNT_IEEE_8023_CNT:
1103 *p_hw_stats = mlxsw_sp_port_hw_stats;
1104 *p_len = MLXSW_SP_PORT_HW_STATS_LEN;
1105 break;
1106 case MLXSW_REG_PPCNT_PRIO_CNT:
1107 *p_hw_stats = mlxsw_sp_port_hw_prio_stats;
1108 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
1109 break;
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001110 case MLXSW_REG_PPCNT_TC_CNT:
1111 *p_hw_stats = mlxsw_sp_port_hw_tc_stats;
1112 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN;
1113 break;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001114 default:
1115 WARN_ON(1);
1116 return -ENOTSUPP;
1117 }
1118 return 0;
1119}
1120
1121static void __mlxsw_sp_port_get_stats(struct net_device *dev,
1122 enum mlxsw_reg_ppcnt_grp grp, int prio,
1123 u64 *data, int data_index)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001124{
1125 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1126 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001127 struct mlxsw_sp_port_hw_stats *hw_stats;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001128 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001129 int i, len;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001130 int err;
1131
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001132 err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp);
1133 if (err)
1134 return;
1135 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001136 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001137 for (i = 0; i < len; i++)
1138 data[data_index + i] = !err ? hw_stats[i].getter(ppcnt_pl) : 0;
1139}
1140
1141static void mlxsw_sp_port_get_stats(struct net_device *dev,
1142 struct ethtool_stats *stats, u64 *data)
1143{
1144 int i, data_index = 0;
1145
1146 /* IEEE 802.3 Counters */
1147 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0,
1148 data, data_index);
1149 data_index = MLXSW_SP_PORT_HW_STATS_LEN;
1150
1151 /* Per-Priority Counters */
1152 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1153 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i,
1154 data, data_index);
1155 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
1156 }
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001157
1158 /* Per-TC Counters */
1159 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1160 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i,
1161 data, data_index);
1162 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN;
1163 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001164}
1165
1166static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
1167{
1168 switch (sset) {
1169 case ETH_SS_STATS:
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001170 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001171 default:
1172 return -EOPNOTSUPP;
1173 }
1174}
1175
1176struct mlxsw_sp_port_link_mode {
1177 u32 mask;
1178 u32 supported;
1179 u32 advertised;
1180 u32 speed;
1181};
1182
1183static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
1184 {
1185 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
1186 .supported = SUPPORTED_100baseT_Full,
1187 .advertised = ADVERTISED_100baseT_Full,
1188 .speed = 100,
1189 },
1190 {
1191 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX,
1192 .speed = 100,
1193 },
1194 {
1195 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
1196 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
1197 .supported = SUPPORTED_1000baseKX_Full,
1198 .advertised = ADVERTISED_1000baseKX_Full,
1199 .speed = 1000,
1200 },
1201 {
1202 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
1203 .supported = SUPPORTED_10000baseT_Full,
1204 .advertised = ADVERTISED_10000baseT_Full,
1205 .speed = 10000,
1206 },
1207 {
1208 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
1209 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
1210 .supported = SUPPORTED_10000baseKX4_Full,
1211 .advertised = ADVERTISED_10000baseKX4_Full,
1212 .speed = 10000,
1213 },
1214 {
1215 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1216 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1217 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1218 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
1219 .supported = SUPPORTED_10000baseKR_Full,
1220 .advertised = ADVERTISED_10000baseKR_Full,
1221 .speed = 10000,
1222 },
1223 {
1224 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
1225 .supported = SUPPORTED_20000baseKR2_Full,
1226 .advertised = ADVERTISED_20000baseKR2_Full,
1227 .speed = 20000,
1228 },
1229 {
1230 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
1231 .supported = SUPPORTED_40000baseCR4_Full,
1232 .advertised = ADVERTISED_40000baseCR4_Full,
1233 .speed = 40000,
1234 },
1235 {
1236 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
1237 .supported = SUPPORTED_40000baseKR4_Full,
1238 .advertised = ADVERTISED_40000baseKR4_Full,
1239 .speed = 40000,
1240 },
1241 {
1242 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
1243 .supported = SUPPORTED_40000baseSR4_Full,
1244 .advertised = ADVERTISED_40000baseSR4_Full,
1245 .speed = 40000,
1246 },
1247 {
1248 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
1249 .supported = SUPPORTED_40000baseLR4_Full,
1250 .advertised = ADVERTISED_40000baseLR4_Full,
1251 .speed = 40000,
1252 },
1253 {
1254 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR |
1255 MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR |
1256 MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
1257 .speed = 25000,
1258 },
1259 {
1260 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 |
1261 MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 |
1262 MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
1263 .speed = 50000,
1264 },
1265 {
1266 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
1267 .supported = SUPPORTED_56000baseKR4_Full,
1268 .advertised = ADVERTISED_56000baseKR4_Full,
1269 .speed = 56000,
1270 },
1271 {
1272 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 |
1273 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
1274 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
1275 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
1276 .speed = 100000,
1277 },
1278};
1279
1280#define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
1281
1282static u32 mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto)
1283{
1284 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1285 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1286 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
1287 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
1288 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
1289 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
1290 return SUPPORTED_FIBRE;
1291
1292 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1293 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
1294 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
1295 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
1296 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
1297 return SUPPORTED_Backplane;
1298 return 0;
1299}
1300
1301static u32 mlxsw_sp_from_ptys_supported_link(u32 ptys_eth_proto)
1302{
1303 u32 modes = 0;
1304 int i;
1305
1306 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1307 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
1308 modes |= mlxsw_sp_port_link_mode[i].supported;
1309 }
1310 return modes;
1311}
1312
1313static u32 mlxsw_sp_from_ptys_advert_link(u32 ptys_eth_proto)
1314{
1315 u32 modes = 0;
1316 int i;
1317
1318 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1319 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
1320 modes |= mlxsw_sp_port_link_mode[i].advertised;
1321 }
1322 return modes;
1323}
1324
1325static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
1326 struct ethtool_cmd *cmd)
1327{
1328 u32 speed = SPEED_UNKNOWN;
1329 u8 duplex = DUPLEX_UNKNOWN;
1330 int i;
1331
1332 if (!carrier_ok)
1333 goto out;
1334
1335 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1336 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
1337 speed = mlxsw_sp_port_link_mode[i].speed;
1338 duplex = DUPLEX_FULL;
1339 break;
1340 }
1341 }
1342out:
1343 ethtool_cmd_speed_set(cmd, speed);
1344 cmd->duplex = duplex;
1345}
1346
1347static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
1348{
1349 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1350 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
1351 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
1352 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
1353 return PORT_FIBRE;
1354
1355 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1356 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
1357 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
1358 return PORT_DA;
1359
1360 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1361 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
1362 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
1363 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
1364 return PORT_NONE;
1365
1366 return PORT_OTHER;
1367}
1368
1369static int mlxsw_sp_port_get_settings(struct net_device *dev,
1370 struct ethtool_cmd *cmd)
1371{
1372 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1373 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1374 char ptys_pl[MLXSW_REG_PTYS_LEN];
1375 u32 eth_proto_cap;
1376 u32 eth_proto_admin;
1377 u32 eth_proto_oper;
1378 int err;
1379
1380 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
1381 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1382 if (err) {
1383 netdev_err(dev, "Failed to get proto");
1384 return err;
1385 }
1386 mlxsw_reg_ptys_unpack(ptys_pl, &eth_proto_cap,
1387 &eth_proto_admin, &eth_proto_oper);
1388
1389 cmd->supported = mlxsw_sp_from_ptys_supported_port(eth_proto_cap) |
1390 mlxsw_sp_from_ptys_supported_link(eth_proto_cap) |
Ido Schimmelc3f15762016-07-15 11:14:59 +02001391 SUPPORTED_Pause | SUPPORTED_Asym_Pause |
1392 SUPPORTED_Autoneg;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001393 cmd->advertising = mlxsw_sp_from_ptys_advert_link(eth_proto_admin);
1394 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev),
1395 eth_proto_oper, cmd);
1396
1397 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
1398 cmd->port = mlxsw_sp_port_connector_port(eth_proto_oper);
1399 cmd->lp_advertising = mlxsw_sp_from_ptys_advert_link(eth_proto_oper);
1400
1401 cmd->transceiver = XCVR_INTERNAL;
1402 return 0;
1403}
1404
1405static u32 mlxsw_sp_to_ptys_advert_link(u32 advertising)
1406{
1407 u32 ptys_proto = 0;
1408 int i;
1409
1410 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1411 if (advertising & mlxsw_sp_port_link_mode[i].advertised)
1412 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
1413 }
1414 return ptys_proto;
1415}
1416
1417static u32 mlxsw_sp_to_ptys_speed(u32 speed)
1418{
1419 u32 ptys_proto = 0;
1420 int i;
1421
1422 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1423 if (speed == mlxsw_sp_port_link_mode[i].speed)
1424 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
1425 }
1426 return ptys_proto;
1427}
1428
Ido Schimmel18f1e702016-02-26 17:32:31 +01001429static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
1430{
1431 u32 ptys_proto = 0;
1432 int i;
1433
1434 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1435 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
1436 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
1437 }
1438 return ptys_proto;
1439}
1440
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001441static int mlxsw_sp_port_set_settings(struct net_device *dev,
1442 struct ethtool_cmd *cmd)
1443{
1444 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1445 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1446 char ptys_pl[MLXSW_REG_PTYS_LEN];
1447 u32 speed;
1448 u32 eth_proto_new;
1449 u32 eth_proto_cap;
1450 u32 eth_proto_admin;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001451 int err;
1452
1453 speed = ethtool_cmd_speed(cmd);
1454
1455 eth_proto_new = cmd->autoneg == AUTONEG_ENABLE ?
1456 mlxsw_sp_to_ptys_advert_link(cmd->advertising) :
1457 mlxsw_sp_to_ptys_speed(speed);
1458
1459 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
1460 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1461 if (err) {
1462 netdev_err(dev, "Failed to get proto");
1463 return err;
1464 }
1465 mlxsw_reg_ptys_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin, NULL);
1466
1467 eth_proto_new = eth_proto_new & eth_proto_cap;
1468 if (!eth_proto_new) {
1469 netdev_err(dev, "Not supported proto admin requested");
1470 return -EINVAL;
1471 }
1472 if (eth_proto_new == eth_proto_admin)
1473 return 0;
1474
1475 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port, eth_proto_new);
1476 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1477 if (err) {
1478 netdev_err(dev, "Failed to set proto admin");
1479 return err;
1480 }
1481
Ido Schimmel6277d462016-07-15 11:14:58 +02001482 if (!netif_running(dev))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001483 return 0;
1484
1485 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1486 if (err) {
1487 netdev_err(dev, "Failed to set admin status");
1488 return err;
1489 }
1490
1491 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
1492 if (err) {
1493 netdev_err(dev, "Failed to set admin status");
1494 return err;
1495 }
1496
1497 return 0;
1498}
1499
1500static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
1501 .get_drvinfo = mlxsw_sp_port_get_drvinfo,
1502 .get_link = ethtool_op_get_link,
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001503 .get_pauseparam = mlxsw_sp_port_get_pauseparam,
1504 .set_pauseparam = mlxsw_sp_port_set_pauseparam,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001505 .get_strings = mlxsw_sp_port_get_strings,
Ido Schimmel3a66ee32015-11-27 13:45:55 +01001506 .set_phys_id = mlxsw_sp_port_set_phys_id,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001507 .get_ethtool_stats = mlxsw_sp_port_get_stats,
1508 .get_sset_count = mlxsw_sp_port_get_sset_count,
1509 .get_settings = mlxsw_sp_port_get_settings,
1510 .set_settings = mlxsw_sp_port_set_settings,
1511};
1512
Ido Schimmel18f1e702016-02-26 17:32:31 +01001513static int
1514mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
1515{
1516 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1517 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
1518 char ptys_pl[MLXSW_REG_PTYS_LEN];
1519 u32 eth_proto_admin;
1520
1521 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
1522 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port,
1523 eth_proto_admin);
1524 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1525}
1526
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001527int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
1528 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
1529 bool dwrr, u8 dwrr_weight)
Ido Schimmel90183b92016-04-06 17:10:08 +02001530{
1531 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1532 char qeec_pl[MLXSW_REG_QEEC_LEN];
1533
1534 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
1535 next_index);
1536 mlxsw_reg_qeec_de_set(qeec_pl, true);
1537 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
1538 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
1539 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
1540}
1541
Ido Schimmelcc7cf512016-04-06 17:10:11 +02001542int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
1543 enum mlxsw_reg_qeec_hr hr, u8 index,
1544 u8 next_index, u32 maxrate)
Ido Schimmel90183b92016-04-06 17:10:08 +02001545{
1546 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1547 char qeec_pl[MLXSW_REG_QEEC_LEN];
1548
1549 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
1550 next_index);
1551 mlxsw_reg_qeec_mase_set(qeec_pl, true);
1552 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
1553 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
1554}
1555
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001556int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
1557 u8 switch_prio, u8 tclass)
Ido Schimmel90183b92016-04-06 17:10:08 +02001558{
1559 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1560 char qtct_pl[MLXSW_REG_QTCT_LEN];
1561
1562 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
1563 tclass);
1564 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
1565}
1566
1567static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
1568{
1569 int err, i;
1570
1571 /* Setup the elements hierarcy, so that each TC is linked to
1572 * one subgroup, which are all member in the same group.
1573 */
1574 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
1575 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
1576 0);
1577 if (err)
1578 return err;
1579 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1580 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
1581 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
1582 0, false, 0);
1583 if (err)
1584 return err;
1585 }
1586 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1587 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
1588 MLXSW_REG_QEEC_HIERARCY_TC, i, i,
1589 false, 0);
1590 if (err)
1591 return err;
1592 }
1593
1594 /* Make sure the max shaper is disabled in all hierarcies that
1595 * support it.
1596 */
1597 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
1598 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
1599 MLXSW_REG_QEEC_MAS_DIS);
1600 if (err)
1601 return err;
1602 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1603 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
1604 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
1605 i, 0,
1606 MLXSW_REG_QEEC_MAS_DIS);
1607 if (err)
1608 return err;
1609 }
1610 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1611 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
1612 MLXSW_REG_QEEC_HIERARCY_TC,
1613 i, i,
1614 MLXSW_REG_QEEC_MAS_DIS);
1615 if (err)
1616 return err;
1617 }
1618
1619 /* Map all priorities to traffic class 0. */
1620 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1621 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
1622 if (err)
1623 return err;
1624 }
1625
1626 return 0;
1627}
1628
Ido Schimmelbe945352016-06-09 09:51:39 +02001629static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
Ido Schimmeld664b412016-06-09 09:51:40 +02001630 bool split, u8 module, u8 width, u8 lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001631{
1632 struct mlxsw_sp_port *mlxsw_sp_port;
1633 struct net_device *dev;
Ido Schimmelbd40e9d2015-12-15 16:03:36 +01001634 size_t bytes;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001635 int err;
1636
1637 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
1638 if (!dev)
1639 return -ENOMEM;
1640 mlxsw_sp_port = netdev_priv(dev);
1641 mlxsw_sp_port->dev = dev;
1642 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
1643 mlxsw_sp_port->local_port = local_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01001644 mlxsw_sp_port->split = split;
Ido Schimmeld664b412016-06-09 09:51:40 +02001645 mlxsw_sp_port->mapping.module = module;
1646 mlxsw_sp_port->mapping.width = width;
1647 mlxsw_sp_port->mapping.lane = lane;
Ido Schimmelbd40e9d2015-12-15 16:03:36 +01001648 bytes = DIV_ROUND_UP(VLAN_N_VID, BITS_PER_BYTE);
1649 mlxsw_sp_port->active_vlans = kzalloc(bytes, GFP_KERNEL);
1650 if (!mlxsw_sp_port->active_vlans) {
1651 err = -ENOMEM;
1652 goto err_port_active_vlans_alloc;
1653 }
Elad Razfc1273a2016-01-06 13:01:11 +01001654 mlxsw_sp_port->untagged_vlans = kzalloc(bytes, GFP_KERNEL);
1655 if (!mlxsw_sp_port->untagged_vlans) {
1656 err = -ENOMEM;
1657 goto err_port_untagged_vlans_alloc;
1658 }
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001659 INIT_LIST_HEAD(&mlxsw_sp_port->vports_list);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001660
1661 mlxsw_sp_port->pcpu_stats =
1662 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
1663 if (!mlxsw_sp_port->pcpu_stats) {
1664 err = -ENOMEM;
1665 goto err_alloc_stats;
1666 }
1667
1668 dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
1669 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
1670
1671 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
1672 if (err) {
1673 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
1674 mlxsw_sp_port->local_port);
1675 goto err_dev_addr_init;
1676 }
1677
1678 netif_carrier_off(dev);
1679
1680 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
1681 NETIF_F_HW_VLAN_CTAG_FILTER;
1682
1683 /* Each packet needs to have a Tx header (metadata) on top all other
1684 * headers.
1685 */
1686 dev->hard_header_len += MLXSW_TXHDR_LEN;
1687
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001688 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
1689 if (err) {
1690 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
1691 mlxsw_sp_port->local_port);
1692 goto err_port_system_port_mapping_set;
1693 }
1694
1695 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
1696 if (err) {
1697 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
1698 mlxsw_sp_port->local_port);
1699 goto err_port_swid_set;
1700 }
1701
Ido Schimmel18f1e702016-02-26 17:32:31 +01001702 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
1703 if (err) {
1704 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
1705 mlxsw_sp_port->local_port);
1706 goto err_port_speed_by_width_set;
1707 }
1708
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001709 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
1710 if (err) {
1711 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
1712 mlxsw_sp_port->local_port);
1713 goto err_port_mtu_set;
1714 }
1715
1716 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1717 if (err)
1718 goto err_port_admin_status_set;
1719
1720 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
1721 if (err) {
1722 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
1723 mlxsw_sp_port->local_port);
1724 goto err_port_buffers_init;
1725 }
1726
Ido Schimmel90183b92016-04-06 17:10:08 +02001727 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
1728 if (err) {
1729 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
1730 mlxsw_sp_port->local_port);
1731 goto err_port_ets_init;
1732 }
1733
Ido Schimmelf00817d2016-04-06 17:10:09 +02001734 /* ETS and buffers must be initialized before DCB. */
1735 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
1736 if (err) {
1737 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
1738 mlxsw_sp_port->local_port);
1739 goto err_port_dcb_init;
1740 }
1741
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001742 mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
1743 err = register_netdev(dev);
1744 if (err) {
1745 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
1746 mlxsw_sp_port->local_port);
1747 goto err_register_netdev;
1748 }
1749
Jiri Pirko932762b2016-04-08 19:11:21 +02001750 err = mlxsw_core_port_init(mlxsw_sp->core, &mlxsw_sp_port->core_port,
1751 mlxsw_sp_port->local_port, dev,
1752 mlxsw_sp_port->split, module);
1753 if (err) {
1754 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
1755 mlxsw_sp_port->local_port);
1756 goto err_core_port_init;
1757 }
Jiri Pirkoc4745502016-02-26 17:32:26 +01001758
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001759 err = mlxsw_sp_port_vlan_init(mlxsw_sp_port);
1760 if (err)
1761 goto err_port_vlan_init;
1762
1763 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
1764 return 0;
1765
1766err_port_vlan_init:
Jiri Pirko932762b2016-04-08 19:11:21 +02001767 mlxsw_core_port_fini(&mlxsw_sp_port->core_port);
1768err_core_port_init:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001769 unregister_netdev(dev);
1770err_register_netdev:
Ido Schimmelf00817d2016-04-06 17:10:09 +02001771err_port_dcb_init:
Ido Schimmel90183b92016-04-06 17:10:08 +02001772err_port_ets_init:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001773err_port_buffers_init:
1774err_port_admin_status_set:
1775err_port_mtu_set:
Ido Schimmel18f1e702016-02-26 17:32:31 +01001776err_port_speed_by_width_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001777err_port_swid_set:
1778err_port_system_port_mapping_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001779err_dev_addr_init:
1780 free_percpu(mlxsw_sp_port->pcpu_stats);
1781err_alloc_stats:
Elad Razfc1273a2016-01-06 13:01:11 +01001782 kfree(mlxsw_sp_port->untagged_vlans);
1783err_port_untagged_vlans_alloc:
Ido Schimmelbd40e9d2015-12-15 16:03:36 +01001784 kfree(mlxsw_sp_port->active_vlans);
1785err_port_active_vlans_alloc:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001786 free_netdev(dev);
1787 return err;
1788}
1789
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001790static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
1791{
1792 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
1793
1794 if (!mlxsw_sp_port)
1795 return;
Ido Schimmela1333182016-02-26 17:32:30 +01001796 mlxsw_sp->ports[local_port] = NULL;
Jiri Pirko932762b2016-04-08 19:11:21 +02001797 mlxsw_core_port_fini(&mlxsw_sp_port->core_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001798 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
Ido Schimmelf00817d2016-04-06 17:10:09 +02001799 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
Ido Schimmel32d863f2016-07-02 11:00:10 +02001800 mlxsw_sp_port_kill_vid(mlxsw_sp_port->dev, 0, 1);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001801 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
Ido Schimmel3e9b27b2016-02-26 17:32:28 +01001802 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
1803 mlxsw_sp_port_module_unmap(mlxsw_sp, mlxsw_sp_port->local_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001804 free_percpu(mlxsw_sp_port->pcpu_stats);
Elad Razfc1273a2016-01-06 13:01:11 +01001805 kfree(mlxsw_sp_port->untagged_vlans);
Ido Schimmelbd40e9d2015-12-15 16:03:36 +01001806 kfree(mlxsw_sp_port->active_vlans);
Ido Schimmel32d863f2016-07-02 11:00:10 +02001807 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vports_list));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001808 free_netdev(mlxsw_sp_port->dev);
1809}
1810
1811static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
1812{
1813 int i;
1814
1815 for (i = 1; i < MLXSW_PORT_MAX_PORTS; i++)
1816 mlxsw_sp_port_remove(mlxsw_sp, i);
1817 kfree(mlxsw_sp->ports);
1818}
1819
1820static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
1821{
Ido Schimmeld664b412016-06-09 09:51:40 +02001822 u8 module, width, lane;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001823 size_t alloc_size;
1824 int i;
1825 int err;
1826
1827 alloc_size = sizeof(struct mlxsw_sp_port *) * MLXSW_PORT_MAX_PORTS;
1828 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
1829 if (!mlxsw_sp->ports)
1830 return -ENOMEM;
1831
1832 for (i = 1; i < MLXSW_PORT_MAX_PORTS; i++) {
Ido Schimmel558c2d52016-02-26 17:32:29 +01001833 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
Ido Schimmeld664b412016-06-09 09:51:40 +02001834 &width, &lane);
Ido Schimmel558c2d52016-02-26 17:32:29 +01001835 if (err)
1836 goto err_port_module_info_get;
1837 if (!width)
1838 continue;
1839 mlxsw_sp->port_to_module[i] = module;
Ido Schimmeld664b412016-06-09 09:51:40 +02001840 err = mlxsw_sp_port_create(mlxsw_sp, i, false, module, width,
1841 lane);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001842 if (err)
1843 goto err_port_create;
1844 }
1845 return 0;
1846
1847err_port_create:
Ido Schimmel558c2d52016-02-26 17:32:29 +01001848err_port_module_info_get:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001849 for (i--; i >= 1; i--)
1850 mlxsw_sp_port_remove(mlxsw_sp, i);
1851 kfree(mlxsw_sp->ports);
1852 return err;
1853}
1854
Ido Schimmel18f1e702016-02-26 17:32:31 +01001855static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
1856{
1857 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
1858
1859 return local_port - offset;
1860}
1861
Ido Schimmelbe945352016-06-09 09:51:39 +02001862static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
1863 u8 module, unsigned int count)
1864{
1865 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
1866 int err, i;
1867
1868 for (i = 0; i < count; i++) {
1869 err = mlxsw_sp_port_module_map(mlxsw_sp, base_port + i, module,
1870 width, i * width);
1871 if (err)
1872 goto err_port_module_map;
1873 }
1874
1875 for (i = 0; i < count; i++) {
1876 err = __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i, 0);
1877 if (err)
1878 goto err_port_swid_set;
1879 }
1880
1881 for (i = 0; i < count; i++) {
1882 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
Ido Schimmeld664b412016-06-09 09:51:40 +02001883 module, width, i * width);
Ido Schimmelbe945352016-06-09 09:51:39 +02001884 if (err)
1885 goto err_port_create;
1886 }
1887
1888 return 0;
1889
1890err_port_create:
1891 for (i--; i >= 0; i--)
1892 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
1893 i = count;
1894err_port_swid_set:
1895 for (i--; i >= 0; i--)
1896 __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i,
1897 MLXSW_PORT_SWID_DISABLED_PORT);
1898 i = count;
1899err_port_module_map:
1900 for (i--; i >= 0; i--)
1901 mlxsw_sp_port_module_unmap(mlxsw_sp, base_port + i);
1902 return err;
1903}
1904
1905static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
1906 u8 base_port, unsigned int count)
1907{
1908 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
1909 int i;
1910
1911 /* Split by four means we need to re-create two ports, otherwise
1912 * only one.
1913 */
1914 count = count / 2;
1915
1916 for (i = 0; i < count; i++) {
1917 local_port = base_port + i * 2;
1918 module = mlxsw_sp->port_to_module[local_port];
1919
1920 mlxsw_sp_port_module_map(mlxsw_sp, local_port, module, width,
1921 0);
1922 }
1923
1924 for (i = 0; i < count; i++)
1925 __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i * 2, 0);
1926
1927 for (i = 0; i < count; i++) {
1928 local_port = base_port + i * 2;
1929 module = mlxsw_sp->port_to_module[local_port];
1930
1931 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
Ido Schimmeld664b412016-06-09 09:51:40 +02001932 width, 0);
Ido Schimmelbe945352016-06-09 09:51:39 +02001933 }
1934}
1935
Jiri Pirkob2f10572016-04-08 19:11:23 +02001936static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
1937 unsigned int count)
Ido Schimmel18f1e702016-02-26 17:32:31 +01001938{
Jiri Pirkob2f10572016-04-08 19:11:23 +02001939 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01001940 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01001941 u8 module, cur_width, base_port;
1942 int i;
1943 int err;
1944
1945 mlxsw_sp_port = mlxsw_sp->ports[local_port];
1946 if (!mlxsw_sp_port) {
1947 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
1948 local_port);
1949 return -EINVAL;
1950 }
1951
Ido Schimmeld664b412016-06-09 09:51:40 +02001952 module = mlxsw_sp_port->mapping.module;
1953 cur_width = mlxsw_sp_port->mapping.width;
1954
Ido Schimmel18f1e702016-02-26 17:32:31 +01001955 if (count != 2 && count != 4) {
1956 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
1957 return -EINVAL;
1958 }
1959
Ido Schimmel18f1e702016-02-26 17:32:31 +01001960 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
1961 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
1962 return -EINVAL;
1963 }
1964
1965 /* Make sure we have enough slave (even) ports for the split. */
1966 if (count == 2) {
1967 base_port = local_port;
1968 if (mlxsw_sp->ports[base_port + 1]) {
1969 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
1970 return -EINVAL;
1971 }
1972 } else {
1973 base_port = mlxsw_sp_cluster_base_port_get(local_port);
1974 if (mlxsw_sp->ports[base_port + 1] ||
1975 mlxsw_sp->ports[base_port + 3]) {
1976 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
1977 return -EINVAL;
1978 }
1979 }
1980
1981 for (i = 0; i < count; i++)
1982 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
1983
Ido Schimmelbe945352016-06-09 09:51:39 +02001984 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count);
1985 if (err) {
1986 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
1987 goto err_port_split_create;
Ido Schimmel18f1e702016-02-26 17:32:31 +01001988 }
1989
1990 return 0;
1991
Ido Schimmelbe945352016-06-09 09:51:39 +02001992err_port_split_create:
1993 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01001994 return err;
1995}
1996
Jiri Pirkob2f10572016-04-08 19:11:23 +02001997static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port)
Ido Schimmel18f1e702016-02-26 17:32:31 +01001998{
Jiri Pirkob2f10572016-04-08 19:11:23 +02001999 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01002000 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmeld664b412016-06-09 09:51:40 +02002001 u8 cur_width, base_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01002002 unsigned int count;
2003 int i;
Ido Schimmel18f1e702016-02-26 17:32:31 +01002004
2005 mlxsw_sp_port = mlxsw_sp->ports[local_port];
2006 if (!mlxsw_sp_port) {
2007 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
2008 local_port);
2009 return -EINVAL;
2010 }
2011
2012 if (!mlxsw_sp_port->split) {
2013 netdev_err(mlxsw_sp_port->dev, "Port wasn't split\n");
2014 return -EINVAL;
2015 }
2016
Ido Schimmeld664b412016-06-09 09:51:40 +02002017 cur_width = mlxsw_sp_port->mapping.width;
Ido Schimmel18f1e702016-02-26 17:32:31 +01002018 count = cur_width == 1 ? 4 : 2;
2019
2020 base_port = mlxsw_sp_cluster_base_port_get(local_port);
2021
2022 /* Determine which ports to remove. */
2023 if (count == 2 && local_port >= base_port + 2)
2024 base_port = base_port + 2;
2025
2026 for (i = 0; i < count; i++)
2027 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
2028
Ido Schimmelbe945352016-06-09 09:51:39 +02002029 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01002030
2031 return 0;
2032}
2033
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002034static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
2035 char *pude_pl, void *priv)
2036{
2037 struct mlxsw_sp *mlxsw_sp = priv;
2038 struct mlxsw_sp_port *mlxsw_sp_port;
2039 enum mlxsw_reg_pude_oper_status status;
2040 u8 local_port;
2041
2042 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
2043 mlxsw_sp_port = mlxsw_sp->ports[local_port];
Ido Schimmelbbf2a472016-07-02 11:00:14 +02002044 if (!mlxsw_sp_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002045 return;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002046
2047 status = mlxsw_reg_pude_oper_status_get(pude_pl);
2048 if (status == MLXSW_PORT_OPER_STATUS_UP) {
2049 netdev_info(mlxsw_sp_port->dev, "link up\n");
2050 netif_carrier_on(mlxsw_sp_port->dev);
2051 } else {
2052 netdev_info(mlxsw_sp_port->dev, "link down\n");
2053 netif_carrier_off(mlxsw_sp_port->dev);
2054 }
2055}
2056
2057static struct mlxsw_event_listener mlxsw_sp_pude_event = {
2058 .func = mlxsw_sp_pude_event_func,
2059 .trap_id = MLXSW_TRAP_ID_PUDE,
2060};
2061
2062static int mlxsw_sp_event_register(struct mlxsw_sp *mlxsw_sp,
2063 enum mlxsw_event_trap_id trap_id)
2064{
2065 struct mlxsw_event_listener *el;
2066 char hpkt_pl[MLXSW_REG_HPKT_LEN];
2067 int err;
2068
2069 switch (trap_id) {
2070 case MLXSW_TRAP_ID_PUDE:
2071 el = &mlxsw_sp_pude_event;
2072 break;
2073 }
2074 err = mlxsw_core_event_listener_register(mlxsw_sp->core, el, mlxsw_sp);
2075 if (err)
2076 return err;
2077
2078 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD, trap_id);
2079 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2080 if (err)
2081 goto err_event_trap_set;
2082
2083 return 0;
2084
2085err_event_trap_set:
2086 mlxsw_core_event_listener_unregister(mlxsw_sp->core, el, mlxsw_sp);
2087 return err;
2088}
2089
2090static void mlxsw_sp_event_unregister(struct mlxsw_sp *mlxsw_sp,
2091 enum mlxsw_event_trap_id trap_id)
2092{
2093 struct mlxsw_event_listener *el;
2094
2095 switch (trap_id) {
2096 case MLXSW_TRAP_ID_PUDE:
2097 el = &mlxsw_sp_pude_event;
2098 break;
2099 }
2100 mlxsw_core_event_listener_unregister(mlxsw_sp->core, el, mlxsw_sp);
2101}
2102
2103static void mlxsw_sp_rx_listener_func(struct sk_buff *skb, u8 local_port,
2104 void *priv)
2105{
2106 struct mlxsw_sp *mlxsw_sp = priv;
2107 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
2108 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
2109
2110 if (unlikely(!mlxsw_sp_port)) {
2111 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
2112 local_port);
2113 return;
2114 }
2115
2116 skb->dev = mlxsw_sp_port->dev;
2117
2118 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
2119 u64_stats_update_begin(&pcpu_stats->syncp);
2120 pcpu_stats->rx_packets++;
2121 pcpu_stats->rx_bytes += skb->len;
2122 u64_stats_update_end(&pcpu_stats->syncp);
2123
2124 skb->protocol = eth_type_trans(skb, skb->dev);
2125 netif_receive_skb(skb);
2126}
2127
2128static const struct mlxsw_rx_listener mlxsw_sp_rx_listener[] = {
2129 {
2130 .func = mlxsw_sp_rx_listener_func,
2131 .local_port = MLXSW_PORT_DONT_CARE,
2132 .trap_id = MLXSW_TRAP_ID_FDB_MC,
2133 },
2134 /* Traps for specific L2 packet types, not trapped as FDB MC */
2135 {
2136 .func = mlxsw_sp_rx_listener_func,
2137 .local_port = MLXSW_PORT_DONT_CARE,
2138 .trap_id = MLXSW_TRAP_ID_STP,
2139 },
2140 {
2141 .func = mlxsw_sp_rx_listener_func,
2142 .local_port = MLXSW_PORT_DONT_CARE,
2143 .trap_id = MLXSW_TRAP_ID_LACP,
2144 },
2145 {
2146 .func = mlxsw_sp_rx_listener_func,
2147 .local_port = MLXSW_PORT_DONT_CARE,
2148 .trap_id = MLXSW_TRAP_ID_EAPOL,
2149 },
2150 {
2151 .func = mlxsw_sp_rx_listener_func,
2152 .local_port = MLXSW_PORT_DONT_CARE,
2153 .trap_id = MLXSW_TRAP_ID_LLDP,
2154 },
2155 {
2156 .func = mlxsw_sp_rx_listener_func,
2157 .local_port = MLXSW_PORT_DONT_CARE,
2158 .trap_id = MLXSW_TRAP_ID_MMRP,
2159 },
2160 {
2161 .func = mlxsw_sp_rx_listener_func,
2162 .local_port = MLXSW_PORT_DONT_CARE,
2163 .trap_id = MLXSW_TRAP_ID_MVRP,
2164 },
2165 {
2166 .func = mlxsw_sp_rx_listener_func,
2167 .local_port = MLXSW_PORT_DONT_CARE,
2168 .trap_id = MLXSW_TRAP_ID_RPVST,
2169 },
2170 {
2171 .func = mlxsw_sp_rx_listener_func,
2172 .local_port = MLXSW_PORT_DONT_CARE,
2173 .trap_id = MLXSW_TRAP_ID_DHCP,
2174 },
2175 {
2176 .func = mlxsw_sp_rx_listener_func,
2177 .local_port = MLXSW_PORT_DONT_CARE,
2178 .trap_id = MLXSW_TRAP_ID_IGMP_QUERY,
2179 },
2180 {
2181 .func = mlxsw_sp_rx_listener_func,
2182 .local_port = MLXSW_PORT_DONT_CARE,
2183 .trap_id = MLXSW_TRAP_ID_IGMP_V1_REPORT,
2184 },
2185 {
2186 .func = mlxsw_sp_rx_listener_func,
2187 .local_port = MLXSW_PORT_DONT_CARE,
2188 .trap_id = MLXSW_TRAP_ID_IGMP_V2_REPORT,
2189 },
2190 {
2191 .func = mlxsw_sp_rx_listener_func,
2192 .local_port = MLXSW_PORT_DONT_CARE,
2193 .trap_id = MLXSW_TRAP_ID_IGMP_V2_LEAVE,
2194 },
2195 {
2196 .func = mlxsw_sp_rx_listener_func,
2197 .local_port = MLXSW_PORT_DONT_CARE,
2198 .trap_id = MLXSW_TRAP_ID_IGMP_V3_REPORT,
2199 },
Jiri Pirko7b27ce72016-07-02 11:00:20 +02002200 {
2201 .func = mlxsw_sp_rx_listener_func,
2202 .local_port = MLXSW_PORT_DONT_CARE,
2203 .trap_id = MLXSW_TRAP_ID_ARPBC,
2204 },
2205 {
2206 .func = mlxsw_sp_rx_listener_func,
2207 .local_port = MLXSW_PORT_DONT_CARE,
2208 .trap_id = MLXSW_TRAP_ID_ARPUC,
2209 },
2210 {
2211 .func = mlxsw_sp_rx_listener_func,
2212 .local_port = MLXSW_PORT_DONT_CARE,
2213 .trap_id = MLXSW_TRAP_ID_IP2ME,
2214 },
2215 {
2216 .func = mlxsw_sp_rx_listener_func,
2217 .local_port = MLXSW_PORT_DONT_CARE,
2218 .trap_id = MLXSW_TRAP_ID_RTR_INGRESS0,
2219 },
2220 {
2221 .func = mlxsw_sp_rx_listener_func,
2222 .local_port = MLXSW_PORT_DONT_CARE,
2223 .trap_id = MLXSW_TRAP_ID_HOST_MISS_IPV4,
2224 },
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002225};
2226
2227static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
2228{
2229 char htgt_pl[MLXSW_REG_HTGT_LEN];
2230 char hpkt_pl[MLXSW_REG_HPKT_LEN];
2231 int i;
2232 int err;
2233
2234 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_RX);
2235 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(htgt), htgt_pl);
2236 if (err)
2237 return err;
2238
2239 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_CTRL);
2240 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(htgt), htgt_pl);
2241 if (err)
2242 return err;
2243
2244 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_rx_listener); i++) {
2245 err = mlxsw_core_rx_listener_register(mlxsw_sp->core,
2246 &mlxsw_sp_rx_listener[i],
2247 mlxsw_sp);
2248 if (err)
2249 goto err_rx_listener_register;
2250
2251 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU,
2252 mlxsw_sp_rx_listener[i].trap_id);
2253 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2254 if (err)
2255 goto err_rx_trap_set;
2256 }
2257 return 0;
2258
2259err_rx_trap_set:
2260 mlxsw_core_rx_listener_unregister(mlxsw_sp->core,
2261 &mlxsw_sp_rx_listener[i],
2262 mlxsw_sp);
2263err_rx_listener_register:
2264 for (i--; i >= 0; i--) {
Ido Schimmel10f00aa2016-07-02 11:00:19 +02002265 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_DISCARD,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002266 mlxsw_sp_rx_listener[i].trap_id);
2267 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2268
2269 mlxsw_core_rx_listener_unregister(mlxsw_sp->core,
2270 &mlxsw_sp_rx_listener[i],
2271 mlxsw_sp);
2272 }
2273 return err;
2274}
2275
2276static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
2277{
2278 char hpkt_pl[MLXSW_REG_HPKT_LEN];
2279 int i;
2280
2281 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_rx_listener); i++) {
Ido Schimmel10f00aa2016-07-02 11:00:19 +02002282 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_DISCARD,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002283 mlxsw_sp_rx_listener[i].trap_id);
2284 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2285
2286 mlxsw_core_rx_listener_unregister(mlxsw_sp->core,
2287 &mlxsw_sp_rx_listener[i],
2288 mlxsw_sp);
2289 }
2290}
2291
2292static int __mlxsw_sp_flood_init(struct mlxsw_core *mlxsw_core,
2293 enum mlxsw_reg_sfgc_type type,
2294 enum mlxsw_reg_sfgc_bridge_type bridge_type)
2295{
2296 enum mlxsw_flood_table_type table_type;
2297 enum mlxsw_sp_flood_table flood_table;
2298 char sfgc_pl[MLXSW_REG_SFGC_LEN];
2299
Ido Schimmel19ae6122015-12-15 16:03:39 +01002300 if (bridge_type == MLXSW_REG_SFGC_BRIDGE_TYPE_VFID)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002301 table_type = MLXSW_REG_SFGC_TABLE_TYPE_FID;
Ido Schimmel19ae6122015-12-15 16:03:39 +01002302 else
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002303 table_type = MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST;
Ido Schimmel19ae6122015-12-15 16:03:39 +01002304
2305 if (type == MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST)
2306 flood_table = MLXSW_SP_FLOOD_TABLE_UC;
2307 else
2308 flood_table = MLXSW_SP_FLOOD_TABLE_BM;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002309
2310 mlxsw_reg_sfgc_pack(sfgc_pl, type, bridge_type, table_type,
2311 flood_table);
2312 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(sfgc), sfgc_pl);
2313}
2314
2315static int mlxsw_sp_flood_init(struct mlxsw_sp *mlxsw_sp)
2316{
2317 int type, err;
2318
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002319 for (type = 0; type < MLXSW_REG_SFGC_TYPE_MAX; type++) {
2320 if (type == MLXSW_REG_SFGC_TYPE_RESERVED)
2321 continue;
2322
2323 err = __mlxsw_sp_flood_init(mlxsw_sp->core, type,
2324 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID);
2325 if (err)
2326 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002327
2328 err = __mlxsw_sp_flood_init(mlxsw_sp->core, type,
2329 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID);
2330 if (err)
2331 return err;
2332 }
2333
2334 return 0;
2335}
2336
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002337static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
2338{
2339 char slcr_pl[MLXSW_REG_SLCR_LEN];
2340
2341 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
2342 MLXSW_REG_SLCR_LAG_HASH_DMAC |
2343 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
2344 MLXSW_REG_SLCR_LAG_HASH_VLANID |
2345 MLXSW_REG_SLCR_LAG_HASH_SIP |
2346 MLXSW_REG_SLCR_LAG_HASH_DIP |
2347 MLXSW_REG_SLCR_LAG_HASH_SPORT |
2348 MLXSW_REG_SLCR_LAG_HASH_DPORT |
2349 MLXSW_REG_SLCR_LAG_HASH_IPPROTO);
2350 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
2351}
2352
Jiri Pirkob2f10572016-04-08 19:11:23 +02002353static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002354 const struct mlxsw_bus_info *mlxsw_bus_info)
2355{
Jiri Pirkob2f10572016-04-08 19:11:23 +02002356 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002357 int err;
2358
2359 mlxsw_sp->core = mlxsw_core;
2360 mlxsw_sp->bus_info = mlxsw_bus_info;
Ido Schimmel14d39462016-06-20 23:04:15 +02002361 INIT_LIST_HEAD(&mlxsw_sp->fids);
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02002362 INIT_LIST_HEAD(&mlxsw_sp->vfids.list);
Elad Raz3a49b4f2016-01-10 21:06:28 +01002363 INIT_LIST_HEAD(&mlxsw_sp->br_mids.list);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002364
2365 err = mlxsw_sp_base_mac_get(mlxsw_sp);
2366 if (err) {
2367 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
2368 return err;
2369 }
2370
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002371 err = mlxsw_sp_event_register(mlxsw_sp, MLXSW_TRAP_ID_PUDE);
2372 if (err) {
2373 dev_err(mlxsw_sp->bus_info->dev, "Failed to register for PUDE events\n");
Ido Schimmelbbf2a472016-07-02 11:00:14 +02002374 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002375 }
2376
2377 err = mlxsw_sp_traps_init(mlxsw_sp);
2378 if (err) {
2379 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps for RX\n");
2380 goto err_rx_listener_register;
2381 }
2382
2383 err = mlxsw_sp_flood_init(mlxsw_sp);
2384 if (err) {
2385 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize flood tables\n");
2386 goto err_flood_init;
2387 }
2388
2389 err = mlxsw_sp_buffers_init(mlxsw_sp);
2390 if (err) {
2391 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
2392 goto err_buffers_init;
2393 }
2394
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002395 err = mlxsw_sp_lag_init(mlxsw_sp);
2396 if (err) {
2397 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
2398 goto err_lag_init;
2399 }
2400
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002401 err = mlxsw_sp_switchdev_init(mlxsw_sp);
2402 if (err) {
2403 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
2404 goto err_switchdev_init;
2405 }
2406
Ido Schimmel464dce12016-07-02 11:00:15 +02002407 err = mlxsw_sp_router_init(mlxsw_sp);
2408 if (err) {
2409 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
2410 goto err_router_init;
2411 }
2412
Ido Schimmelbbf2a472016-07-02 11:00:14 +02002413 err = mlxsw_sp_ports_create(mlxsw_sp);
2414 if (err) {
2415 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
2416 goto err_ports_create;
2417 }
2418
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002419 return 0;
2420
Ido Schimmelbbf2a472016-07-02 11:00:14 +02002421err_ports_create:
Ido Schimmel464dce12016-07-02 11:00:15 +02002422 mlxsw_sp_router_fini(mlxsw_sp);
2423err_router_init:
Ido Schimmelbbf2a472016-07-02 11:00:14 +02002424 mlxsw_sp_switchdev_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002425err_switchdev_init:
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002426err_lag_init:
Jiri Pirko0f433fa2016-04-14 18:19:24 +02002427 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002428err_buffers_init:
2429err_flood_init:
2430 mlxsw_sp_traps_fini(mlxsw_sp);
2431err_rx_listener_register:
2432 mlxsw_sp_event_unregister(mlxsw_sp, MLXSW_TRAP_ID_PUDE);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002433 return err;
2434}
2435
Jiri Pirkob2f10572016-04-08 19:11:23 +02002436static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002437{
Jiri Pirkob2f10572016-04-08 19:11:23 +02002438 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmelfa3054f2016-07-02 11:00:16 +02002439 int i;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002440
Ido Schimmelbbf2a472016-07-02 11:00:14 +02002441 mlxsw_sp_ports_remove(mlxsw_sp);
Ido Schimmel464dce12016-07-02 11:00:15 +02002442 mlxsw_sp_router_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002443 mlxsw_sp_switchdev_fini(mlxsw_sp);
Jiri Pirko5113bfd2016-05-06 22:20:59 +02002444 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002445 mlxsw_sp_traps_fini(mlxsw_sp);
2446 mlxsw_sp_event_unregister(mlxsw_sp, MLXSW_TRAP_ID_PUDE);
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02002447 WARN_ON(!list_empty(&mlxsw_sp->vfids.list));
Ido Schimmel14d39462016-06-20 23:04:15 +02002448 WARN_ON(!list_empty(&mlxsw_sp->fids));
Ido Schimmelfa3054f2016-07-02 11:00:16 +02002449 for (i = 0; i < MLXSW_SP_RIF_MAX; i++)
2450 WARN_ON_ONCE(mlxsw_sp->rifs[i]);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002451}
2452
2453static struct mlxsw_config_profile mlxsw_sp_config_profile = {
2454 .used_max_vepa_channels = 1,
2455 .max_vepa_channels = 0,
2456 .used_max_lag = 1,
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002457 .max_lag = MLXSW_SP_LAG_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002458 .used_max_port_per_lag = 1,
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002459 .max_port_per_lag = MLXSW_SP_PORT_PER_LAG_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002460 .used_max_mid = 1,
Elad Raz53ae6282016-01-10 21:06:26 +01002461 .max_mid = MLXSW_SP_MID_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002462 .used_max_pgt = 1,
2463 .max_pgt = 0,
2464 .used_max_system_port = 1,
2465 .max_system_port = 64,
2466 .used_max_vlan_groups = 1,
2467 .max_vlan_groups = 127,
2468 .used_max_regions = 1,
2469 .max_regions = 400,
2470 .used_flood_tables = 1,
2471 .used_flood_mode = 1,
2472 .flood_mode = 3,
2473 .max_fid_offset_flood_tables = 2,
2474 .fid_offset_flood_table_size = VLAN_N_VID - 1,
Ido Schimmel19ae6122015-12-15 16:03:39 +01002475 .max_fid_flood_tables = 2,
2476 .fid_flood_table_size = MLXSW_SP_VFID_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002477 .used_max_ib_mc = 1,
2478 .max_ib_mc = 0,
2479 .used_max_pkey = 1,
2480 .max_pkey = 0,
Jiri Pirkoc6022422016-07-05 11:27:46 +02002481 .used_kvd_sizes = 1,
2482 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE,
2483 .kvd_hash_single_size = MLXSW_SP_KVD_HASH_SINGLE_SIZE,
2484 .kvd_hash_double_size = MLXSW_SP_KVD_HASH_DOUBLE_SIZE,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002485 .swid_config = {
2486 {
2487 .used_type = 1,
2488 .type = MLXSW_PORT_SWID_TYPE_ETH,
2489 }
2490 },
Nogah Frankel57d316b2016-07-21 12:03:09 +02002491 .resource_query_enable = 1,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002492};
2493
2494static struct mlxsw_driver mlxsw_sp_driver = {
Jiri Pirko2d0ed392016-04-14 18:19:30 +02002495 .kind = MLXSW_DEVICE_KIND_SPECTRUM,
2496 .owner = THIS_MODULE,
2497 .priv_size = sizeof(struct mlxsw_sp),
2498 .init = mlxsw_sp_init,
2499 .fini = mlxsw_sp_fini,
2500 .port_split = mlxsw_sp_port_split,
2501 .port_unsplit = mlxsw_sp_port_unsplit,
2502 .sb_pool_get = mlxsw_sp_sb_pool_get,
2503 .sb_pool_set = mlxsw_sp_sb_pool_set,
2504 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
2505 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
2506 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
2507 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
2508 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
2509 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
2510 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
2511 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
2512 .txhdr_construct = mlxsw_sp_txhdr_construct,
2513 .txhdr_len = MLXSW_TXHDR_LEN,
2514 .profile = &mlxsw_sp_config_profile,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002515};
2516
Jiri Pirko7ce856a2016-07-04 08:23:12 +02002517static bool mlxsw_sp_port_dev_check(const struct net_device *dev)
2518{
2519 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
2520}
2521
2522static struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
2523{
2524 struct net_device *lower_dev;
2525 struct list_head *iter;
2526
2527 if (mlxsw_sp_port_dev_check(dev))
2528 return netdev_priv(dev);
2529
2530 netdev_for_each_all_lower_dev(dev, lower_dev, iter) {
2531 if (mlxsw_sp_port_dev_check(lower_dev))
2532 return netdev_priv(lower_dev);
2533 }
2534 return NULL;
2535}
2536
2537static struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
2538{
2539 struct mlxsw_sp_port *mlxsw_sp_port;
2540
2541 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
2542 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
2543}
2544
2545static struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
2546{
2547 struct net_device *lower_dev;
2548 struct list_head *iter;
2549
2550 if (mlxsw_sp_port_dev_check(dev))
2551 return netdev_priv(dev);
2552
2553 netdev_for_each_all_lower_dev_rcu(dev, lower_dev, iter) {
2554 if (mlxsw_sp_port_dev_check(lower_dev))
2555 return netdev_priv(lower_dev);
2556 }
2557 return NULL;
2558}
2559
2560struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev)
2561{
2562 struct mlxsw_sp_port *mlxsw_sp_port;
2563
2564 rcu_read_lock();
2565 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev);
2566 if (mlxsw_sp_port)
2567 dev_hold(mlxsw_sp_port->dev);
2568 rcu_read_unlock();
2569 return mlxsw_sp_port;
2570}
2571
2572void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port)
2573{
2574 dev_put(mlxsw_sp_port->dev);
2575}
2576
Ido Schimmel99724c12016-07-04 08:23:14 +02002577static bool mlxsw_sp_rif_should_config(struct mlxsw_sp_rif *r,
2578 unsigned long event)
2579{
2580 switch (event) {
2581 case NETDEV_UP:
2582 if (!r)
2583 return true;
2584 r->ref_count++;
2585 return false;
2586 case NETDEV_DOWN:
2587 if (r && --r->ref_count == 0)
2588 return true;
2589 /* It is possible we already removed the RIF ourselves
2590 * if it was assigned to a netdev that is now a bridge
2591 * or LAG slave.
2592 */
2593 return false;
2594 }
2595
2596 return false;
2597}
2598
2599static int mlxsw_sp_avail_rif_get(struct mlxsw_sp *mlxsw_sp)
2600{
2601 int i;
2602
2603 for (i = 0; i < MLXSW_SP_RIF_MAX; i++)
2604 if (!mlxsw_sp->rifs[i])
2605 return i;
2606
2607 return MLXSW_SP_RIF_MAX;
2608}
2609
2610static void mlxsw_sp_vport_rif_sp_attr_get(struct mlxsw_sp_port *mlxsw_sp_vport,
2611 bool *p_lagged, u16 *p_system_port)
2612{
2613 u8 local_port = mlxsw_sp_vport->local_port;
2614
2615 *p_lagged = mlxsw_sp_vport->lagged;
2616 *p_system_port = *p_lagged ? mlxsw_sp_vport->lag_id : local_port;
2617}
2618
2619static int mlxsw_sp_vport_rif_sp_op(struct mlxsw_sp_port *mlxsw_sp_vport,
2620 struct net_device *l3_dev, u16 rif,
2621 bool create)
2622{
2623 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_vport->mlxsw_sp;
2624 bool lagged = mlxsw_sp_vport->lagged;
2625 char ritr_pl[MLXSW_REG_RITR_LEN];
2626 u16 system_port;
2627
2628 mlxsw_reg_ritr_pack(ritr_pl, create, MLXSW_REG_RITR_SP_IF, rif,
2629 l3_dev->mtu, l3_dev->dev_addr);
2630
2631 mlxsw_sp_vport_rif_sp_attr_get(mlxsw_sp_vport, &lagged, &system_port);
2632 mlxsw_reg_ritr_sp_if_pack(ritr_pl, lagged, system_port,
2633 mlxsw_sp_vport_vid_get(mlxsw_sp_vport));
2634
2635 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ritr), ritr_pl);
2636}
2637
2638static void mlxsw_sp_vport_rif_sp_leave(struct mlxsw_sp_port *mlxsw_sp_vport);
2639
2640static struct mlxsw_sp_fid *
2641mlxsw_sp_rfid_alloc(u16 fid, struct net_device *l3_dev)
2642{
2643 struct mlxsw_sp_fid *f;
2644
2645 f = kzalloc(sizeof(*f), GFP_KERNEL);
2646 if (!f)
2647 return NULL;
2648
2649 f->leave = mlxsw_sp_vport_rif_sp_leave;
2650 f->ref_count = 0;
2651 f->dev = l3_dev;
2652 f->fid = fid;
2653
2654 return f;
2655}
2656
2657static struct mlxsw_sp_rif *
2658mlxsw_sp_rif_alloc(u16 rif, struct net_device *l3_dev, struct mlxsw_sp_fid *f)
2659{
2660 struct mlxsw_sp_rif *r;
2661
2662 r = kzalloc(sizeof(*r), GFP_KERNEL);
2663 if (!r)
2664 return NULL;
2665
2666 ether_addr_copy(r->addr, l3_dev->dev_addr);
2667 r->mtu = l3_dev->mtu;
2668 r->ref_count = 1;
2669 r->dev = l3_dev;
2670 r->rif = rif;
2671 r->f = f;
2672
2673 return r;
2674}
2675
2676static struct mlxsw_sp_rif *
2677mlxsw_sp_vport_rif_sp_create(struct mlxsw_sp_port *mlxsw_sp_vport,
2678 struct net_device *l3_dev)
2679{
2680 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_vport->mlxsw_sp;
2681 struct mlxsw_sp_fid *f;
2682 struct mlxsw_sp_rif *r;
2683 u16 fid, rif;
2684 int err;
2685
2686 rif = mlxsw_sp_avail_rif_get(mlxsw_sp);
2687 if (rif == MLXSW_SP_RIF_MAX)
2688 return ERR_PTR(-ERANGE);
2689
2690 err = mlxsw_sp_vport_rif_sp_op(mlxsw_sp_vport, l3_dev, rif, true);
2691 if (err)
2692 return ERR_PTR(err);
2693
2694 fid = mlxsw_sp_rif_sp_to_fid(rif);
2695 err = mlxsw_sp_rif_fdb_op(mlxsw_sp, l3_dev->dev_addr, fid, true);
2696 if (err)
2697 goto err_rif_fdb_op;
2698
2699 f = mlxsw_sp_rfid_alloc(fid, l3_dev);
2700 if (!f) {
2701 err = -ENOMEM;
2702 goto err_rfid_alloc;
2703 }
2704
2705 r = mlxsw_sp_rif_alloc(rif, l3_dev, f);
2706 if (!r) {
2707 err = -ENOMEM;
2708 goto err_rif_alloc;
2709 }
2710
2711 f->r = r;
2712 mlxsw_sp->rifs[rif] = r;
2713
2714 return r;
2715
2716err_rif_alloc:
2717 kfree(f);
2718err_rfid_alloc:
2719 mlxsw_sp_rif_fdb_op(mlxsw_sp, l3_dev->dev_addr, fid, false);
2720err_rif_fdb_op:
2721 mlxsw_sp_vport_rif_sp_op(mlxsw_sp_vport, l3_dev, rif, false);
2722 return ERR_PTR(err);
2723}
2724
2725static void mlxsw_sp_vport_rif_sp_destroy(struct mlxsw_sp_port *mlxsw_sp_vport,
2726 struct mlxsw_sp_rif *r)
2727{
2728 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_vport->mlxsw_sp;
2729 struct net_device *l3_dev = r->dev;
2730 struct mlxsw_sp_fid *f = r->f;
2731 u16 fid = f->fid;
2732 u16 rif = r->rif;
2733
2734 mlxsw_sp->rifs[rif] = NULL;
2735 f->r = NULL;
2736
2737 kfree(r);
2738
2739 kfree(f);
2740
2741 mlxsw_sp_rif_fdb_op(mlxsw_sp, l3_dev->dev_addr, fid, false);
2742
2743 mlxsw_sp_vport_rif_sp_op(mlxsw_sp_vport, l3_dev, rif, false);
2744}
2745
2746static int mlxsw_sp_vport_rif_sp_join(struct mlxsw_sp_port *mlxsw_sp_vport,
2747 struct net_device *l3_dev)
2748{
2749 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_vport->mlxsw_sp;
2750 struct mlxsw_sp_rif *r;
2751
2752 r = mlxsw_sp_rif_find_by_dev(mlxsw_sp, l3_dev);
2753 if (!r) {
2754 r = mlxsw_sp_vport_rif_sp_create(mlxsw_sp_vport, l3_dev);
2755 if (IS_ERR(r))
2756 return PTR_ERR(r);
2757 }
2758
2759 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, r->f);
2760 r->f->ref_count++;
2761
2762 netdev_dbg(mlxsw_sp_vport->dev, "Joined FID=%d\n", r->f->fid);
2763
2764 return 0;
2765}
2766
2767static void mlxsw_sp_vport_rif_sp_leave(struct mlxsw_sp_port *mlxsw_sp_vport)
2768{
2769 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
2770
2771 netdev_dbg(mlxsw_sp_vport->dev, "Left FID=%d\n", f->fid);
2772
2773 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, NULL);
2774 if (--f->ref_count == 0)
2775 mlxsw_sp_vport_rif_sp_destroy(mlxsw_sp_vport, f->r);
2776}
2777
2778static int mlxsw_sp_inetaddr_vport_event(struct net_device *l3_dev,
2779 struct net_device *port_dev,
2780 unsigned long event, u16 vid)
2781{
2782 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(port_dev);
2783 struct mlxsw_sp_port *mlxsw_sp_vport;
2784
2785 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
2786 if (WARN_ON(!mlxsw_sp_vport))
2787 return -EINVAL;
2788
2789 switch (event) {
2790 case NETDEV_UP:
2791 return mlxsw_sp_vport_rif_sp_join(mlxsw_sp_vport, l3_dev);
2792 case NETDEV_DOWN:
2793 mlxsw_sp_vport_rif_sp_leave(mlxsw_sp_vport);
2794 break;
2795 }
2796
2797 return 0;
2798}
2799
2800static int mlxsw_sp_inetaddr_port_event(struct net_device *port_dev,
2801 unsigned long event)
2802{
2803 if (netif_is_bridge_port(port_dev) || netif_is_lag_port(port_dev))
2804 return 0;
2805
2806 return mlxsw_sp_inetaddr_vport_event(port_dev, port_dev, event, 1);
2807}
2808
2809static int __mlxsw_sp_inetaddr_lag_event(struct net_device *l3_dev,
2810 struct net_device *lag_dev,
2811 unsigned long event, u16 vid)
2812{
2813 struct net_device *port_dev;
2814 struct list_head *iter;
2815 int err;
2816
2817 netdev_for_each_lower_dev(lag_dev, port_dev, iter) {
2818 if (mlxsw_sp_port_dev_check(port_dev)) {
2819 err = mlxsw_sp_inetaddr_vport_event(l3_dev, port_dev,
2820 event, vid);
2821 if (err)
2822 return err;
2823 }
2824 }
2825
2826 return 0;
2827}
2828
2829static int mlxsw_sp_inetaddr_lag_event(struct net_device *lag_dev,
2830 unsigned long event)
2831{
2832 if (netif_is_bridge_port(lag_dev))
2833 return 0;
2834
2835 return __mlxsw_sp_inetaddr_lag_event(lag_dev, lag_dev, event, 1);
2836}
2837
Ido Schimmel99f44bb2016-07-04 08:23:17 +02002838static struct mlxsw_sp_fid *mlxsw_sp_bridge_fid_get(struct mlxsw_sp *mlxsw_sp,
2839 struct net_device *l3_dev)
2840{
2841 u16 fid;
2842
2843 if (is_vlan_dev(l3_dev))
2844 fid = vlan_dev_vlan_id(l3_dev);
2845 else if (mlxsw_sp->master_bridge.dev == l3_dev)
2846 fid = 1;
2847 else
2848 return mlxsw_sp_vfid_find(mlxsw_sp, l3_dev);
2849
2850 return mlxsw_sp_fid_find(mlxsw_sp, fid);
2851}
2852
2853static enum mlxsw_reg_ritr_if_type mlxsw_sp_rif_type_get(u16 fid)
2854{
2855 if (mlxsw_sp_fid_is_vfid(fid))
2856 return MLXSW_REG_RITR_FID_IF;
2857 else
2858 return MLXSW_REG_RITR_VLAN_IF;
2859}
2860
2861static int mlxsw_sp_rif_bridge_op(struct mlxsw_sp *mlxsw_sp,
2862 struct net_device *l3_dev,
2863 u16 fid, u16 rif,
2864 bool create)
2865{
2866 enum mlxsw_reg_ritr_if_type rif_type;
2867 char ritr_pl[MLXSW_REG_RITR_LEN];
2868
2869 rif_type = mlxsw_sp_rif_type_get(fid);
2870 mlxsw_reg_ritr_pack(ritr_pl, create, rif_type, rif, l3_dev->mtu,
2871 l3_dev->dev_addr);
2872 mlxsw_reg_ritr_fid_set(ritr_pl, rif_type, fid);
2873
2874 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ritr), ritr_pl);
2875}
2876
2877static int mlxsw_sp_rif_bridge_create(struct mlxsw_sp *mlxsw_sp,
2878 struct net_device *l3_dev,
2879 struct mlxsw_sp_fid *f)
2880{
2881 struct mlxsw_sp_rif *r;
2882 u16 rif;
2883 int err;
2884
2885 rif = mlxsw_sp_avail_rif_get(mlxsw_sp);
2886 if (rif == MLXSW_SP_RIF_MAX)
2887 return -ERANGE;
2888
2889 err = mlxsw_sp_rif_bridge_op(mlxsw_sp, l3_dev, f->fid, rif, true);
2890 if (err)
2891 return err;
2892
2893 err = mlxsw_sp_rif_fdb_op(mlxsw_sp, l3_dev->dev_addr, f->fid, true);
2894 if (err)
2895 goto err_rif_fdb_op;
2896
2897 r = mlxsw_sp_rif_alloc(rif, l3_dev, f);
2898 if (!r) {
2899 err = -ENOMEM;
2900 goto err_rif_alloc;
2901 }
2902
2903 f->r = r;
2904 mlxsw_sp->rifs[rif] = r;
2905
2906 netdev_dbg(l3_dev, "RIF=%d created\n", rif);
2907
2908 return 0;
2909
2910err_rif_alloc:
2911 mlxsw_sp_rif_fdb_op(mlxsw_sp, l3_dev->dev_addr, f->fid, false);
2912err_rif_fdb_op:
2913 mlxsw_sp_rif_bridge_op(mlxsw_sp, l3_dev, f->fid, rif, false);
2914 return err;
2915}
2916
2917void mlxsw_sp_rif_bridge_destroy(struct mlxsw_sp *mlxsw_sp,
2918 struct mlxsw_sp_rif *r)
2919{
2920 struct net_device *l3_dev = r->dev;
2921 struct mlxsw_sp_fid *f = r->f;
2922 u16 rif = r->rif;
2923
2924 mlxsw_sp->rifs[rif] = NULL;
2925 f->r = NULL;
2926
2927 kfree(r);
2928
2929 mlxsw_sp_rif_fdb_op(mlxsw_sp, l3_dev->dev_addr, f->fid, false);
2930
2931 mlxsw_sp_rif_bridge_op(mlxsw_sp, l3_dev, f->fid, rif, false);
2932
2933 netdev_dbg(l3_dev, "RIF=%d destroyed\n", rif);
2934}
2935
2936static int mlxsw_sp_inetaddr_bridge_event(struct net_device *l3_dev,
2937 struct net_device *br_dev,
2938 unsigned long event)
2939{
2940 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(l3_dev);
2941 struct mlxsw_sp_fid *f;
2942
2943 /* FID can either be an actual FID if the L3 device is the
2944 * VLAN-aware bridge or a VLAN device on top. Otherwise, the
2945 * L3 device is a VLAN-unaware bridge and we get a vFID.
2946 */
2947 f = mlxsw_sp_bridge_fid_get(mlxsw_sp, l3_dev);
2948 if (WARN_ON(!f))
2949 return -EINVAL;
2950
2951 switch (event) {
2952 case NETDEV_UP:
2953 return mlxsw_sp_rif_bridge_create(mlxsw_sp, l3_dev, f);
2954 case NETDEV_DOWN:
2955 mlxsw_sp_rif_bridge_destroy(mlxsw_sp, f->r);
2956 break;
2957 }
2958
2959 return 0;
2960}
2961
Ido Schimmel99724c12016-07-04 08:23:14 +02002962static int mlxsw_sp_inetaddr_vlan_event(struct net_device *vlan_dev,
2963 unsigned long event)
2964{
2965 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
Ido Schimmel99f44bb2016-07-04 08:23:17 +02002966 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(vlan_dev);
Ido Schimmel99724c12016-07-04 08:23:14 +02002967 u16 vid = vlan_dev_vlan_id(vlan_dev);
2968
2969 if (mlxsw_sp_port_dev_check(real_dev))
2970 return mlxsw_sp_inetaddr_vport_event(vlan_dev, real_dev, event,
2971 vid);
2972 else if (netif_is_lag_master(real_dev))
2973 return __mlxsw_sp_inetaddr_lag_event(vlan_dev, real_dev, event,
2974 vid);
Ido Schimmel99f44bb2016-07-04 08:23:17 +02002975 else if (netif_is_bridge_master(real_dev) &&
2976 mlxsw_sp->master_bridge.dev == real_dev)
2977 return mlxsw_sp_inetaddr_bridge_event(vlan_dev, real_dev,
2978 event);
Ido Schimmel99724c12016-07-04 08:23:14 +02002979
2980 return 0;
2981}
2982
2983static int mlxsw_sp_inetaddr_event(struct notifier_block *unused,
2984 unsigned long event, void *ptr)
2985{
2986 struct in_ifaddr *ifa = (struct in_ifaddr *) ptr;
2987 struct net_device *dev = ifa->ifa_dev->dev;
2988 struct mlxsw_sp *mlxsw_sp;
2989 struct mlxsw_sp_rif *r;
2990 int err = 0;
2991
2992 mlxsw_sp = mlxsw_sp_lower_get(dev);
2993 if (!mlxsw_sp)
2994 goto out;
2995
2996 r = mlxsw_sp_rif_find_by_dev(mlxsw_sp, dev);
2997 if (!mlxsw_sp_rif_should_config(r, event))
2998 goto out;
2999
3000 if (mlxsw_sp_port_dev_check(dev))
3001 err = mlxsw_sp_inetaddr_port_event(dev, event);
3002 else if (netif_is_lag_master(dev))
3003 err = mlxsw_sp_inetaddr_lag_event(dev, event);
Ido Schimmel99f44bb2016-07-04 08:23:17 +02003004 else if (netif_is_bridge_master(dev))
3005 err = mlxsw_sp_inetaddr_bridge_event(dev, dev, event);
Ido Schimmel99724c12016-07-04 08:23:14 +02003006 else if (is_vlan_dev(dev))
3007 err = mlxsw_sp_inetaddr_vlan_event(dev, event);
3008
3009out:
3010 return notifier_from_errno(err);
3011}
3012
Ido Schimmel6e095fd2016-07-04 08:23:13 +02003013static int mlxsw_sp_rif_edit(struct mlxsw_sp *mlxsw_sp, u16 rif,
3014 const char *mac, int mtu)
3015{
3016 char ritr_pl[MLXSW_REG_RITR_LEN];
3017 int err;
3018
3019 mlxsw_reg_ritr_rif_pack(ritr_pl, rif);
3020 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ritr), ritr_pl);
3021 if (err)
3022 return err;
3023
3024 mlxsw_reg_ritr_mtu_set(ritr_pl, mtu);
3025 mlxsw_reg_ritr_if_mac_memcpy_to(ritr_pl, mac);
3026 mlxsw_reg_ritr_op_set(ritr_pl, MLXSW_REG_RITR_RIF_CREATE);
3027 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ritr), ritr_pl);
3028}
3029
3030static int mlxsw_sp_netdevice_router_port_event(struct net_device *dev)
3031{
3032 struct mlxsw_sp *mlxsw_sp;
3033 struct mlxsw_sp_rif *r;
3034 int err;
3035
3036 mlxsw_sp = mlxsw_sp_lower_get(dev);
3037 if (!mlxsw_sp)
3038 return 0;
3039
3040 r = mlxsw_sp_rif_find_by_dev(mlxsw_sp, dev);
3041 if (!r)
3042 return 0;
3043
3044 err = mlxsw_sp_rif_fdb_op(mlxsw_sp, r->addr, r->f->fid, false);
3045 if (err)
3046 return err;
3047
3048 err = mlxsw_sp_rif_edit(mlxsw_sp, r->rif, dev->dev_addr, dev->mtu);
3049 if (err)
3050 goto err_rif_edit;
3051
3052 err = mlxsw_sp_rif_fdb_op(mlxsw_sp, dev->dev_addr, r->f->fid, true);
3053 if (err)
3054 goto err_rif_fdb_op;
3055
3056 ether_addr_copy(r->addr, dev->dev_addr);
3057 r->mtu = dev->mtu;
3058
3059 netdev_dbg(dev, "Updated RIF=%d\n", r->rif);
3060
3061 return 0;
3062
3063err_rif_fdb_op:
3064 mlxsw_sp_rif_edit(mlxsw_sp, r->rif, r->addr, r->mtu);
3065err_rif_edit:
3066 mlxsw_sp_rif_fdb_op(mlxsw_sp, r->addr, r->f->fid, true);
3067 return err;
3068}
3069
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003070static bool mlxsw_sp_lag_port_fid_member(struct mlxsw_sp_port *lag_port,
3071 u16 fid)
3072{
3073 if (mlxsw_sp_fid_is_vfid(fid))
3074 return mlxsw_sp_port_vport_find_by_fid(lag_port, fid);
3075 else
3076 return test_bit(fid, lag_port->active_vlans);
3077}
3078
3079static bool mlxsw_sp_port_fdb_should_flush(struct mlxsw_sp_port *mlxsw_sp_port,
3080 u16 fid)
Ido Schimmel039c49a2016-01-27 15:20:18 +01003081{
3082 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003083 u8 local_port = mlxsw_sp_port->local_port;
3084 u16 lag_id = mlxsw_sp_port->lag_id;
3085 int i, count = 0;
Ido Schimmel039c49a2016-01-27 15:20:18 +01003086
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003087 if (!mlxsw_sp_port->lagged)
3088 return true;
Ido Schimmel039c49a2016-01-27 15:20:18 +01003089
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003090 for (i = 0; i < MLXSW_SP_PORT_PER_LAG_MAX; i++) {
3091 struct mlxsw_sp_port *lag_port;
3092
3093 lag_port = mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i);
3094 if (!lag_port || lag_port->local_port == local_port)
3095 continue;
3096 if (mlxsw_sp_lag_port_fid_member(lag_port, fid))
3097 count++;
3098 }
3099
3100 return !count;
Ido Schimmel039c49a2016-01-27 15:20:18 +01003101}
3102
3103static int
3104mlxsw_sp_port_fdb_flush_by_port_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
3105 u16 fid)
3106{
3107 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3108 char sfdf_pl[MLXSW_REG_SFDF_LEN];
3109
3110 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID);
3111 mlxsw_reg_sfdf_fid_set(sfdf_pl, fid);
3112 mlxsw_reg_sfdf_port_fid_system_port_set(sfdf_pl,
3113 mlxsw_sp_port->local_port);
3114
Ido Schimmel22305372016-06-20 23:04:21 +02003115 netdev_dbg(mlxsw_sp_port->dev, "FDB flushed using Port=%d, FID=%d\n",
3116 mlxsw_sp_port->local_port, fid);
3117
Ido Schimmel039c49a2016-01-27 15:20:18 +01003118 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
3119}
3120
3121static int
Ido Schimmel039c49a2016-01-27 15:20:18 +01003122mlxsw_sp_port_fdb_flush_by_lag_id_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
3123 u16 fid)
3124{
3125 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3126 char sfdf_pl[MLXSW_REG_SFDF_LEN];
3127
3128 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID);
3129 mlxsw_reg_sfdf_fid_set(sfdf_pl, fid);
3130 mlxsw_reg_sfdf_lag_fid_lag_id_set(sfdf_pl, mlxsw_sp_port->lag_id);
3131
Ido Schimmel22305372016-06-20 23:04:21 +02003132 netdev_dbg(mlxsw_sp_port->dev, "FDB flushed using LAG ID=%d, FID=%d\n",
3133 mlxsw_sp_port->lag_id, fid);
3134
Ido Schimmel039c49a2016-01-27 15:20:18 +01003135 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
3136}
3137
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003138int mlxsw_sp_port_fdb_flush(struct mlxsw_sp_port *mlxsw_sp_port, u16 fid)
Ido Schimmel039c49a2016-01-27 15:20:18 +01003139{
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003140 if (!mlxsw_sp_port_fdb_should_flush(mlxsw_sp_port, fid))
3141 return 0;
Ido Schimmel039c49a2016-01-27 15:20:18 +01003142
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003143 if (mlxsw_sp_port->lagged)
3144 return mlxsw_sp_port_fdb_flush_by_lag_id_fid(mlxsw_sp_port,
Ido Schimmel039c49a2016-01-27 15:20:18 +01003145 fid);
3146 else
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003147 return mlxsw_sp_port_fdb_flush_by_port_fid(mlxsw_sp_port, fid);
Ido Schimmel039c49a2016-01-27 15:20:18 +01003148}
3149
Ido Schimmel701b1862016-07-04 08:23:16 +02003150static void mlxsw_sp_master_bridge_gone_sync(struct mlxsw_sp *mlxsw_sp)
3151{
3152 struct mlxsw_sp_fid *f, *tmp;
3153
3154 list_for_each_entry_safe(f, tmp, &mlxsw_sp->fids, list)
3155 if (--f->ref_count == 0)
3156 mlxsw_sp_fid_destroy(mlxsw_sp, f);
3157 else
3158 WARN_ON_ONCE(1);
3159}
3160
Ido Schimmel7117a572016-06-20 23:04:06 +02003161static bool mlxsw_sp_master_bridge_check(struct mlxsw_sp *mlxsw_sp,
3162 struct net_device *br_dev)
3163{
3164 return !mlxsw_sp->master_bridge.dev ||
3165 mlxsw_sp->master_bridge.dev == br_dev;
3166}
3167
3168static void mlxsw_sp_master_bridge_inc(struct mlxsw_sp *mlxsw_sp,
3169 struct net_device *br_dev)
3170{
3171 mlxsw_sp->master_bridge.dev = br_dev;
3172 mlxsw_sp->master_bridge.ref_count++;
3173}
3174
3175static void mlxsw_sp_master_bridge_dec(struct mlxsw_sp *mlxsw_sp)
3176{
Ido Schimmel701b1862016-07-04 08:23:16 +02003177 if (--mlxsw_sp->master_bridge.ref_count == 0) {
Ido Schimmel7117a572016-06-20 23:04:06 +02003178 mlxsw_sp->master_bridge.dev = NULL;
Ido Schimmel701b1862016-07-04 08:23:16 +02003179 /* It's possible upper VLAN devices are still holding
3180 * references to underlying FIDs. Drop the reference
3181 * and release the resources if it was the last one.
3182 * If it wasn't, then something bad happened.
3183 */
3184 mlxsw_sp_master_bridge_gone_sync(mlxsw_sp);
3185 }
Ido Schimmel7117a572016-06-20 23:04:06 +02003186}
3187
3188static int mlxsw_sp_port_bridge_join(struct mlxsw_sp_port *mlxsw_sp_port,
3189 struct net_device *br_dev)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003190{
3191 struct net_device *dev = mlxsw_sp_port->dev;
3192 int err;
3193
3194 /* When port is not bridged untagged packets are tagged with
3195 * PVID=VID=1, thereby creating an implicit VLAN interface in
3196 * the device. Remove it and let bridge code take care of its
3197 * own VLANs.
3198 */
3199 err = mlxsw_sp_port_kill_vid(dev, 0, 1);
Ido Schimmel6c72a3d2016-01-04 10:42:26 +01003200 if (err)
3201 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003202
Ido Schimmel7117a572016-06-20 23:04:06 +02003203 mlxsw_sp_master_bridge_inc(mlxsw_sp_port->mlxsw_sp, br_dev);
3204
Ido Schimmel6c72a3d2016-01-04 10:42:26 +01003205 mlxsw_sp_port->learning = 1;
3206 mlxsw_sp_port->learning_sync = 1;
3207 mlxsw_sp_port->uc_flood = 1;
3208 mlxsw_sp_port->bridged = 1;
3209
3210 return 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003211}
3212
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003213static void mlxsw_sp_port_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003214{
3215 struct net_device *dev = mlxsw_sp_port->dev;
Ido Schimmel5a8f4522016-01-04 10:42:25 +01003216
Ido Schimmel28a01d22016-02-18 11:30:02 +01003217 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1);
3218
Ido Schimmel7117a572016-06-20 23:04:06 +02003219 mlxsw_sp_master_bridge_dec(mlxsw_sp_port->mlxsw_sp);
3220
Ido Schimmel6c72a3d2016-01-04 10:42:26 +01003221 mlxsw_sp_port->learning = 0;
3222 mlxsw_sp_port->learning_sync = 0;
3223 mlxsw_sp_port->uc_flood = 0;
Ido Schimmel5a8f4522016-01-04 10:42:25 +01003224 mlxsw_sp_port->bridged = 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003225
3226 /* Add implicit VLAN interface in the device, so that untagged
3227 * packets will be classified to the default vFID.
3228 */
Ido Schimmel82e6db02016-06-20 23:04:04 +02003229 mlxsw_sp_port_add_vid(dev, 0, 1);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003230}
3231
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003232static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003233{
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003234 char sldr_pl[MLXSW_REG_SLDR_LEN];
3235
3236 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
3237 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
3238}
3239
3240static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
3241{
3242 char sldr_pl[MLXSW_REG_SLDR_LEN];
3243
3244 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
3245 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
3246}
3247
3248static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
3249 u16 lag_id, u8 port_index)
3250{
3251 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3252 char slcor_pl[MLXSW_REG_SLCOR_LEN];
3253
3254 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
3255 lag_id, port_index);
3256 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
3257}
3258
3259static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
3260 u16 lag_id)
3261{
3262 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3263 char slcor_pl[MLXSW_REG_SLCOR_LEN];
3264
3265 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
3266 lag_id);
3267 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
3268}
3269
3270static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
3271 u16 lag_id)
3272{
3273 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3274 char slcor_pl[MLXSW_REG_SLCOR_LEN];
3275
3276 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
3277 lag_id);
3278 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
3279}
3280
3281static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
3282 u16 lag_id)
3283{
3284 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3285 char slcor_pl[MLXSW_REG_SLCOR_LEN];
3286
3287 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
3288 lag_id);
3289 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
3290}
3291
3292static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
3293 struct net_device *lag_dev,
3294 u16 *p_lag_id)
3295{
3296 struct mlxsw_sp_upper *lag;
3297 int free_lag_id = -1;
3298 int i;
3299
3300 for (i = 0; i < MLXSW_SP_LAG_MAX; i++) {
3301 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
3302 if (lag->ref_count) {
3303 if (lag->dev == lag_dev) {
3304 *p_lag_id = i;
3305 return 0;
3306 }
3307 } else if (free_lag_id < 0) {
3308 free_lag_id = i;
3309 }
3310 }
3311 if (free_lag_id < 0)
3312 return -EBUSY;
3313 *p_lag_id = free_lag_id;
3314 return 0;
3315}
3316
3317static bool
3318mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
3319 struct net_device *lag_dev,
3320 struct netdev_lag_upper_info *lag_upper_info)
3321{
3322 u16 lag_id;
3323
3324 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0)
3325 return false;
3326 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
3327 return false;
3328 return true;
3329}
3330
3331static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
3332 u16 lag_id, u8 *p_port_index)
3333{
3334 int i;
3335
3336 for (i = 0; i < MLXSW_SP_PORT_PER_LAG_MAX; i++) {
3337 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
3338 *p_port_index = i;
3339 return 0;
3340 }
3341 }
3342 return -EBUSY;
3343}
3344
Ido Schimmel86bf95b2016-07-02 11:00:11 +02003345static void
3346mlxsw_sp_port_pvid_vport_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
3347 u16 lag_id)
3348{
3349 struct mlxsw_sp_port *mlxsw_sp_vport;
Ido Schimmel11943ff2016-07-02 11:00:12 +02003350 struct mlxsw_sp_fid *f;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02003351
3352 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, 1);
3353 if (WARN_ON(!mlxsw_sp_vport))
3354 return;
3355
Ido Schimmel11943ff2016-07-02 11:00:12 +02003356 /* If vPort is assigned a RIF, then leave it since it's no
3357 * longer valid.
3358 */
3359 f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
3360 if (f)
3361 f->leave(mlxsw_sp_vport);
3362
Ido Schimmel86bf95b2016-07-02 11:00:11 +02003363 mlxsw_sp_vport->lag_id = lag_id;
3364 mlxsw_sp_vport->lagged = 1;
3365}
3366
3367static void
3368mlxsw_sp_port_pvid_vport_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port)
3369{
3370 struct mlxsw_sp_port *mlxsw_sp_vport;
Ido Schimmel11943ff2016-07-02 11:00:12 +02003371 struct mlxsw_sp_fid *f;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02003372
3373 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, 1);
3374 if (WARN_ON(!mlxsw_sp_vport))
3375 return;
3376
Ido Schimmel11943ff2016-07-02 11:00:12 +02003377 f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
3378 if (f)
3379 f->leave(mlxsw_sp_vport);
3380
Ido Schimmel86bf95b2016-07-02 11:00:11 +02003381 mlxsw_sp_vport->lagged = 0;
3382}
3383
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003384static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
3385 struct net_device *lag_dev)
3386{
3387 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3388 struct mlxsw_sp_upper *lag;
3389 u16 lag_id;
3390 u8 port_index;
3391 int err;
3392
3393 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
3394 if (err)
3395 return err;
3396 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
3397 if (!lag->ref_count) {
3398 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
3399 if (err)
3400 return err;
3401 lag->dev = lag_dev;
3402 }
3403
3404 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
3405 if (err)
3406 return err;
3407 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
3408 if (err)
3409 goto err_col_port_add;
3410 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id);
3411 if (err)
3412 goto err_col_port_enable;
3413
3414 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
3415 mlxsw_sp_port->local_port);
3416 mlxsw_sp_port->lag_id = lag_id;
3417 mlxsw_sp_port->lagged = 1;
3418 lag->ref_count++;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02003419
3420 mlxsw_sp_port_pvid_vport_lag_join(mlxsw_sp_port, lag_id);
3421
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003422 return 0;
3423
Ido Schimmel51554db2016-05-06 22:18:39 +02003424err_col_port_enable:
3425 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003426err_col_port_add:
3427 if (!lag->ref_count)
3428 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003429 return err;
3430}
3431
Ido Schimmel82e6db02016-06-20 23:04:04 +02003432static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
3433 struct net_device *lag_dev)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003434{
3435 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003436 u16 lag_id = mlxsw_sp_port->lag_id;
Ido Schimmel1c800752016-06-20 23:04:20 +02003437 struct mlxsw_sp_upper *lag;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003438
3439 if (!mlxsw_sp_port->lagged)
Ido Schimmel82e6db02016-06-20 23:04:04 +02003440 return;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003441 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
3442 WARN_ON(lag->ref_count == 0);
3443
Ido Schimmel82e6db02016-06-20 23:04:04 +02003444 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id);
3445 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003446
Ido Schimmel4dc236c2016-01-27 15:20:16 +01003447 if (mlxsw_sp_port->bridged) {
3448 mlxsw_sp_port_active_vlans_del(mlxsw_sp_port);
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003449 mlxsw_sp_port_bridge_leave(mlxsw_sp_port);
Ido Schimmel4dc236c2016-01-27 15:20:16 +01003450 }
3451
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003452 if (lag->ref_count == 1)
Ido Schimmel82e6db02016-06-20 23:04:04 +02003453 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003454
3455 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
3456 mlxsw_sp_port->local_port);
3457 mlxsw_sp_port->lagged = 0;
3458 lag->ref_count--;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02003459
3460 mlxsw_sp_port_pvid_vport_lag_leave(mlxsw_sp_port);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003461}
3462
Jiri Pirko74581202015-12-03 12:12:30 +01003463static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
3464 u16 lag_id)
3465{
3466 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3467 char sldr_pl[MLXSW_REG_SLDR_LEN];
3468
3469 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
3470 mlxsw_sp_port->local_port);
3471 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
3472}
3473
3474static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
3475 u16 lag_id)
3476{
3477 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3478 char sldr_pl[MLXSW_REG_SLDR_LEN];
3479
3480 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
3481 mlxsw_sp_port->local_port);
3482 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
3483}
3484
3485static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port,
3486 bool lag_tx_enabled)
3487{
3488 if (lag_tx_enabled)
3489 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port,
3490 mlxsw_sp_port->lag_id);
3491 else
3492 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
3493 mlxsw_sp_port->lag_id);
3494}
3495
3496static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
3497 struct netdev_lag_lower_state_info *info)
3498{
3499 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled);
3500}
3501
Ido Schimmel9589a7b52015-12-15 16:03:43 +01003502static int mlxsw_sp_port_vlan_link(struct mlxsw_sp_port *mlxsw_sp_port,
3503 struct net_device *vlan_dev)
3504{
3505 struct mlxsw_sp_port *mlxsw_sp_vport;
3506 u16 vid = vlan_dev_vlan_id(vlan_dev);
3507
3508 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
Ido Schimmel423b9372016-06-20 23:04:03 +02003509 if (WARN_ON(!mlxsw_sp_vport))
Ido Schimmel9589a7b52015-12-15 16:03:43 +01003510 return -EINVAL;
Ido Schimmel9589a7b52015-12-15 16:03:43 +01003511
3512 mlxsw_sp_vport->dev = vlan_dev;
3513
3514 return 0;
3515}
3516
Ido Schimmel82e6db02016-06-20 23:04:04 +02003517static void mlxsw_sp_port_vlan_unlink(struct mlxsw_sp_port *mlxsw_sp_port,
3518 struct net_device *vlan_dev)
Ido Schimmel9589a7b52015-12-15 16:03:43 +01003519{
3520 struct mlxsw_sp_port *mlxsw_sp_vport;
3521 u16 vid = vlan_dev_vlan_id(vlan_dev);
3522
3523 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
Ido Schimmel423b9372016-06-20 23:04:03 +02003524 if (WARN_ON(!mlxsw_sp_vport))
Ido Schimmel82e6db02016-06-20 23:04:04 +02003525 return;
Ido Schimmel9589a7b52015-12-15 16:03:43 +01003526
3527 mlxsw_sp_vport->dev = mlxsw_sp_port->dev;
Ido Schimmel9589a7b52015-12-15 16:03:43 +01003528}
3529
Jiri Pirko74581202015-12-03 12:12:30 +01003530static int mlxsw_sp_netdevice_port_upper_event(struct net_device *dev,
3531 unsigned long event, void *ptr)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003532{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003533 struct netdev_notifier_changeupper_info *info;
3534 struct mlxsw_sp_port *mlxsw_sp_port;
3535 struct net_device *upper_dev;
3536 struct mlxsw_sp *mlxsw_sp;
Ido Schimmel80bedf12016-06-20 23:03:59 +02003537 int err = 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003538
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003539 mlxsw_sp_port = netdev_priv(dev);
3540 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3541 info = ptr;
3542
3543 switch (event) {
3544 case NETDEV_PRECHANGEUPPER:
3545 upper_dev = info->upper_dev;
Ido Schimmel59fe9b32016-06-20 23:04:00 +02003546 if (!is_vlan_dev(upper_dev) &&
3547 !netif_is_lag_master(upper_dev) &&
3548 !netif_is_bridge_master(upper_dev))
3549 return -EINVAL;
Ido Schimmel6ec43902016-06-20 23:04:01 +02003550 if (!info->linking)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003551 break;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003552 /* HW limitation forbids to put ports to multiple bridges. */
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003553 if (netif_is_bridge_master(upper_dev) &&
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003554 !mlxsw_sp_master_bridge_check(mlxsw_sp, upper_dev))
Ido Schimmel80bedf12016-06-20 23:03:59 +02003555 return -EINVAL;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003556 if (netif_is_lag_master(upper_dev) &&
3557 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
3558 info->upper_info))
Ido Schimmel80bedf12016-06-20 23:03:59 +02003559 return -EINVAL;
Ido Schimmel6ec43902016-06-20 23:04:01 +02003560 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev))
3561 return -EINVAL;
3562 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
3563 !netif_is_lag_master(vlan_dev_real_dev(upper_dev)))
3564 return -EINVAL;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003565 break;
3566 case NETDEV_CHANGEUPPER:
3567 upper_dev = info->upper_dev;
Ido Schimmel9589a7b52015-12-15 16:03:43 +01003568 if (is_vlan_dev(upper_dev)) {
Ido Schimmel80bedf12016-06-20 23:03:59 +02003569 if (info->linking)
Ido Schimmel9589a7b52015-12-15 16:03:43 +01003570 err = mlxsw_sp_port_vlan_link(mlxsw_sp_port,
3571 upper_dev);
Ido Schimmel80bedf12016-06-20 23:03:59 +02003572 else
Ido Schimmel82e6db02016-06-20 23:04:04 +02003573 mlxsw_sp_port_vlan_unlink(mlxsw_sp_port,
3574 upper_dev);
Ido Schimmel9589a7b52015-12-15 16:03:43 +01003575 } else if (netif_is_bridge_master(upper_dev)) {
Ido Schimmel7117a572016-06-20 23:04:06 +02003576 if (info->linking)
3577 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
3578 upper_dev);
3579 else
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003580 mlxsw_sp_port_bridge_leave(mlxsw_sp_port);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003581 } else if (netif_is_lag_master(upper_dev)) {
Ido Schimmel80bedf12016-06-20 23:03:59 +02003582 if (info->linking)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003583 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
3584 upper_dev);
Ido Schimmel80bedf12016-06-20 23:03:59 +02003585 else
Ido Schimmel82e6db02016-06-20 23:04:04 +02003586 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
3587 upper_dev);
Ido Schimmel59fe9b32016-06-20 23:04:00 +02003588 } else {
3589 err = -EINVAL;
3590 WARN_ON(1);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003591 }
3592 break;
3593 }
3594
Ido Schimmel80bedf12016-06-20 23:03:59 +02003595 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003596}
3597
Jiri Pirko74581202015-12-03 12:12:30 +01003598static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
3599 unsigned long event, void *ptr)
3600{
3601 struct netdev_notifier_changelowerstate_info *info;
3602 struct mlxsw_sp_port *mlxsw_sp_port;
3603 int err;
3604
3605 mlxsw_sp_port = netdev_priv(dev);
3606 info = ptr;
3607
3608 switch (event) {
3609 case NETDEV_CHANGELOWERSTATE:
3610 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
3611 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
3612 info->lower_state_info);
3613 if (err)
3614 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
3615 }
3616 break;
3617 }
3618
Ido Schimmel80bedf12016-06-20 23:03:59 +02003619 return 0;
Jiri Pirko74581202015-12-03 12:12:30 +01003620}
3621
3622static int mlxsw_sp_netdevice_port_event(struct net_device *dev,
3623 unsigned long event, void *ptr)
3624{
3625 switch (event) {
3626 case NETDEV_PRECHANGEUPPER:
3627 case NETDEV_CHANGEUPPER:
3628 return mlxsw_sp_netdevice_port_upper_event(dev, event, ptr);
3629 case NETDEV_CHANGELOWERSTATE:
3630 return mlxsw_sp_netdevice_port_lower_event(dev, event, ptr);
3631 }
3632
Ido Schimmel80bedf12016-06-20 23:03:59 +02003633 return 0;
Jiri Pirko74581202015-12-03 12:12:30 +01003634}
3635
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003636static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
3637 unsigned long event, void *ptr)
3638{
3639 struct net_device *dev;
3640 struct list_head *iter;
3641 int ret;
3642
3643 netdev_for_each_lower_dev(lag_dev, dev, iter) {
3644 if (mlxsw_sp_port_dev_check(dev)) {
3645 ret = mlxsw_sp_netdevice_port_event(dev, event, ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02003646 if (ret)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003647 return ret;
3648 }
3649 }
3650
Ido Schimmel80bedf12016-06-20 23:03:59 +02003651 return 0;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003652}
3653
Ido Schimmel701b1862016-07-04 08:23:16 +02003654static int mlxsw_sp_master_bridge_vlan_link(struct mlxsw_sp *mlxsw_sp,
3655 struct net_device *vlan_dev)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003656{
Ido Schimmel701b1862016-07-04 08:23:16 +02003657 u16 fid = vlan_dev_vlan_id(vlan_dev);
Ido Schimmeld0ec8752016-06-20 23:04:12 +02003658 struct mlxsw_sp_fid *f;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003659
Ido Schimmel701b1862016-07-04 08:23:16 +02003660 f = mlxsw_sp_fid_find(mlxsw_sp, fid);
3661 if (!f) {
3662 f = mlxsw_sp_fid_create(mlxsw_sp, fid);
3663 if (IS_ERR(f))
3664 return PTR_ERR(f);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003665 }
3666
Ido Schimmel701b1862016-07-04 08:23:16 +02003667 f->ref_count++;
3668
3669 return 0;
3670}
3671
3672static void mlxsw_sp_master_bridge_vlan_unlink(struct mlxsw_sp *mlxsw_sp,
3673 struct net_device *vlan_dev)
3674{
3675 u16 fid = vlan_dev_vlan_id(vlan_dev);
3676 struct mlxsw_sp_fid *f;
3677
3678 f = mlxsw_sp_fid_find(mlxsw_sp, fid);
Ido Schimmel99f44bb2016-07-04 08:23:17 +02003679 if (f && f->r)
3680 mlxsw_sp_rif_bridge_destroy(mlxsw_sp, f->r);
Ido Schimmel701b1862016-07-04 08:23:16 +02003681 if (f && --f->ref_count == 0)
3682 mlxsw_sp_fid_destroy(mlxsw_sp, f);
3683}
3684
3685static int mlxsw_sp_netdevice_bridge_event(struct net_device *br_dev,
3686 unsigned long event, void *ptr)
3687{
3688 struct netdev_notifier_changeupper_info *info;
3689 struct net_device *upper_dev;
3690 struct mlxsw_sp *mlxsw_sp;
3691 int err;
3692
3693 mlxsw_sp = mlxsw_sp_lower_get(br_dev);
3694 if (!mlxsw_sp)
3695 return 0;
3696 if (br_dev != mlxsw_sp->master_bridge.dev)
3697 return 0;
3698
3699 info = ptr;
3700
3701 switch (event) {
3702 case NETDEV_CHANGEUPPER:
3703 upper_dev = info->upper_dev;
3704 if (!is_vlan_dev(upper_dev))
3705 break;
3706 if (info->linking) {
3707 err = mlxsw_sp_master_bridge_vlan_link(mlxsw_sp,
3708 upper_dev);
3709 if (err)
3710 return err;
3711 } else {
3712 mlxsw_sp_master_bridge_vlan_unlink(mlxsw_sp, upper_dev);
3713 }
3714 break;
3715 }
3716
3717 return 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003718}
3719
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02003720static u16 mlxsw_sp_avail_vfid_get(const struct mlxsw_sp *mlxsw_sp)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003721{
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02003722 return find_first_zero_bit(mlxsw_sp->vfids.mapped,
Ido Schimmel99724c12016-07-04 08:23:14 +02003723 MLXSW_SP_VFID_MAX);
3724}
3725
3726static int mlxsw_sp_vfid_op(struct mlxsw_sp *mlxsw_sp, u16 fid, bool create)
3727{
3728 char sfmr_pl[MLXSW_REG_SFMR_LEN];
3729
3730 mlxsw_reg_sfmr_pack(sfmr_pl, !create, fid, 0);
3731 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfmr), sfmr_pl);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003732}
3733
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02003734static void mlxsw_sp_vport_vfid_leave(struct mlxsw_sp_port *mlxsw_sp_vport);
Ido Schimmel1c800752016-06-20 23:04:20 +02003735
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02003736static struct mlxsw_sp_fid *mlxsw_sp_vfid_create(struct mlxsw_sp *mlxsw_sp,
3737 struct net_device *br_dev)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003738{
3739 struct device *dev = mlxsw_sp->bus_info->dev;
Ido Schimmeld0ec8752016-06-20 23:04:12 +02003740 struct mlxsw_sp_fid *f;
Ido Schimmelc7e920b2016-06-20 23:04:09 +02003741 u16 vfid, fid;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003742 int err;
3743
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02003744 vfid = mlxsw_sp_avail_vfid_get(mlxsw_sp);
Ido Schimmelc7e920b2016-06-20 23:04:09 +02003745 if (vfid == MLXSW_SP_VFID_MAX) {
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003746 dev_err(dev, "No available vFIDs\n");
3747 return ERR_PTR(-ERANGE);
3748 }
3749
Ido Schimmelc7e920b2016-06-20 23:04:09 +02003750 fid = mlxsw_sp_vfid_to_fid(vfid);
3751 err = mlxsw_sp_vfid_op(mlxsw_sp, fid, true);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003752 if (err) {
Ido Schimmelc7e920b2016-06-20 23:04:09 +02003753 dev_err(dev, "Failed to create FID=%d\n", fid);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003754 return ERR_PTR(err);
3755 }
3756
Ido Schimmelc7e920b2016-06-20 23:04:09 +02003757 f = kzalloc(sizeof(*f), GFP_KERNEL);
3758 if (!f)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003759 goto err_allocate_vfid;
3760
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02003761 f->leave = mlxsw_sp_vport_vfid_leave;
Ido Schimmeld0ec8752016-06-20 23:04:12 +02003762 f->fid = fid;
3763 f->dev = br_dev;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003764
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02003765 list_add(&f->list, &mlxsw_sp->vfids.list);
3766 set_bit(vfid, mlxsw_sp->vfids.mapped);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003767
Ido Schimmelc7e920b2016-06-20 23:04:09 +02003768 return f;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003769
3770err_allocate_vfid:
Ido Schimmelc7e920b2016-06-20 23:04:09 +02003771 mlxsw_sp_vfid_op(mlxsw_sp, fid, false);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003772 return ERR_PTR(-ENOMEM);
3773}
3774
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02003775static void mlxsw_sp_vfid_destroy(struct mlxsw_sp *mlxsw_sp,
3776 struct mlxsw_sp_fid *f)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003777{
Ido Schimmeld0ec8752016-06-20 23:04:12 +02003778 u16 vfid = mlxsw_sp_fid_to_vfid(f->fid);
Ido Schimmel99f44bb2016-07-04 08:23:17 +02003779 u16 fid = f->fid;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003780
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02003781 clear_bit(vfid, mlxsw_sp->vfids.mapped);
Ido Schimmeld0ec8752016-06-20 23:04:12 +02003782 list_del(&f->list);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003783
Ido Schimmel99f44bb2016-07-04 08:23:17 +02003784 if (f->r)
3785 mlxsw_sp_rif_bridge_destroy(mlxsw_sp, f->r);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003786
Ido Schimmeld0ec8752016-06-20 23:04:12 +02003787 kfree(f);
Ido Schimmel99f44bb2016-07-04 08:23:17 +02003788
3789 mlxsw_sp_vfid_op(mlxsw_sp, fid, false);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003790}
3791
Ido Schimmel99724c12016-07-04 08:23:14 +02003792static int mlxsw_sp_vport_fid_map(struct mlxsw_sp_port *mlxsw_sp_vport, u16 fid,
3793 bool valid)
3794{
3795 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
3796 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
3797
3798 return mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport, mt, valid, fid,
3799 vid);
3800}
3801
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02003802static int mlxsw_sp_vport_vfid_join(struct mlxsw_sp_port *mlxsw_sp_vport,
3803 struct net_device *br_dev)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003804{
Ido Schimmel0355b592016-06-20 23:04:13 +02003805 struct mlxsw_sp_fid *f;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003806 int err;
3807
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02003808 f = mlxsw_sp_vfid_find(mlxsw_sp_vport->mlxsw_sp, br_dev);
Ido Schimmel0355b592016-06-20 23:04:13 +02003809 if (!f) {
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02003810 f = mlxsw_sp_vfid_create(mlxsw_sp_vport->mlxsw_sp, br_dev);
Ido Schimmel0355b592016-06-20 23:04:13 +02003811 if (IS_ERR(f))
3812 return PTR_ERR(f);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003813 }
3814
Ido Schimmel0355b592016-06-20 23:04:13 +02003815 err = mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, true);
3816 if (err)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003817 goto err_vport_flood_set;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003818
Ido Schimmel0355b592016-06-20 23:04:13 +02003819 err = mlxsw_sp_vport_fid_map(mlxsw_sp_vport, f->fid, true);
3820 if (err)
3821 goto err_vport_fid_map;
Ido Schimmel6a9863a2016-02-15 13:19:54 +01003822
Ido Schimmel41b996c2016-06-20 23:04:17 +02003823 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, f);
Ido Schimmel0355b592016-06-20 23:04:13 +02003824 f->ref_count++;
Ido Schimmel039c49a2016-01-27 15:20:18 +01003825
Ido Schimmel22305372016-06-20 23:04:21 +02003826 netdev_dbg(mlxsw_sp_vport->dev, "Joined FID=%d\n", f->fid);
3827
Ido Schimmel0355b592016-06-20 23:04:13 +02003828 return 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003829
Ido Schimmel9c4d4422016-06-20 23:04:10 +02003830err_vport_fid_map:
Ido Schimmel0355b592016-06-20 23:04:13 +02003831 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, false);
3832err_vport_flood_set:
3833 if (!f->ref_count)
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02003834 mlxsw_sp_vfid_destroy(mlxsw_sp_vport->mlxsw_sp, f);
Ido Schimmel0355b592016-06-20 23:04:13 +02003835 return err;
3836}
3837
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02003838static void mlxsw_sp_vport_vfid_leave(struct mlxsw_sp_port *mlxsw_sp_vport)
Ido Schimmel0355b592016-06-20 23:04:13 +02003839{
Ido Schimmel41b996c2016-06-20 23:04:17 +02003840 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
Ido Schimmel0355b592016-06-20 23:04:13 +02003841
Ido Schimmel22305372016-06-20 23:04:21 +02003842 netdev_dbg(mlxsw_sp_vport->dev, "Left FID=%d\n", f->fid);
3843
Ido Schimmel0355b592016-06-20 23:04:13 +02003844 mlxsw_sp_vport_fid_map(mlxsw_sp_vport, f->fid, false);
3845
3846 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, false);
3847
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003848 mlxsw_sp_port_fdb_flush(mlxsw_sp_vport, f->fid);
3849
Ido Schimmel41b996c2016-06-20 23:04:17 +02003850 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, NULL);
Ido Schimmel0355b592016-06-20 23:04:13 +02003851 if (--f->ref_count == 0)
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02003852 mlxsw_sp_vfid_destroy(mlxsw_sp_vport->mlxsw_sp, f);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003853}
3854
3855static int mlxsw_sp_vport_bridge_join(struct mlxsw_sp_port *mlxsw_sp_vport,
3856 struct net_device *br_dev)
3857{
Ido Schimmel99724c12016-07-04 08:23:14 +02003858 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003859 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
3860 struct net_device *dev = mlxsw_sp_vport->dev;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003861 int err;
3862
Ido Schimmel99724c12016-07-04 08:23:14 +02003863 if (f && !WARN_ON(!f->leave))
3864 f->leave(mlxsw_sp_vport);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003865
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02003866 err = mlxsw_sp_vport_vfid_join(mlxsw_sp_vport, br_dev);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003867 if (err) {
Ido Schimmel0355b592016-06-20 23:04:13 +02003868 netdev_err(dev, "Failed to join vFID\n");
Ido Schimmel99724c12016-07-04 08:23:14 +02003869 return err;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003870 }
3871
3872 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, true);
3873 if (err) {
3874 netdev_err(dev, "Failed to enable learning\n");
3875 goto err_port_vid_learning_set;
3876 }
3877
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003878 mlxsw_sp_vport->learning = 1;
3879 mlxsw_sp_vport->learning_sync = 1;
3880 mlxsw_sp_vport->uc_flood = 1;
3881 mlxsw_sp_vport->bridged = 1;
3882
3883 return 0;
3884
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003885err_port_vid_learning_set:
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02003886 mlxsw_sp_vport_vfid_leave(mlxsw_sp_vport);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003887 return err;
3888}
3889
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003890static void mlxsw_sp_vport_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_vport)
Ido Schimmel0355b592016-06-20 23:04:13 +02003891{
3892 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
Ido Schimmel0355b592016-06-20 23:04:13 +02003893
3894 mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, false);
3895
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02003896 mlxsw_sp_vport_vfid_leave(mlxsw_sp_vport);
Ido Schimmel0355b592016-06-20 23:04:13 +02003897
Ido Schimmel0355b592016-06-20 23:04:13 +02003898 mlxsw_sp_vport->learning = 0;
3899 mlxsw_sp_vport->learning_sync = 0;
3900 mlxsw_sp_vport->uc_flood = 0;
3901 mlxsw_sp_vport->bridged = 0;
3902}
3903
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003904static bool
3905mlxsw_sp_port_master_bridge_check(const struct mlxsw_sp_port *mlxsw_sp_port,
3906 const struct net_device *br_dev)
3907{
3908 struct mlxsw_sp_port *mlxsw_sp_vport;
3909
3910 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
3911 vport.list) {
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02003912 struct net_device *dev = mlxsw_sp_vport_dev_get(mlxsw_sp_vport);
Ido Schimmel56918b62016-06-20 23:04:18 +02003913
3914 if (dev && dev == br_dev)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003915 return false;
3916 }
3917
3918 return true;
3919}
3920
3921static int mlxsw_sp_netdevice_vport_event(struct net_device *dev,
3922 unsigned long event, void *ptr,
3923 u16 vid)
3924{
3925 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
3926 struct netdev_notifier_changeupper_info *info = ptr;
3927 struct mlxsw_sp_port *mlxsw_sp_vport;
3928 struct net_device *upper_dev;
Ido Schimmel80bedf12016-06-20 23:03:59 +02003929 int err = 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003930
3931 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
3932
3933 switch (event) {
3934 case NETDEV_PRECHANGEUPPER:
3935 upper_dev = info->upper_dev;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003936 if (!netif_is_bridge_master(upper_dev))
Ido Schimmel80bedf12016-06-20 23:03:59 +02003937 return -EINVAL;
Ido Schimmelddbe9932016-06-20 23:04:02 +02003938 if (!info->linking)
3939 break;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003940 /* We can't have multiple VLAN interfaces configured on
3941 * the same port and being members in the same bridge.
3942 */
3943 if (!mlxsw_sp_port_master_bridge_check(mlxsw_sp_port,
3944 upper_dev))
Ido Schimmel80bedf12016-06-20 23:03:59 +02003945 return -EINVAL;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003946 break;
3947 case NETDEV_CHANGEUPPER:
3948 upper_dev = info->upper_dev;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003949 if (info->linking) {
Ido Schimmel423b9372016-06-20 23:04:03 +02003950 if (WARN_ON(!mlxsw_sp_vport))
Ido Schimmel80bedf12016-06-20 23:03:59 +02003951 return -EINVAL;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003952 err = mlxsw_sp_vport_bridge_join(mlxsw_sp_vport,
3953 upper_dev);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003954 } else {
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003955 if (!mlxsw_sp_vport)
Ido Schimmel80bedf12016-06-20 23:03:59 +02003956 return 0;
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003957 mlxsw_sp_vport_bridge_leave(mlxsw_sp_vport);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003958 }
3959 }
3960
Ido Schimmel80bedf12016-06-20 23:03:59 +02003961 return err;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003962}
3963
Ido Schimmel272c4472015-12-15 16:03:47 +01003964static int mlxsw_sp_netdevice_lag_vport_event(struct net_device *lag_dev,
3965 unsigned long event, void *ptr,
3966 u16 vid)
3967{
3968 struct net_device *dev;
3969 struct list_head *iter;
3970 int ret;
3971
3972 netdev_for_each_lower_dev(lag_dev, dev, iter) {
3973 if (mlxsw_sp_port_dev_check(dev)) {
3974 ret = mlxsw_sp_netdevice_vport_event(dev, event, ptr,
3975 vid);
Ido Schimmel80bedf12016-06-20 23:03:59 +02003976 if (ret)
Ido Schimmel272c4472015-12-15 16:03:47 +01003977 return ret;
3978 }
3979 }
3980
Ido Schimmel80bedf12016-06-20 23:03:59 +02003981 return 0;
Ido Schimmel272c4472015-12-15 16:03:47 +01003982}
3983
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003984static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
3985 unsigned long event, void *ptr)
3986{
3987 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
3988 u16 vid = vlan_dev_vlan_id(vlan_dev);
3989
Ido Schimmel272c4472015-12-15 16:03:47 +01003990 if (mlxsw_sp_port_dev_check(real_dev))
3991 return mlxsw_sp_netdevice_vport_event(real_dev, event, ptr,
3992 vid);
3993 else if (netif_is_lag_master(real_dev))
3994 return mlxsw_sp_netdevice_lag_vport_event(real_dev, event, ptr,
3995 vid);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003996
Ido Schimmel80bedf12016-06-20 23:03:59 +02003997 return 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003998}
3999
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004000static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
4001 unsigned long event, void *ptr)
4002{
4003 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004004 int err = 0;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004005
Ido Schimmel6e095fd2016-07-04 08:23:13 +02004006 if (event == NETDEV_CHANGEADDR || event == NETDEV_CHANGEMTU)
4007 err = mlxsw_sp_netdevice_router_port_event(dev);
4008 else if (mlxsw_sp_port_dev_check(dev))
Ido Schimmel80bedf12016-06-20 23:03:59 +02004009 err = mlxsw_sp_netdevice_port_event(dev, event, ptr);
4010 else if (netif_is_lag_master(dev))
4011 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
Ido Schimmel701b1862016-07-04 08:23:16 +02004012 else if (netif_is_bridge_master(dev))
4013 err = mlxsw_sp_netdevice_bridge_event(dev, event, ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004014 else if (is_vlan_dev(dev))
4015 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004016
Ido Schimmel80bedf12016-06-20 23:03:59 +02004017 return notifier_from_errno(err);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004018}
4019
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004020static struct notifier_block mlxsw_sp_netdevice_nb __read_mostly = {
4021 .notifier_call = mlxsw_sp_netdevice_event,
4022};
4023
Ido Schimmel99724c12016-07-04 08:23:14 +02004024static struct notifier_block mlxsw_sp_inetaddr_nb __read_mostly = {
4025 .notifier_call = mlxsw_sp_inetaddr_event,
4026 .priority = 10, /* Must be called before FIB notifier block */
4027};
4028
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004029static int __init mlxsw_sp_module_init(void)
4030{
4031 int err;
4032
4033 register_netdevice_notifier(&mlxsw_sp_netdevice_nb);
Ido Schimmel99724c12016-07-04 08:23:14 +02004034 register_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004035 err = mlxsw_core_driver_register(&mlxsw_sp_driver);
4036 if (err)
4037 goto err_core_driver_register;
4038 return 0;
4039
4040err_core_driver_register:
4041 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
4042 return err;
4043}
4044
4045static void __exit mlxsw_sp_module_exit(void)
4046{
4047 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
Ido Schimmel99724c12016-07-04 08:23:14 +02004048 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004049 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
4050}
4051
4052module_init(mlxsw_sp_module_init);
4053module_exit(mlxsw_sp_module_exit);
4054
4055MODULE_LICENSE("Dual BSD/GPL");
4056MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
4057MODULE_DESCRIPTION("Mellanox Spectrum driver");
4058MODULE_MLXSW_DRIVER_ALIAS(MLXSW_DEVICE_KIND_SPECTRUM);