arch/arm/boot/dts/stih407-clock.dtsi

/*
 * Copyright (C) 2014 STMicroelectronics R&D Limited
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
/ {
	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		/*
		 * Fixed 30MHz oscillator inputs to SoC
		 */
		clk_sysin: clk-sysin {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <30000000>;
		};

		/*
		 * ARM Peripheral clock for timers
		 */
		arm_periph_clk: arm-periph-clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <600000000>;
		};

		/*
		 * Bootloader initialized system infrastructure clock for
		 * serial devices.
		 */
		clk_ext2f_a9: clockgen-c0@13 {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <200000000>;
			clock-output-names = "clk-s-icn-reg-0";
		};

		clockgen-a@090ff000 {
			compatible = "st,clkgen-c32";
			reg = <0x90ff000 0x1000>;

			clk_s_a0_pll: clk-s-a0-pll {
				#clock-cells = <1>;
				compatible = "st,stih407-plls-c32-a0", "st,clkgen-plls-c32";

				clocks = <&clk_sysin>;

				clock-output-names = "clk-s-a0-pll-ofd-0";
			};

			clk_s_a0_flexgen: clk-s-a0-flexgen {
				compatible = "st,flexgen";

				#clock-cells = <1>;

				clocks = <&clk_s_a0_pll 0>,
					 <&clk_sysin>;

				clock-output-names = "clk-ic-lmi0";
			};
		};
	};
};