wanzongshun | 7ec80dd | 2008-12-03 03:55:38 +0100 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/mach-w90x900/time.c |
| 3 | * |
| 4 | * Based on linux/arch/arm/plat-s3c24xx/time.c by Ben Dooks |
| 5 | * |
wanzongshun | 58b5369 | 2009-08-14 15:36:44 +0100 | [diff] [blame^] | 6 | * Copyright (c) 2009 Nuvoton technology corporation |
wanzongshun | 7ec80dd | 2008-12-03 03:55:38 +0100 | [diff] [blame] | 7 | * All rights reserved. |
| 8 | * |
| 9 | * Wan ZongShun <mcuos.com@gmail.com> |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License as published by |
| 13 | * the Free Software Foundation; either version 2 of the License, or |
| 14 | * (at your option) any later version. |
| 15 | * |
| 16 | */ |
| 17 | |
| 18 | #include <linux/kernel.h> |
| 19 | #include <linux/sched.h> |
| 20 | #include <linux/init.h> |
| 21 | #include <linux/interrupt.h> |
| 22 | #include <linux/err.h> |
| 23 | #include <linux/clk.h> |
| 24 | #include <linux/io.h> |
| 25 | #include <linux/leds.h> |
wanzongshun | 58b5369 | 2009-08-14 15:36:44 +0100 | [diff] [blame^] | 26 | #include <linux/clocksource.h> |
| 27 | #include <linux/clockchips.h> |
wanzongshun | 7ec80dd | 2008-12-03 03:55:38 +0100 | [diff] [blame] | 28 | |
| 29 | #include <asm/mach-types.h> |
| 30 | #include <asm/mach/irq.h> |
| 31 | #include <asm/mach/time.h> |
| 32 | |
wanzongshun | 7ec80dd | 2008-12-03 03:55:38 +0100 | [diff] [blame] | 33 | #include <mach/map.h> |
| 34 | #include <mach/regs-timer.h> |
| 35 | |
wanzongshun | 58b5369 | 2009-08-14 15:36:44 +0100 | [diff] [blame^] | 36 | #define RESETINT 0x1f |
| 37 | #define PERIOD (0x01 << 27) |
| 38 | #define ONESHOT (0x00 << 27) |
| 39 | #define COUNTEN (0x01 << 30) |
| 40 | #define INTEN (0x01 << 29) |
| 41 | |
| 42 | #define TICKS_PER_SEC 100 |
| 43 | #define PRESCALE 0x63 /* Divider = prescale + 1 */ |
| 44 | |
| 45 | unsigned int timer0_load; |
| 46 | |
| 47 | static void w90p910_clockevent_setmode(enum clock_event_mode mode, |
| 48 | struct clock_event_device *clk) |
wanzongshun | 7ec80dd | 2008-12-03 03:55:38 +0100 | [diff] [blame] | 49 | { |
wanzongshun | 58b5369 | 2009-08-14 15:36:44 +0100 | [diff] [blame^] | 50 | unsigned int val; |
| 51 | |
| 52 | val = __raw_readl(REG_TCSR0); |
| 53 | val &= ~(0x03 << 27); |
| 54 | |
| 55 | switch (mode) { |
| 56 | case CLOCK_EVT_MODE_PERIODIC: |
| 57 | __raw_writel(timer0_load, REG_TICR0); |
| 58 | val |= (PERIOD | COUNTEN | INTEN | PRESCALE); |
| 59 | break; |
| 60 | |
| 61 | case CLOCK_EVT_MODE_ONESHOT: |
| 62 | val |= (ONESHOT | COUNTEN | INTEN | PRESCALE); |
| 63 | break; |
| 64 | |
| 65 | case CLOCK_EVT_MODE_UNUSED: |
| 66 | case CLOCK_EVT_MODE_SHUTDOWN: |
| 67 | case CLOCK_EVT_MODE_RESUME: |
| 68 | break; |
| 69 | } |
| 70 | |
| 71 | __raw_writel(val, REG_TCSR0); |
| 72 | } |
| 73 | |
| 74 | static int w90p910_clockevent_setnextevent(unsigned long evt, |
| 75 | struct clock_event_device *clk) |
| 76 | { |
| 77 | unsigned int val; |
| 78 | |
| 79 | __raw_writel(evt, REG_TICR0); |
| 80 | |
| 81 | val = __raw_readl(REG_TCSR0); |
| 82 | val |= (COUNTEN | INTEN | PRESCALE); |
| 83 | __raw_writel(val, REG_TCSR0); |
| 84 | |
wanzongshun | 7ec80dd | 2008-12-03 03:55:38 +0100 | [diff] [blame] | 85 | return 0; |
| 86 | } |
| 87 | |
wanzongshun | 58b5369 | 2009-08-14 15:36:44 +0100 | [diff] [blame^] | 88 | static struct clock_event_device w90p910_clockevent_device = { |
| 89 | .name = "w90p910-timer0", |
| 90 | .shift = 32, |
| 91 | .features = CLOCK_EVT_MODE_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, |
| 92 | .set_mode = w90p910_clockevent_setmode, |
| 93 | .set_next_event = w90p910_clockevent_setnextevent, |
| 94 | .rating = 300, |
| 95 | }; |
| 96 | |
wanzongshun | 7ec80dd | 2008-12-03 03:55:38 +0100 | [diff] [blame] | 97 | /*IRQ handler for the timer*/ |
| 98 | |
wanzongshun | 58b5369 | 2009-08-14 15:36:44 +0100 | [diff] [blame^] | 99 | static irqreturn_t w90p910_timer0_interrupt(int irq, void *dev_id) |
wanzongshun | 7ec80dd | 2008-12-03 03:55:38 +0100 | [diff] [blame] | 100 | { |
wanzongshun | 58b5369 | 2009-08-14 15:36:44 +0100 | [diff] [blame^] | 101 | struct clock_event_device *evt = &w90p910_clockevent_device; |
| 102 | |
wanzongshun | 7ec80dd | 2008-12-03 03:55:38 +0100 | [diff] [blame] | 103 | __raw_writel(0x01, REG_TISR); /* clear TIF0 */ |
wanzongshun | 58b5369 | 2009-08-14 15:36:44 +0100 | [diff] [blame^] | 104 | |
| 105 | evt->event_handler(evt); |
wanzongshun | 7ec80dd | 2008-12-03 03:55:38 +0100 | [diff] [blame] | 106 | return IRQ_HANDLED; |
| 107 | } |
| 108 | |
wanzongshun | 58b5369 | 2009-08-14 15:36:44 +0100 | [diff] [blame^] | 109 | static struct irqaction w90p910_timer0_irq = { |
| 110 | .name = "w90p910-timer0", |
wanzongshun | 7ec80dd | 2008-12-03 03:55:38 +0100 | [diff] [blame] | 111 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, |
wanzongshun | 58b5369 | 2009-08-14 15:36:44 +0100 | [diff] [blame^] | 112 | .handler = w90p910_timer0_interrupt, |
wanzongshun | 7ec80dd | 2008-12-03 03:55:38 +0100 | [diff] [blame] | 113 | }; |
| 114 | |
wanzongshun | 58b5369 | 2009-08-14 15:36:44 +0100 | [diff] [blame^] | 115 | static void __init w90p910_clockevents_init(unsigned int rate) |
wanzongshun | 7ec80dd | 2008-12-03 03:55:38 +0100 | [diff] [blame] | 116 | { |
wanzongshun | 58b5369 | 2009-08-14 15:36:44 +0100 | [diff] [blame^] | 117 | w90p910_clockevent_device.mult = div_sc(rate, NSEC_PER_SEC, |
| 118 | w90p910_clockevent_device.shift); |
| 119 | w90p910_clockevent_device.max_delta_ns = clockevent_delta2ns(0xffffffff, |
| 120 | &w90p910_clockevent_device); |
| 121 | w90p910_clockevent_device.min_delta_ns = clockevent_delta2ns(0xf, |
| 122 | &w90p910_clockevent_device); |
| 123 | w90p910_clockevent_device.cpumask = cpumask_of(0); |
| 124 | |
| 125 | clockevents_register_device(&w90p910_clockevent_device); |
wanzongshun | 7ec80dd | 2008-12-03 03:55:38 +0100 | [diff] [blame] | 126 | } |
| 127 | |
wanzongshun | 58b5369 | 2009-08-14 15:36:44 +0100 | [diff] [blame^] | 128 | static cycle_t w90p910_get_cycles(struct clocksource *cs) |
wanzongshun | 7ec80dd | 2008-12-03 03:55:38 +0100 | [diff] [blame] | 129 | { |
wanzongshun | 58b5369 | 2009-08-14 15:36:44 +0100 | [diff] [blame^] | 130 | return ~__raw_readl(REG_TDR1); |
| 131 | } |
| 132 | |
| 133 | static struct clocksource clocksource_w90p910 = { |
| 134 | .name = "w90p910-timer1", |
| 135 | .rating = 200, |
| 136 | .read = w90p910_get_cycles, |
| 137 | .mask = CLOCKSOURCE_MASK(32), |
| 138 | .shift = 20, |
| 139 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
| 140 | }; |
| 141 | |
| 142 | static void __init w90p910_clocksource_init(unsigned int rate) |
| 143 | { |
| 144 | unsigned int val; |
| 145 | |
| 146 | __raw_writel(0xffffffff, REG_TICR1); |
| 147 | |
| 148 | val = __raw_readl(REG_TCSR1); |
| 149 | val |= (COUNTEN | PERIOD); |
| 150 | __raw_writel(val, REG_TCSR1); |
| 151 | |
| 152 | clocksource_w90p910.mult = |
| 153 | clocksource_khz2mult((rate / 1000), clocksource_w90p910.shift); |
| 154 | clocksource_register(&clocksource_w90p910); |
| 155 | } |
| 156 | |
| 157 | static void __init w90p910_timer_init(void) |
| 158 | { |
| 159 | struct clk *ck_ext = clk_get(NULL, "ext"); |
| 160 | unsigned int rate; |
| 161 | |
| 162 | BUG_ON(IS_ERR(ck_ext)); |
| 163 | |
| 164 | rate = clk_get_rate(ck_ext); |
| 165 | clk_put(ck_ext); |
| 166 | rate = rate / (PRESCALE + 0x01); |
| 167 | |
| 168 | /* set a known state */ |
| 169 | __raw_writel(0x00, REG_TCSR0); |
| 170 | __raw_writel(0x00, REG_TCSR1); |
| 171 | __raw_writel(RESETINT, REG_TISR); |
| 172 | timer0_load = (rate / TICKS_PER_SEC); |
| 173 | |
| 174 | setup_irq(IRQ_TIMER0, &w90p910_timer0_irq); |
| 175 | |
| 176 | w90p910_clocksource_init(rate); |
| 177 | w90p910_clockevents_init(rate); |
wanzongshun | 7ec80dd | 2008-12-03 03:55:38 +0100 | [diff] [blame] | 178 | } |
| 179 | |
| 180 | struct sys_timer w90x900_timer = { |
wanzongshun | 58b5369 | 2009-08-14 15:36:44 +0100 | [diff] [blame^] | 181 | .init = w90p910_timer_init, |
wanzongshun | 7ec80dd | 2008-12-03 03:55:38 +0100 | [diff] [blame] | 182 | }; |