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Russell Kingf27ecac2005-08-18 21:31:00 +01001/*
Rob Herring520f7bd2012-12-27 13:10:24 -06002 * include/linux/irqchip/arm-gic.h
Russell Kingf27ecac2005-08-18 21:31:00 +01003 *
4 * Copyright (C) 2002 ARM Limited, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
Rob Herring520f7bd2012-12-27 13:10:24 -060010#ifndef __LINUX_IRQCHIP_ARM_GIC_H
11#define __LINUX_IRQCHIP_ARM_GIC_H
Russell Kingf27ecac2005-08-18 21:31:00 +010012
Russell Kingf27ecac2005-08-18 21:31:00 +010013#define GIC_CPU_CTRL 0x00
14#define GIC_CPU_PRIMASK 0x04
15#define GIC_CPU_BINPOINT 0x08
16#define GIC_CPU_INTACK 0x0c
17#define GIC_CPU_EOI 0x10
18#define GIC_CPU_RUNNINGPRI 0x14
19#define GIC_CPU_HIGHPRI 0x18
20
21#define GIC_DIST_CTRL 0x000
22#define GIC_DIST_CTR 0x004
Christoffer Dall7c7945a2013-01-23 13:18:03 -050023#define GIC_DIST_IGROUP 0x080
Russell Kingf27ecac2005-08-18 21:31:00 +010024#define GIC_DIST_ENABLE_SET 0x100
25#define GIC_DIST_ENABLE_CLEAR 0x180
26#define GIC_DIST_PENDING_SET 0x200
27#define GIC_DIST_PENDING_CLEAR 0x280
Christoffer Dall7c7945a2013-01-23 13:18:03 -050028#define GIC_DIST_ACTIVE_SET 0x300
29#define GIC_DIST_ACTIVE_CLEAR 0x380
Russell Kingf27ecac2005-08-18 21:31:00 +010030#define GIC_DIST_PRI 0x400
31#define GIC_DIST_TARGET 0x800
32#define GIC_DIST_CONFIG 0xc00
33#define GIC_DIST_SOFTINT 0xf00
Nicolas Pitre1a6b69b2012-04-12 01:40:31 -040034#define GIC_DIST_SGI_PENDING_CLEAR 0xf10
35#define GIC_DIST_SGI_PENDING_SET 0xf20
Russell Kingf27ecac2005-08-18 21:31:00 +010036
Marc Zyngierfdf77a72013-01-21 19:36:11 -050037#define GICH_HCR 0x0
38#define GICH_VTR 0x4
39#define GICH_VMCR 0x8
40#define GICH_MISR 0x10
41#define GICH_EISR0 0x20
42#define GICH_EISR1 0x24
43#define GICH_ELRSR0 0x30
44#define GICH_ELRSR1 0x34
45#define GICH_APR 0xf0
46#define GICH_LR0 0x100
47
48#define GICH_HCR_EN (1 << 0)
49#define GICH_HCR_UIE (1 << 1)
50
51#define GICH_LR_VIRTUALID (0x3ff << 0)
52#define GICH_LR_PHYSID_CPUID_SHIFT (10)
53#define GICH_LR_PHYSID_CPUID (7 << GICH_LR_PHYSID_CPUID_SHIFT)
54#define GICH_LR_STATE (3 << 28)
55#define GICH_LR_PENDING_BIT (1 << 28)
56#define GICH_LR_ACTIVE_BIT (1 << 29)
57#define GICH_LR_EOI (1 << 19)
58
59#define GICH_MISR_EOI (1 << 0)
60#define GICH_MISR_U (1 << 1)
61
Marc Zyngiera96ab032013-01-24 13:39:43 +000062#ifndef __ASSEMBLY__
63
Rob Herring4294f8b2011-09-28 21:25:31 -050064struct device_node;
65
Santosh Shilimkard7ed36a2011-03-02 08:03:22 +010066extern struct irq_chip gic_arch_extn;
Russell Kingff2e27a2010-12-04 16:13:29 +000067
Marc Zyngierdb0d4db2011-11-12 16:09:49 +000068void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *,
Grant Likely75294952012-02-14 14:06:57 -070069 u32 offset, struct device_node *);
Catalin Marinasb3a1bde2007-02-14 19:14:56 +010070void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
Nicolas Pitre10d9eb82013-03-19 23:59:04 -040071void gic_cpu_if_down(void);
Changhwan Youne807acb2011-07-16 10:49:47 +090072
Marc Zyngierdb0d4db2011-11-12 16:09:49 +000073static inline void gic_init(unsigned int nr, int start,
74 void __iomem *dist , void __iomem *cpu)
75{
Grant Likely75294952012-02-14 14:06:57 -070076 gic_init_bases(nr, start, dist, cpu, 0, NULL);
Marc Zyngierdb0d4db2011-11-12 16:09:49 +000077}
78
Nicolas Pitre14d2ca62012-11-28 18:48:19 -050079void gic_send_sgi(unsigned int cpu_id, unsigned int irq);
Nicolas Pitreed967622012-07-05 21:33:26 -040080int gic_get_cpu_id(unsigned int cpu);
Nicolas Pitre1a6b69b2012-04-12 01:40:31 -040081void gic_migrate_target(unsigned int new_cpu_id);
Nicolas Pitreeeb44652012-11-28 18:17:25 -050082unsigned long gic_get_sgir_physaddr(void);
Nicolas Pitre1a6b69b2012-04-12 01:40:31 -040083
Marc Zyngiera96ab032013-01-24 13:39:43 +000084#endif /* __ASSEMBLY */
85
Russell Kingf27ecac2005-08-18 21:31:00 +010086#endif