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Shawn Guo95ceafd2012-09-06 07:09:11 +00001/*
2 * Copyright (C) 2012 Freescale Semiconductor, Inc.
3 *
4 * The OPP code in function cpu0_set_target() is reused from
5 * drivers/cpufreq/omap-cpufreq.c
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13
14#include <linux/clk.h>
Sudeep KarkadaNageshae1825b22013-09-10 18:59:46 +010015#include <linux/cpu.h>
Shawn Guo95ceafd2012-09-06 07:09:11 +000016#include <linux/cpufreq.h>
17#include <linux/err.h>
18#include <linux/module.h>
19#include <linux/of.h>
Nishanth Menone4db1c72013-09-19 16:03:52 -050020#include <linux/pm_opp.h>
Shawn Guo5553f9e2013-01-30 14:27:49 +000021#include <linux/platform_device.h>
Shawn Guo95ceafd2012-09-06 07:09:11 +000022#include <linux/regulator/consumer.h>
23#include <linux/slab.h>
24
25static unsigned int transition_latency;
26static unsigned int voltage_tolerance; /* in percentage */
27
28static struct device *cpu_dev;
29static struct clk *cpu_clk;
30static struct regulator *cpu_reg;
31static struct cpufreq_frequency_table *freq_table;
32
Shawn Guo95ceafd2012-09-06 07:09:11 +000033static unsigned int cpu0_get_speed(unsigned int cpu)
34{
35 return clk_get_rate(cpu_clk) / 1000;
36}
37
Viresh Kumar9c0ebcf2013-10-25 19:45:48 +053038static int cpu0_set_target(struct cpufreq_policy *policy, unsigned int index)
Shawn Guo95ceafd2012-09-06 07:09:11 +000039{
Nishanth Menon47d43ba2013-09-19 16:03:51 -050040 struct dev_pm_opp *opp;
jhbird.choi@samsung.com5df60552013-03-18 08:09:42 +000041 unsigned long volt = 0, volt_old = 0, tol = 0;
Viresh Kumard4019f02013-08-14 19:38:24 +053042 unsigned int old_freq, new_freq;
Guennadi Liakhovetski0ca68432013-02-25 18:22:37 +010043 long freq_Hz, freq_exact;
Shawn Guo95ceafd2012-09-06 07:09:11 +000044 int ret;
45
Shawn Guo95ceafd2012-09-06 07:09:11 +000046 freq_Hz = clk_round_rate(cpu_clk, freq_table[index].frequency * 1000);
47 if (freq_Hz < 0)
48 freq_Hz = freq_table[index].frequency * 1000;
Shawn Guo95ceafd2012-09-06 07:09:11 +000049
Viresh Kumard4019f02013-08-14 19:38:24 +053050 freq_exact = freq_Hz;
51 new_freq = freq_Hz / 1000;
52 old_freq = clk_get_rate(cpu_clk) / 1000;
Shawn Guo95ceafd2012-09-06 07:09:11 +000053
Mark Brown4a511de2013-08-13 14:58:24 +020054 if (!IS_ERR(cpu_reg)) {
Nishanth Menon78e8eb82013-01-18 19:52:33 +000055 rcu_read_lock();
Nishanth Menon5d4879c2013-09-19 16:03:50 -050056 opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_Hz);
Shawn Guo95ceafd2012-09-06 07:09:11 +000057 if (IS_ERR(opp)) {
Nishanth Menon78e8eb82013-01-18 19:52:33 +000058 rcu_read_unlock();
Shawn Guo95ceafd2012-09-06 07:09:11 +000059 pr_err("failed to find OPP for %ld\n", freq_Hz);
Viresh Kumard4019f02013-08-14 19:38:24 +053060 return PTR_ERR(opp);
Shawn Guo95ceafd2012-09-06 07:09:11 +000061 }
Nishanth Menon5d4879c2013-09-19 16:03:50 -050062 volt = dev_pm_opp_get_voltage(opp);
Nishanth Menon78e8eb82013-01-18 19:52:33 +000063 rcu_read_unlock();
Shawn Guo95ceafd2012-09-06 07:09:11 +000064 tol = volt * voltage_tolerance / 100;
65 volt_old = regulator_get_voltage(cpu_reg);
66 }
67
68 pr_debug("%u MHz, %ld mV --> %u MHz, %ld mV\n",
Viresh Kumard4019f02013-08-14 19:38:24 +053069 old_freq / 1000, volt_old ? volt_old / 1000 : -1,
70 new_freq / 1000, volt ? volt / 1000 : -1);
Shawn Guo95ceafd2012-09-06 07:09:11 +000071
72 /* scaling up? scale voltage before frequency */
Viresh Kumard4019f02013-08-14 19:38:24 +053073 if (!IS_ERR(cpu_reg) && new_freq > old_freq) {
Shawn Guo95ceafd2012-09-06 07:09:11 +000074 ret = regulator_set_voltage_tol(cpu_reg, volt, tol);
75 if (ret) {
76 pr_err("failed to scale voltage up: %d\n", ret);
Viresh Kumard4019f02013-08-14 19:38:24 +053077 return ret;
Shawn Guo95ceafd2012-09-06 07:09:11 +000078 }
79 }
80
Guennadi Liakhovetski0ca68432013-02-25 18:22:37 +010081 ret = clk_set_rate(cpu_clk, freq_exact);
Shawn Guo95ceafd2012-09-06 07:09:11 +000082 if (ret) {
83 pr_err("failed to set clock rate: %d\n", ret);
Mark Brown4a511de2013-08-13 14:58:24 +020084 if (!IS_ERR(cpu_reg))
Shawn Guo95ceafd2012-09-06 07:09:11 +000085 regulator_set_voltage_tol(cpu_reg, volt_old, tol);
Viresh Kumard4019f02013-08-14 19:38:24 +053086 return ret;
Shawn Guo95ceafd2012-09-06 07:09:11 +000087 }
88
89 /* scaling down? scale voltage after frequency */
Viresh Kumard4019f02013-08-14 19:38:24 +053090 if (!IS_ERR(cpu_reg) && new_freq < old_freq) {
Shawn Guo95ceafd2012-09-06 07:09:11 +000091 ret = regulator_set_voltage_tol(cpu_reg, volt, tol);
92 if (ret) {
93 pr_err("failed to scale voltage down: %d\n", ret);
Viresh Kumard4019f02013-08-14 19:38:24 +053094 clk_set_rate(cpu_clk, old_freq * 1000);
Shawn Guo95ceafd2012-09-06 07:09:11 +000095 }
96 }
97
Viresh Kumarfd143b42013-04-01 12:57:44 +000098 return ret;
Shawn Guo95ceafd2012-09-06 07:09:11 +000099}
100
101static int cpu0_cpufreq_init(struct cpufreq_policy *policy)
102{
Viresh Kumar78b3d102013-10-03 20:29:09 +0530103 return cpufreq_generic_init(policy, freq_table, transition_latency);
Shawn Guo95ceafd2012-09-06 07:09:11 +0000104}
105
Shawn Guo95ceafd2012-09-06 07:09:11 +0000106static struct cpufreq_driver cpu0_cpufreq_driver = {
107 .flags = CPUFREQ_STICKY,
Viresh Kumarf793d792013-10-03 20:28:00 +0530108 .verify = cpufreq_generic_frequency_table_verify,
Viresh Kumar9c0ebcf2013-10-25 19:45:48 +0530109 .target_index = cpu0_set_target,
Shawn Guo95ceafd2012-09-06 07:09:11 +0000110 .get = cpu0_get_speed,
111 .init = cpu0_cpufreq_init,
Viresh Kumarf793d792013-10-03 20:28:00 +0530112 .exit = cpufreq_generic_exit,
Shawn Guo95ceafd2012-09-06 07:09:11 +0000113 .name = "generic_cpu0",
Viresh Kumarf793d792013-10-03 20:28:00 +0530114 .attr = cpufreq_generic_attr,
Shawn Guo95ceafd2012-09-06 07:09:11 +0000115};
116
Shawn Guo5553f9e2013-01-30 14:27:49 +0000117static int cpu0_cpufreq_probe(struct platform_device *pdev)
Shawn Guo95ceafd2012-09-06 07:09:11 +0000118{
Sudeep KarkadaNageshaf837a9b2013-06-17 15:04:19 +0100119 struct device_node *np;
Shawn Guo95ceafd2012-09-06 07:09:11 +0000120 int ret;
121
Sudeep KarkadaNageshae1825b22013-09-10 18:59:46 +0100122 cpu_dev = get_cpu_device(0);
123 if (!cpu_dev) {
124 pr_err("failed to get cpu0 device\n");
125 return -ENODEV;
126 }
Paolo Pisatif5c3ef22013-03-28 09:24:29 +0000127
Sudeep KarkadaNageshaf837a9b2013-06-17 15:04:19 +0100128 np = of_node_get(cpu_dev->of_node);
Shawn Guo95ceafd2012-09-06 07:09:11 +0000129 if (!np) {
130 pr_err("failed to find cpu0 node\n");
Sudeep KarkadaNageshaf837a9b2013-06-17 15:04:19 +0100131 return -ENOENT;
Shawn Guo95ceafd2012-09-06 07:09:11 +0000132 }
133
Mark Brown7d748972013-08-09 19:07:12 +0100134 cpu_reg = devm_regulator_get_optional(cpu_dev, "cpu0");
Nishanth Menonfc31d6f2013-05-01 13:38:12 +0000135 if (IS_ERR(cpu_reg)) {
136 /*
137 * If cpu0 regulator supply node is present, but regulator is
138 * not yet registered, we should try defering probe.
139 */
140 if (PTR_ERR(cpu_reg) == -EPROBE_DEFER) {
141 dev_err(cpu_dev, "cpu0 regulator not ready, retry\n");
142 ret = -EPROBE_DEFER;
143 goto out_put_node;
144 }
145 pr_warn("failed to get cpu0 regulator: %ld\n",
146 PTR_ERR(cpu_reg));
Nishanth Menonfc31d6f2013-05-01 13:38:12 +0000147 }
148
Shawn Guo5553f9e2013-01-30 14:27:49 +0000149 cpu_clk = devm_clk_get(cpu_dev, NULL);
Shawn Guo95ceafd2012-09-06 07:09:11 +0000150 if (IS_ERR(cpu_clk)) {
151 ret = PTR_ERR(cpu_clk);
152 pr_err("failed to get cpu0 clock: %d\n", ret);
153 goto out_put_node;
154 }
155
Shawn Guo95ceafd2012-09-06 07:09:11 +0000156 ret = of_init_opp_table(cpu_dev);
157 if (ret) {
158 pr_err("failed to init OPP table: %d\n", ret);
159 goto out_put_node;
160 }
161
Nishanth Menon5d4879c2013-09-19 16:03:50 -0500162 ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
Shawn Guo95ceafd2012-09-06 07:09:11 +0000163 if (ret) {
164 pr_err("failed to init cpufreq table: %d\n", ret);
165 goto out_put_node;
166 }
167
168 of_property_read_u32(np, "voltage-tolerance", &voltage_tolerance);
169
170 if (of_property_read_u32(np, "clock-latency", &transition_latency))
171 transition_latency = CPUFREQ_ETERNAL;
172
Philipp Zabel43c638e2013-09-26 11:19:37 +0200173 if (!IS_ERR(cpu_reg)) {
Nishanth Menon47d43ba2013-09-19 16:03:51 -0500174 struct dev_pm_opp *opp;
Shawn Guo95ceafd2012-09-06 07:09:11 +0000175 unsigned long min_uV, max_uV;
176 int i;
177
178 /*
179 * OPP is maintained in order of increasing frequency, and
180 * freq_table initialised from OPP is therefore sorted in the
181 * same order.
182 */
183 for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++)
184 ;
Nishanth Menon78e8eb82013-01-18 19:52:33 +0000185 rcu_read_lock();
Nishanth Menon5d4879c2013-09-19 16:03:50 -0500186 opp = dev_pm_opp_find_freq_exact(cpu_dev,
Shawn Guo95ceafd2012-09-06 07:09:11 +0000187 freq_table[0].frequency * 1000, true);
Nishanth Menon5d4879c2013-09-19 16:03:50 -0500188 min_uV = dev_pm_opp_get_voltage(opp);
189 opp = dev_pm_opp_find_freq_exact(cpu_dev,
Shawn Guo95ceafd2012-09-06 07:09:11 +0000190 freq_table[i-1].frequency * 1000, true);
Nishanth Menon5d4879c2013-09-19 16:03:50 -0500191 max_uV = dev_pm_opp_get_voltage(opp);
Nishanth Menon78e8eb82013-01-18 19:52:33 +0000192 rcu_read_unlock();
Shawn Guo95ceafd2012-09-06 07:09:11 +0000193 ret = regulator_set_voltage_time(cpu_reg, min_uV, max_uV);
194 if (ret > 0)
195 transition_latency += ret * 1000;
196 }
197
198 ret = cpufreq_register_driver(&cpu0_cpufreq_driver);
199 if (ret) {
200 pr_err("failed register driver: %d\n", ret);
201 goto out_free_table;
202 }
203
204 of_node_put(np);
205 return 0;
206
207out_free_table:
Nishanth Menon5d4879c2013-09-19 16:03:50 -0500208 dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
Shawn Guo95ceafd2012-09-06 07:09:11 +0000209out_put_node:
210 of_node_put(np);
211 return ret;
212}
Shawn Guo5553f9e2013-01-30 14:27:49 +0000213
214static int cpu0_cpufreq_remove(struct platform_device *pdev)
215{
216 cpufreq_unregister_driver(&cpu0_cpufreq_driver);
Nishanth Menon5d4879c2013-09-19 16:03:50 -0500217 dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
Shawn Guo5553f9e2013-01-30 14:27:49 +0000218
219 return 0;
220}
221
222static struct platform_driver cpu0_cpufreq_platdrv = {
223 .driver = {
224 .name = "cpufreq-cpu0",
225 .owner = THIS_MODULE,
226 },
227 .probe = cpu0_cpufreq_probe,
228 .remove = cpu0_cpufreq_remove,
229};
230module_platform_driver(cpu0_cpufreq_platdrv);
Shawn Guo95ceafd2012-09-06 07:09:11 +0000231
232MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
233MODULE_DESCRIPTION("Generic CPU0 cpufreq driver");
234MODULE_LICENSE("GPL");