blob: dd162248c3ee71a8a484c220f2f64e7f31bb193c [file] [log] [blame]
Tomasz Nowicki935c7602016-06-10 21:55:13 +02001/*
2 * Copyright (C) 2016 Broadcom
3 * Author: Jayachandran C <jchandra@broadcom.com>
4 * Copyright (C) 2016 Semihalf
5 * Author: Tomasz Nowicki <tn@semihalf.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License, version 2, as
9 * published by the Free Software Foundation (the "GPL").
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License version 2 (GPLv2) for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * version 2 (GPLv2) along with this source code.
18 */
19
20#define pr_fmt(fmt) "ACPI: " fmt
21
22#include <linux/kernel.h>
23#include <linux/pci.h>
24#include <linux/pci-acpi.h>
Tomasz Nowicki13983eb2016-09-09 21:24:03 +020025#include <linux/pci-ecam.h>
Tomasz Nowicki935c7602016-06-10 21:55:13 +020026
27/* Structure to hold entries from the MCFG table */
28struct mcfg_entry {
29 struct list_head list;
30 phys_addr_t addr;
31 u16 segment;
32 u8 bus_start;
33 u8 bus_end;
34};
35
Tomasz Nowicki5b69b852016-09-09 21:24:04 +020036#ifdef CONFIG_PCI_QUIRKS
37struct mcfg_fixup {
38 char oem_id[ACPI_OEM_ID_SIZE + 1];
39 char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
40 u32 oem_revision;
41 u16 segment;
42 struct resource bus_range;
43 struct pci_ecam_ops *ops;
44 struct resource cfgres;
45};
46
47#define MCFG_BUS_RANGE(start, end) DEFINE_RES_NAMED((start), \
48 ((end) - (start) + 1), \
49 NULL, IORESOURCE_BUS)
50#define MCFG_BUS_ANY MCFG_BUS_RANGE(0x0, 0xff)
51
52static struct mcfg_fixup mcfg_quirks[] = {
53/* { OEM_ID, OEM_TABLE_ID, REV, SEGMENT, BUS_RANGE, ops, cfgres }, */
Christopher Covington2ca5b8d2016-11-02 11:11:27 -050054
55#define QCOM_ECAM32(seg) \
56 { "QCOM ", "QDF2432 ", 1, seg, MCFG_BUS_ANY, &pci_32b_ops }
57 QCOM_ECAM32(0),
58 QCOM_ECAM32(1),
59 QCOM_ECAM32(2),
60 QCOM_ECAM32(3),
61 QCOM_ECAM32(4),
62 QCOM_ECAM32(5),
63 QCOM_ECAM32(6),
64 QCOM_ECAM32(7),
Dongdong Liu5f00f1a2016-12-01 00:45:35 -060065
66#define HISI_QUAD_DOM(table_id, seg, ops) \
67 { "HISI ", table_id, 0, (seg) + 0, MCFG_BUS_ANY, ops }, \
68 { "HISI ", table_id, 0, (seg) + 1, MCFG_BUS_ANY, ops }, \
69 { "HISI ", table_id, 0, (seg) + 2, MCFG_BUS_ANY, ops }, \
70 { "HISI ", table_id, 0, (seg) + 3, MCFG_BUS_ANY, ops }
71 HISI_QUAD_DOM("HIP05 ", 0, &hisi_pcie_ops),
72 HISI_QUAD_DOM("HIP06 ", 0, &hisi_pcie_ops),
73 HISI_QUAD_DOM("HIP07 ", 0, &hisi_pcie_ops),
74 HISI_QUAD_DOM("HIP07 ", 4, &hisi_pcie_ops),
75 HISI_QUAD_DOM("HIP07 ", 8, &hisi_pcie_ops),
76 HISI_QUAD_DOM("HIP07 ", 12, &hisi_pcie_ops),
Tomasz Nowicki5b69b852016-09-09 21:24:04 +020077};
78
79static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
80static char mcfg_oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
81static u32 mcfg_oem_revision;
82
83static int pci_mcfg_quirk_matches(struct mcfg_fixup *f, u16 segment,
84 struct resource *bus_range)
85{
86 if (!memcmp(f->oem_id, mcfg_oem_id, ACPI_OEM_ID_SIZE) &&
87 !memcmp(f->oem_table_id, mcfg_oem_table_id,
88 ACPI_OEM_TABLE_ID_SIZE) &&
89 f->oem_revision == mcfg_oem_revision &&
90 f->segment == segment &&
91 resource_contains(&f->bus_range, bus_range))
92 return 1;
93
94 return 0;
95}
96#endif
97
98static void pci_mcfg_apply_quirks(struct acpi_pci_root *root,
99 struct resource *cfgres,
100 struct pci_ecam_ops **ecam_ops)
101{
102#ifdef CONFIG_PCI_QUIRKS
103 u16 segment = root->segment;
104 struct resource *bus_range = &root->secondary;
105 struct mcfg_fixup *f;
106 int i;
107
108 for (i = 0, f = mcfg_quirks; i < ARRAY_SIZE(mcfg_quirks); i++, f++) {
109 if (pci_mcfg_quirk_matches(f, segment, bus_range)) {
110 if (f->cfgres.start)
111 *cfgres = f->cfgres;
112 if (f->ops)
113 *ecam_ops = f->ops;
114 dev_info(&root->device->dev, "MCFG quirk: ECAM at %pR for %pR with %ps\n",
115 cfgres, bus_range, *ecam_ops);
116 return;
117 }
118 }
119#endif
120}
121
Tomasz Nowicki935c7602016-06-10 21:55:13 +0200122/* List to save MCFG entries */
123static LIST_HEAD(pci_mcfg_list);
124
Tomasz Nowicki13983eb2016-09-09 21:24:03 +0200125int pci_mcfg_lookup(struct acpi_pci_root *root, struct resource *cfgres,
126 struct pci_ecam_ops **ecam_ops)
Tomasz Nowicki935c7602016-06-10 21:55:13 +0200127{
Tomasz Nowicki13983eb2016-09-09 21:24:03 +0200128 struct pci_ecam_ops *ops = &pci_generic_ecam_ops;
129 struct resource *bus_res = &root->secondary;
130 u16 seg = root->segment;
Tomasz Nowicki935c7602016-06-10 21:55:13 +0200131 struct mcfg_entry *e;
Tomasz Nowicki13983eb2016-09-09 21:24:03 +0200132 struct resource res;
133
134 /* Use address from _CBA if present, otherwise lookup MCFG */
135 if (root->mcfg_addr)
136 goto skip_lookup;
Tomasz Nowicki935c7602016-06-10 21:55:13 +0200137
138 /*
139 * We expect exact match, unless MCFG entry end bus covers more than
140 * specified by caller.
141 */
142 list_for_each_entry(e, &pci_mcfg_list, list) {
143 if (e->segment == seg && e->bus_start == bus_res->start &&
Tomasz Nowicki13983eb2016-09-09 21:24:03 +0200144 e->bus_end >= bus_res->end) {
145 root->mcfg_addr = e->addr;
146 }
147
Tomasz Nowicki935c7602016-06-10 21:55:13 +0200148 }
149
Tomasz Nowicki13983eb2016-09-09 21:24:03 +0200150skip_lookup:
151 memset(&res, 0, sizeof(res));
Tomasz Nowicki5b69b852016-09-09 21:24:04 +0200152 if (root->mcfg_addr) {
153 res.start = root->mcfg_addr + (bus_res->start << 20);
154 res.end = res.start + (resource_size(bus_res) << 20) - 1;
155 res.flags = IORESOURCE_MEM;
156 }
157
158 /*
159 * Allow quirks to override default ECAM ops and CFG resource
160 * range. This may even fabricate a CFG resource range in case
161 * MCFG does not have it. Invalid CFG start address means MCFG
162 * firmware bug or we need another quirk in array.
163 */
164 pci_mcfg_apply_quirks(root, &res, &ops);
165 if (!res.start)
166 return -ENXIO;
167
Tomasz Nowicki13983eb2016-09-09 21:24:03 +0200168 *cfgres = res;
169 *ecam_ops = ops;
Tomasz Nowicki935c7602016-06-10 21:55:13 +0200170 return 0;
171}
172
173static __init int pci_mcfg_parse(struct acpi_table_header *header)
174{
175 struct acpi_table_mcfg *mcfg;
176 struct acpi_mcfg_allocation *mptr;
177 struct mcfg_entry *e, *arr;
178 int i, n;
179
180 if (header->length < sizeof(struct acpi_table_mcfg))
181 return -EINVAL;
182
183 n = (header->length - sizeof(struct acpi_table_mcfg)) /
184 sizeof(struct acpi_mcfg_allocation);
185 mcfg = (struct acpi_table_mcfg *)header;
186 mptr = (struct acpi_mcfg_allocation *) &mcfg[1];
187
188 arr = kcalloc(n, sizeof(*arr), GFP_KERNEL);
189 if (!arr)
190 return -ENOMEM;
191
192 for (i = 0, e = arr; i < n; i++, mptr++, e++) {
193 e->segment = mptr->pci_segment;
194 e->addr = mptr->address;
195 e->bus_start = mptr->start_bus_number;
196 e->bus_end = mptr->end_bus_number;
197 list_add(&e->list, &pci_mcfg_list);
198 }
199
Tomasz Nowicki5b69b852016-09-09 21:24:04 +0200200#ifdef CONFIG_PCI_QUIRKS
201 /* Save MCFG IDs and revision for quirks matching */
202 memcpy(mcfg_oem_id, header->oem_id, ACPI_OEM_ID_SIZE);
203 memcpy(mcfg_oem_table_id, header->oem_table_id, ACPI_OEM_TABLE_ID_SIZE);
204 mcfg_oem_revision = header->oem_revision;
205#endif
206
Tomasz Nowicki935c7602016-06-10 21:55:13 +0200207 pr_info("MCFG table detected, %d entries\n", n);
208 return 0;
209}
210
211/* Interface called by ACPI - parse and save MCFG table */
212void __init pci_mmcfg_late_init(void)
213{
214 int err = acpi_table_parse(ACPI_SIG_MCFG, pci_mcfg_parse);
215 if (err)
216 pr_err("Failed to parse MCFG (%d)\n", err);
217}