Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * include/asm-ppc64/cputable.h |
| 3 | * |
| 4 | * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org) |
| 5 | * |
| 6 | * Modifications for ppc64: |
| 7 | * Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com> |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License |
| 11 | * as published by the Free Software Foundation; either version |
| 12 | * 2 of the License, or (at your option) any later version. |
| 13 | */ |
| 14 | |
| 15 | #ifndef __ASM_PPC_CPUTABLE_H |
| 16 | #define __ASM_PPC_CPUTABLE_H |
| 17 | |
| 18 | #include <linux/config.h> |
| 19 | #include <asm/page.h> /* for ASM_CONST */ |
| 20 | |
| 21 | /* Exposed to userland CPU features - Must match ppc32 definitions */ |
| 22 | #define PPC_FEATURE_32 0x80000000 |
| 23 | #define PPC_FEATURE_64 0x40000000 |
| 24 | #define PPC_FEATURE_601_INSTR 0x20000000 |
| 25 | #define PPC_FEATURE_HAS_ALTIVEC 0x10000000 |
| 26 | #define PPC_FEATURE_HAS_FPU 0x08000000 |
| 27 | #define PPC_FEATURE_HAS_MMU 0x04000000 |
| 28 | #define PPC_FEATURE_HAS_4xxMAC 0x02000000 |
| 29 | #define PPC_FEATURE_UNIFIED_CACHE 0x01000000 |
| 30 | |
| 31 | #ifdef __KERNEL__ |
| 32 | |
| 33 | #ifndef __ASSEMBLY__ |
| 34 | |
| 35 | /* This structure can grow, it's real size is used by head.S code |
| 36 | * via the mkdefs mechanism. |
| 37 | */ |
| 38 | struct cpu_spec; |
| 39 | |
| 40 | typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec); |
| 41 | |
| 42 | struct cpu_spec { |
| 43 | /* CPU is matched via (PVR & pvr_mask) == pvr_value */ |
| 44 | unsigned int pvr_mask; |
| 45 | unsigned int pvr_value; |
| 46 | |
| 47 | char *cpu_name; |
| 48 | unsigned long cpu_features; /* Kernel features */ |
| 49 | unsigned int cpu_user_features; /* Userland features */ |
| 50 | |
| 51 | /* cache line sizes */ |
| 52 | unsigned int icache_bsize; |
| 53 | unsigned int dcache_bsize; |
| 54 | |
| 55 | /* this is called to initialize various CPU bits like L1 cache, |
| 56 | * BHT, SPD, etc... from head.S before branching to identify_machine |
| 57 | */ |
| 58 | cpu_setup_t cpu_setup; |
| 59 | |
| 60 | /* This is used to identify firmware features which are available |
| 61 | * to the kernel. |
| 62 | */ |
| 63 | unsigned long firmware_features; |
| 64 | }; |
| 65 | |
| 66 | extern struct cpu_spec cpu_specs[]; |
| 67 | extern struct cpu_spec *cur_cpu_spec; |
| 68 | |
| 69 | static inline unsigned long cpu_has_feature(unsigned long feature) |
| 70 | { |
| 71 | return cur_cpu_spec->cpu_features & feature; |
| 72 | } |
| 73 | |
| 74 | |
| 75 | /* firmware feature bitmask values */ |
| 76 | #define FIRMWARE_MAX_FEATURES 63 |
| 77 | |
| 78 | #define FW_FEATURE_PFT (1UL<<0) |
| 79 | #define FW_FEATURE_TCE (1UL<<1) |
| 80 | #define FW_FEATURE_SPRG0 (1UL<<2) |
| 81 | #define FW_FEATURE_DABR (1UL<<3) |
| 82 | #define FW_FEATURE_COPY (1UL<<4) |
| 83 | #define FW_FEATURE_ASR (1UL<<5) |
| 84 | #define FW_FEATURE_DEBUG (1UL<<6) |
| 85 | #define FW_FEATURE_TERM (1UL<<7) |
| 86 | #define FW_FEATURE_PERF (1UL<<8) |
| 87 | #define FW_FEATURE_DUMP (1UL<<9) |
| 88 | #define FW_FEATURE_INTERRUPT (1UL<<10) |
| 89 | #define FW_FEATURE_MIGRATE (1UL<<11) |
| 90 | #define FW_FEATURE_PERFMON (1UL<<12) |
| 91 | #define FW_FEATURE_CRQ (1UL<<13) |
| 92 | #define FW_FEATURE_VIO (1UL<<14) |
| 93 | #define FW_FEATURE_RDMA (1UL<<15) |
| 94 | #define FW_FEATURE_LLAN (1UL<<16) |
| 95 | #define FW_FEATURE_BULK (1UL<<17) |
| 96 | #define FW_FEATURE_XDABR (1UL<<18) |
| 97 | #define FW_FEATURE_MULTITCE (1UL<<19) |
| 98 | #define FW_FEATURE_SPLPAR (1UL<<20) |
| 99 | |
| 100 | typedef struct { |
| 101 | unsigned long val; |
| 102 | char * name; |
| 103 | } firmware_feature_t; |
| 104 | |
| 105 | extern firmware_feature_t firmware_features_table[]; |
| 106 | |
| 107 | #endif /* __ASSEMBLY__ */ |
| 108 | |
| 109 | /* CPU kernel features */ |
| 110 | |
| 111 | /* Retain the 32b definitions for the time being - use bottom half of word */ |
| 112 | #define CPU_FTR_SPLIT_ID_CACHE ASM_CONST(0x0000000000000001) |
| 113 | #define CPU_FTR_L2CR ASM_CONST(0x0000000000000002) |
| 114 | #define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004) |
| 115 | #define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008) |
| 116 | #define CPU_FTR_TAU ASM_CONST(0x0000000000000010) |
| 117 | #define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020) |
| 118 | #define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040) |
| 119 | #define CPU_FTR_604_PERF_MON ASM_CONST(0x0000000000000080) |
| 120 | #define CPU_FTR_601 ASM_CONST(0x0000000000000100) |
| 121 | #define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200) |
| 122 | #define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400) |
| 123 | #define CPU_FTR_L3CR ASM_CONST(0x0000000000000800) |
| 124 | #define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000) |
| 125 | #define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000) |
| 126 | #define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000) |
| 127 | |
| 128 | /* Add the 64b processor unique features in the top half of the word */ |
| 129 | #define CPU_FTR_SLB ASM_CONST(0x0000000100000000) |
| 130 | #define CPU_FTR_16M_PAGE ASM_CONST(0x0000000200000000) |
| 131 | #define CPU_FTR_TLBIEL ASM_CONST(0x0000000400000000) |
| 132 | #define CPU_FTR_NOEXECUTE ASM_CONST(0x0000000800000000) |
| 133 | #define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000001000000000) |
| 134 | #define CPU_FTR_IABR ASM_CONST(0x0000002000000000) |
| 135 | #define CPU_FTR_MMCRA ASM_CONST(0x0000004000000000) |
| 136 | #define CPU_FTR_PMC8 ASM_CONST(0x0000008000000000) |
| 137 | #define CPU_FTR_SMT ASM_CONST(0x0000010000000000) |
| 138 | #define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000020000000000) |
| 139 | #define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0000040000000000) |
| 140 | #define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0000080000000000) |
Anton Blanchard | a2f7a9c | 2005-07-07 17:56:11 -0700 | [diff] [blame] | 141 | #define CPU_FTR_CTRL ASM_CONST(0x0000100000000000) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 142 | |
| 143 | /* Platform firmware features */ |
| 144 | #define FW_FTR_ ASM_CONST(0x0000000000000001) |
| 145 | |
| 146 | #ifndef __ASSEMBLY__ |
| 147 | #define COMMON_USER_PPC64 (PPC_FEATURE_32 | PPC_FEATURE_64 | \ |
| 148 | PPC_FEATURE_HAS_FPU | PPC_FEATURE_HAS_MMU) |
| 149 | |
| 150 | #define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \ |
| 151 | CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \ |
Anton Blanchard | a2f7a9c | 2005-07-07 17:56:11 -0700 | [diff] [blame] | 152 | CPU_FTR_NODSISRALIGN | CPU_FTR_CTRL) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 153 | |
| 154 | /* iSeries doesn't support large pages */ |
| 155 | #ifdef CONFIG_PPC_ISERIES |
| 156 | #define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE) |
| 157 | #else |
| 158 | #define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE | CPU_FTR_16M_PAGE) |
| 159 | #endif |
| 160 | |
| 161 | #define COMMON_PPC64_FW (0) |
| 162 | #endif |
| 163 | |
| 164 | #ifdef __ASSEMBLY__ |
| 165 | |
| 166 | #define BEGIN_FTR_SECTION 98: |
| 167 | |
| 168 | #define END_FTR_SECTION(msk, val) \ |
| 169 | 99: \ |
| 170 | .section __ftr_fixup,"a"; \ |
| 171 | .align 3; \ |
| 172 | .llong msk; \ |
| 173 | .llong val; \ |
| 174 | .llong 98b; \ |
| 175 | .llong 99b; \ |
| 176 | .previous |
| 177 | |
| 178 | #else |
| 179 | |
| 180 | #define BEGIN_FTR_SECTION "98:\n" |
| 181 | #define END_FTR_SECTION(msk, val) \ |
| 182 | "99:\n" \ |
| 183 | " .section __ftr_fixup,\"a\";\n" \ |
| 184 | " .align 3;\n" \ |
| 185 | " .llong "#msk";\n" \ |
| 186 | " .llong "#val";\n" \ |
| 187 | " .llong 98b;\n" \ |
| 188 | " .llong 99b;\n" \ |
| 189 | " .previous\n" |
| 190 | |
| 191 | #endif /* __ASSEMBLY__ */ |
| 192 | |
| 193 | #define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk)) |
| 194 | #define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0) |
| 195 | |
| 196 | #endif /* __ASM_PPC_CPUTABLE_H */ |
| 197 | #endif /* __KERNEL__ */ |
| 198 | |