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Mythri P K94c52982011-09-08 19:06:21 +05301/*
2 * ti_hdmi.h
3 *
4 * HDMI driver definition for TI OMAP4, DM81xx, DM38xx Processor.
5 *
6 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published by
10 * the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#ifndef _TI_HDMI_H
22#define _TI_HDMI_H
23
Mythri P K60634a22011-09-08 19:06:26 +053024struct hdmi_ip_data;
25
Mythri P K94c52982011-09-08 19:06:21 +053026enum hdmi_pll_pwr {
27 HDMI_PLLPWRCMD_ALLOFF = 0,
28 HDMI_PLLPWRCMD_PLLONLY = 1,
29 HDMI_PLLPWRCMD_BOTHON_ALLCLKS = 2,
30 HDMI_PLLPWRCMD_BOTHON_NOPHYCLK = 3
31};
32
33enum hdmi_core_hdmi_dvi {
34 HDMI_DVI = 0,
35 HDMI_HDMI = 1
36};
37
38enum hdmi_clk_refsel {
39 HDMI_REFSEL_PCLK = 0,
40 HDMI_REFSEL_REF1 = 1,
41 HDMI_REFSEL_REF2 = 2,
42 HDMI_REFSEL_SYSCLK = 3
43};
44
Mythri P Ka05ce782012-01-06 17:52:08 +053045/* HDMI timing structure */
Mythri P K94c52982011-09-08 19:06:21 +053046struct hdmi_video_timings {
47 u16 x_res;
48 u16 y_res;
49 /* Unit: KHz */
50 u32 pixel_clock;
51 u16 hsw;
52 u16 hfp;
53 u16 hbp;
54 u16 vsw;
55 u16 vfp;
56 u16 vbp;
Mythri P Ka05ce782012-01-06 17:52:08 +053057 bool vsync_pol;
58 bool hsync_pol;
59 bool interlace;
Mythri P K94c52982011-09-08 19:06:21 +053060};
61
62struct hdmi_cm {
63 int code;
64 int mode;
65};
66
67struct hdmi_config {
Mythri P Ka05ce782012-01-06 17:52:08 +053068 struct hdmi_video_timings timings;
Mythri P K94c52982011-09-08 19:06:21 +053069 struct hdmi_cm cm;
70};
71
72/* HDMI PLL structure */
73struct hdmi_pll_info {
74 u16 regn;
75 u16 regm;
76 u32 regmf;
77 u16 regm2;
78 u16 regsd;
79 u16 dcofreq;
80 enum hdmi_clk_refsel refsel;
81};
82
Mythri P K60634a22011-09-08 19:06:26 +053083struct ti_hdmi_ip_ops {
84
85 void (*video_configure)(struct hdmi_ip_data *ip_data);
86
87 int (*phy_enable)(struct hdmi_ip_data *ip_data);
88
89 void (*phy_disable)(struct hdmi_ip_data *ip_data);
90
Tomi Valkeinen937fce12011-08-31 11:12:40 +030091 int (*read_edid)(struct hdmi_ip_data *ip_data, u8 *edid, int len);
Mythri P K60634a22011-09-08 19:06:26 +053092
Tomi Valkeinen759593f2011-08-29 18:10:20 +030093 bool (*detect)(struct hdmi_ip_data *ip_data);
94
Mythri P K60634a22011-09-08 19:06:26 +053095 int (*pll_enable)(struct hdmi_ip_data *ip_data);
96
97 void (*pll_disable)(struct hdmi_ip_data *ip_data);
98
Ricardo Neric0456be2012-04-27 13:48:45 -050099 int (*video_enable)(struct hdmi_ip_data *ip_data);
100
101 void (*video_disable)(struct hdmi_ip_data *ip_data);
Mythri P K162874d2011-09-22 13:37:45 +0530102
103 void (*dump_wrapper)(struct hdmi_ip_data *ip_data, struct seq_file *s);
104
105 void (*dump_core)(struct hdmi_ip_data *ip_data, struct seq_file *s);
106
107 void (*dump_pll)(struct hdmi_ip_data *ip_data, struct seq_file *s);
108
109 void (*dump_phy)(struct hdmi_ip_data *ip_data, struct seq_file *s);
110
Ricardo Neri7e151f72012-03-15 14:08:03 -0600111#if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
Ricardo Neri027bdc82012-04-20 17:17:46 -0500112 int (*audio_enable)(struct hdmi_ip_data *ip_data);
113
114 void (*audio_disable)(struct hdmi_ip_data *ip_data);
Axel Castaneda Gonzalez3df9fb52012-05-03 09:00:21 -0500115
116 int (*audio_start)(struct hdmi_ip_data *ip_data);
117
118 void (*audio_stop)(struct hdmi_ip_data *ip_data);
Ricardo Neri6ec355d2012-03-21 12:38:15 -0600119
120 int (*audio_config)(struct hdmi_ip_data *ip_data,
121 struct omap_dss_audio *audio);
Ricardo Neri80a48592011-11-27 16:09:58 -0600122#endif
123
Mythri P K60634a22011-09-08 19:06:26 +0530124};
125
Mythri P Kda8f14f2012-02-08 11:54:19 +0530126/*
127 * Refer to section 8.2 in HDMI 1.3 specification for
128 * details about infoframe databytes
129 */
130struct hdmi_core_infoframe_avi {
131 /* Y0, Y1 rgb,yCbCr */
132 u8 db1_format;
133 /* A0 Active information Present */
134 u8 db1_active_info;
135 /* B0, B1 Bar info data valid */
136 u8 db1_bar_info_dv;
137 /* S0, S1 scan information */
138 u8 db1_scan_info;
139 /* C0, C1 colorimetry */
140 u8 db2_colorimetry;
141 /* M0, M1 Aspect ratio (4:3, 16:9) */
142 u8 db2_aspect_ratio;
143 /* R0...R3 Active format aspect ratio */
144 u8 db2_active_fmt_ar;
145 /* ITC IT content. */
146 u8 db3_itc;
147 /* EC0, EC1, EC2 Extended colorimetry */
148 u8 db3_ec;
149 /* Q1, Q0 Quantization range */
150 u8 db3_q_range;
151 /* SC1, SC0 Non-uniform picture scaling */
152 u8 db3_nup_scaling;
153 /* VIC0..6 Video format identification */
154 u8 db4_videocode;
155 /* PR0..PR3 Pixel repetition factor */
156 u8 db5_pixel_repeat;
157 /* Line number end of top bar */
158 u16 db6_7_line_eoftop;
159 /* Line number start of bottom bar */
160 u16 db8_9_line_sofbottom;
161 /* Pixel number end of left bar */
162 u16 db10_11_pixel_eofleft;
163 /* Pixel number start of right bar */
164 u16 db12_13_pixel_sofright;
165};
166
Mythri P K94c52982011-09-08 19:06:21 +0530167struct hdmi_ip_data {
168 void __iomem *base_wp; /* HDMI wrapper */
169 unsigned long core_sys_offset;
170 unsigned long core_av_offset;
171 unsigned long pll_offset;
172 unsigned long phy_offset;
Mythri P K60634a22011-09-08 19:06:26 +0530173 const struct ti_hdmi_ip_ops *ops;
Mythri P K94c52982011-09-08 19:06:21 +0530174 struct hdmi_config cfg;
175 struct hdmi_pll_info pll_data;
Mythri P Kda8f14f2012-02-08 11:54:19 +0530176 struct hdmi_core_infoframe_avi avi_cfg;
Tomi Valkeinenc49d0052012-01-17 11:09:57 +0200177
178 /* ti_hdmi_4xxx_ip private data. These should be in a separate struct */
179 int hpd_gpio;
180 bool phy_tx_enabled;
Mythri P K94c52982011-09-08 19:06:21 +0530181};
Mythri P K176b5782011-09-08 19:06:25 +0530182int ti_hdmi_4xxx_phy_enable(struct hdmi_ip_data *ip_data);
183void ti_hdmi_4xxx_phy_disable(struct hdmi_ip_data *ip_data);
Tomi Valkeinen937fce12011-08-31 11:12:40 +0300184int ti_hdmi_4xxx_read_edid(struct hdmi_ip_data *ip_data, u8 *edid, int len);
Tomi Valkeinen759593f2011-08-29 18:10:20 +0300185bool ti_hdmi_4xxx_detect(struct hdmi_ip_data *ip_data);
Ricardo Neric0456be2012-04-27 13:48:45 -0500186int ti_hdmi_4xxx_wp_video_start(struct hdmi_ip_data *ip_data);
187void ti_hdmi_4xxx_wp_video_stop(struct hdmi_ip_data *ip_data);
Mythri P K176b5782011-09-08 19:06:25 +0530188int ti_hdmi_4xxx_pll_enable(struct hdmi_ip_data *ip_data);
189void ti_hdmi_4xxx_pll_disable(struct hdmi_ip_data *ip_data);
190void ti_hdmi_4xxx_basic_configure(struct hdmi_ip_data *ip_data);
Mythri P K162874d2011-09-22 13:37:45 +0530191void ti_hdmi_4xxx_wp_dump(struct hdmi_ip_data *ip_data, struct seq_file *s);
192void ti_hdmi_4xxx_pll_dump(struct hdmi_ip_data *ip_data, struct seq_file *s);
193void ti_hdmi_4xxx_core_dump(struct hdmi_ip_data *ip_data, struct seq_file *s);
194void ti_hdmi_4xxx_phy_dump(struct hdmi_ip_data *ip_data, struct seq_file *s);
Ricardo Neri7e151f72012-03-15 14:08:03 -0600195#if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
Ricardo Neri35547622012-03-20 21:02:01 -0600196int hdmi_compute_acr(u32 sample_freq, u32 *n, u32 *cts);
Ricardo Neri027bdc82012-04-20 17:17:46 -0500197int ti_hdmi_4xxx_wp_audio_enable(struct hdmi_ip_data *ip_data);
198void ti_hdmi_4xxx_wp_audio_disable(struct hdmi_ip_data *ip_data);
Axel Castaneda Gonzalez3df9fb52012-05-03 09:00:21 -0500199int ti_hdmi_4xxx_audio_start(struct hdmi_ip_data *ip_data);
200void ti_hdmi_4xxx_audio_stop(struct hdmi_ip_data *ip_data);
Ricardo Neri6ec355d2012-03-21 12:38:15 -0600201int ti_hdmi_4xxx_audio_config(struct hdmi_ip_data *ip_data,
202 struct omap_dss_audio *audio);
Ricardo Neri80a48592011-11-27 16:09:58 -0600203#endif
Mythri P K94c52982011-09-08 19:06:21 +0530204#endif