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Binghua Duan02c981c2011-07-08 17:40:12 +08001/*
2 * System timer for CSR SiRFprimaII
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#include <linux/kernel.h>
10#include <linux/interrupt.h>
11#include <linux/clockchips.h>
12#include <linux/clocksource.h>
13#include <linux/bitops.h>
14#include <linux/irq.h>
15#include <linux/clk.h>
16#include <linux/err.h>
17#include <linux/slab.h>
18#include <linux/of.h>
Arnd Bergmann67d71342013-03-19 15:31:08 +010019#include <linux/of_irq.h>
Binghua Duan02c981c2011-07-08 17:40:12 +080020#include <linux/of_address.h>
Stephen Boyd38ff87f2013-06-01 23:39:40 -070021#include <linux/sched_clock.h>
Binghua Duan02c981c2011-07-08 17:40:12 +080022
Uwe Kleine-König980c51a2013-11-11 21:06:11 +010023#define PRIMA2_CLOCK_FREQ 1000000
24
Binghua Duan02c981c2011-07-08 17:40:12 +080025#define SIRFSOC_TIMER_COUNTER_LO 0x0000
26#define SIRFSOC_TIMER_COUNTER_HI 0x0004
27#define SIRFSOC_TIMER_MATCH_0 0x0008
28#define SIRFSOC_TIMER_MATCH_1 0x000C
29#define SIRFSOC_TIMER_MATCH_2 0x0010
30#define SIRFSOC_TIMER_MATCH_3 0x0014
31#define SIRFSOC_TIMER_MATCH_4 0x0018
32#define SIRFSOC_TIMER_MATCH_5 0x001C
33#define SIRFSOC_TIMER_STATUS 0x0020
34#define SIRFSOC_TIMER_INT_EN 0x0024
35#define SIRFSOC_TIMER_WATCHDOG_EN 0x0028
36#define SIRFSOC_TIMER_DIV 0x002C
37#define SIRFSOC_TIMER_LATCH 0x0030
38#define SIRFSOC_TIMER_LATCHED_LO 0x0034
39#define SIRFSOC_TIMER_LATCHED_HI 0x0038
40
41#define SIRFSOC_TIMER_WDT_INDEX 5
42
43#define SIRFSOC_TIMER_LATCH_BIT BIT(0)
44
Barry Songe5598a82011-09-21 20:56:33 +080045#define SIRFSOC_TIMER_REG_CNT 11
46
47static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = {
48 SIRFSOC_TIMER_MATCH_0, SIRFSOC_TIMER_MATCH_1, SIRFSOC_TIMER_MATCH_2,
49 SIRFSOC_TIMER_MATCH_3, SIRFSOC_TIMER_MATCH_4, SIRFSOC_TIMER_MATCH_5,
50 SIRFSOC_TIMER_INT_EN, SIRFSOC_TIMER_WATCHDOG_EN, SIRFSOC_TIMER_DIV,
51 SIRFSOC_TIMER_LATCHED_LO, SIRFSOC_TIMER_LATCHED_HI,
52};
53
54static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT];
55
Binghua Duan02c981c2011-07-08 17:40:12 +080056static void __iomem *sirfsoc_timer_base;
Binghua Duan02c981c2011-07-08 17:40:12 +080057
58/* timer0 interrupt handler */
59static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id)
60{
61 struct clock_event_device *ce = dev_id;
62
Bin Shi4c1ad702014-05-06 22:42:29 +080063 WARN_ON(!(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_STATUS) &
64 BIT(0)));
Binghua Duan02c981c2011-07-08 17:40:12 +080065
66 /* clear timer0 interrupt */
67 writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS);
68
69 ce->event_handler(ce);
70
71 return IRQ_HANDLED;
72}
73
74/* read 64-bit timer counter */
Thomas Gleixnera5a1d1c2016-12-21 20:32:01 +010075static u64 notrace sirfsoc_timer_read(struct clocksource *cs)
Binghua Duan02c981c2011-07-08 17:40:12 +080076{
77 u64 cycles;
78
79 /* latch the 64-bit timer counter */
Bin Shi4c1ad702014-05-06 22:42:29 +080080 writel_relaxed(SIRFSOC_TIMER_LATCH_BIT,
81 sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
Binghua Duan02c981c2011-07-08 17:40:12 +080082 cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_HI);
Bin Shi4c1ad702014-05-06 22:42:29 +080083 cycles = (cycles << 32) |
84 readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
Binghua Duan02c981c2011-07-08 17:40:12 +080085
86 return cycles;
87}
88
89static int sirfsoc_timer_set_next_event(unsigned long delta,
90 struct clock_event_device *ce)
91{
92 unsigned long now, next;
93
Bin Shi4c1ad702014-05-06 22:42:29 +080094 writel_relaxed(SIRFSOC_TIMER_LATCH_BIT,
95 sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
Binghua Duan02c981c2011-07-08 17:40:12 +080096 now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
97 next = now + delta;
98 writel_relaxed(next, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0);
Bin Shi4c1ad702014-05-06 22:42:29 +080099 writel_relaxed(SIRFSOC_TIMER_LATCH_BIT,
100 sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
Binghua Duan02c981c2011-07-08 17:40:12 +0800101 now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
102
103 return next - now > delta ? -ETIME : 0;
104}
105
Viresh Kumar53cba062015-06-18 16:24:49 +0530106static int sirfsoc_timer_shutdown(struct clock_event_device *evt)
Binghua Duan02c981c2011-07-08 17:40:12 +0800107{
108 u32 val = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
Viresh Kumar53cba062015-06-18 16:24:49 +0530109
110 writel_relaxed(val & ~BIT(0),
111 sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
112 return 0;
113}
114
115static int sirfsoc_timer_set_oneshot(struct clock_event_device *evt)
116{
117 u32 val = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
118
119 writel_relaxed(val | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
120 return 0;
Binghua Duan02c981c2011-07-08 17:40:12 +0800121}
122
Barry Songe5598a82011-09-21 20:56:33 +0800123static void sirfsoc_clocksource_suspend(struct clocksource *cs)
124{
125 int i;
126
Bin Shi4c1ad702014-05-06 22:42:29 +0800127 writel_relaxed(SIRFSOC_TIMER_LATCH_BIT,
128 sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
Barry Songe5598a82011-09-21 20:56:33 +0800129
130 for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++)
Bin Shi4c1ad702014-05-06 22:42:29 +0800131 sirfsoc_timer_reg_val[i] =
132 readl_relaxed(sirfsoc_timer_base +
133 sirfsoc_timer_reg_list[i]);
Barry Songe5598a82011-09-21 20:56:33 +0800134}
135
136static void sirfsoc_clocksource_resume(struct clocksource *cs)
137{
138 int i;
139
Barry Songdebeaf62012-07-30 13:29:30 +0800140 for (i = 0; i < SIRFSOC_TIMER_REG_CNT - 2; i++)
Bin Shi4c1ad702014-05-06 22:42:29 +0800141 writel_relaxed(sirfsoc_timer_reg_val[i],
142 sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
Barry Songe5598a82011-09-21 20:56:33 +0800143
Bin Shi4c1ad702014-05-06 22:42:29 +0800144 writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2],
145 sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO);
146 writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1],
147 sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI);
Barry Songe5598a82011-09-21 20:56:33 +0800148}
149
Binghua Duan02c981c2011-07-08 17:40:12 +0800150static struct clock_event_device sirfsoc_clockevent = {
151 .name = "sirfsoc_clockevent",
152 .rating = 200,
153 .features = CLOCK_EVT_FEAT_ONESHOT,
Viresh Kumar53cba062015-06-18 16:24:49 +0530154 .set_state_shutdown = sirfsoc_timer_shutdown,
155 .set_state_oneshot = sirfsoc_timer_set_oneshot,
Binghua Duan02c981c2011-07-08 17:40:12 +0800156 .set_next_event = sirfsoc_timer_set_next_event,
157};
158
159static struct clocksource sirfsoc_clocksource = {
160 .name = "sirfsoc_clocksource",
161 .rating = 200,
162 .mask = CLOCKSOURCE_MASK(64),
163 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
164 .read = sirfsoc_timer_read,
Barry Songe5598a82011-09-21 20:56:33 +0800165 .suspend = sirfsoc_clocksource_suspend,
166 .resume = sirfsoc_clocksource_resume,
Binghua Duan02c981c2011-07-08 17:40:12 +0800167};
168
169static struct irqaction sirfsoc_timer_irq = {
170 .name = "sirfsoc_timer0",
171 .flags = IRQF_TIMER,
172 .irq = 0,
173 .handler = sirfsoc_timer_interrupt,
174 .dev_id = &sirfsoc_clockevent,
175};
176
177/* Overwrite weak default sched_clock with more precise one */
Stephen Boyd130e6b252013-07-18 16:21:28 -0700178static u64 notrace sirfsoc_read_sched_clock(void)
Binghua Duan02c981c2011-07-08 17:40:12 +0800179{
Stephen Boyd130e6b252013-07-18 16:21:28 -0700180 return sirfsoc_timer_read(NULL);
Binghua Duan02c981c2011-07-08 17:40:12 +0800181}
182
183static void __init sirfsoc_clockevent_init(void)
184{
Binghua Duan02c981c2011-07-08 17:40:12 +0800185 sirfsoc_clockevent.cpumask = cpumask_of(0);
Uwe Kleine-König980c51a2013-11-11 21:06:11 +0100186 clockevents_config_and_register(&sirfsoc_clockevent, PRIMA2_CLOCK_FREQ,
Shawn Guo838a2ae2013-01-12 11:50:05 +0000187 2, -2);
Binghua Duan02c981c2011-07-08 17:40:12 +0800188}
189
190/* initialize the kernel jiffy timer source */
Daniel Lezcanode234842016-06-06 23:02:59 +0200191static int __init sirfsoc_prima2_timer_init(struct device_node *np)
Binghua Duan02c981c2011-07-08 17:40:12 +0800192{
193 unsigned long rate;
Binghua Duan198678b2012-08-20 06:42:36 +0000194 struct clk *clk;
Daniel Lezcanode234842016-06-06 23:02:59 +0200195 int ret;
Binghua Duan198678b2012-08-20 06:42:36 +0000196
Zhiwu Songc7cff542014-05-05 19:30:04 +0800197 clk = of_clk_get(np, 0);
Daniel Lezcanode234842016-06-06 23:02:59 +0200198 if (IS_ERR(clk)) {
Rafał Miłeckiac9ce6d2017-03-09 10:47:10 +0100199 pr_err("Failed to get clock\n");
Daniel Lezcanode234842016-06-06 23:02:59 +0200200 return PTR_ERR(clk);
201 }
Zhiwu Song38941522014-07-03 20:52:51 +0800202
Daniel Lezcanode234842016-06-06 23:02:59 +0200203 ret = clk_prepare_enable(clk);
204 if (ret) {
Rafał Miłeckiac9ce6d2017-03-09 10:47:10 +0100205 pr_err("Failed to enable clock\n");
Daniel Lezcanode234842016-06-06 23:02:59 +0200206 return ret;
207 }
Zhiwu Song38941522014-07-03 20:52:51 +0800208
Binghua Duan02c981c2011-07-08 17:40:12 +0800209 rate = clk_get_rate(clk);
210
Daniel Lezcanode234842016-06-06 23:02:59 +0200211 if (rate < PRIMA2_CLOCK_FREQ || rate % PRIMA2_CLOCK_FREQ) {
Rafał Miłeckiac9ce6d2017-03-09 10:47:10 +0100212 pr_err("Invalid clock rate\n");
Daniel Lezcanode234842016-06-06 23:02:59 +0200213 return -EINVAL;
214 }
Binghua Duan02c981c2011-07-08 17:40:12 +0800215
Arnd Bergmann275786b2013-03-19 15:27:22 +0100216 sirfsoc_timer_base = of_iomap(np, 0);
Daniel Lezcanode234842016-06-06 23:02:59 +0200217 if (!sirfsoc_timer_base) {
218 pr_err("unable to map timer cpu registers\n");
219 return -ENXIO;
220 }
Arnd Bergmann275786b2013-03-19 15:27:22 +0100221
222 sirfsoc_timer_irq.irq = irq_of_parse_and_map(np, 0);
Marc Zyngierbc8d8492012-01-16 11:44:12 +0000223
Uwe Kleine-König980c51a2013-11-11 21:06:11 +0100224 writel_relaxed(rate / PRIMA2_CLOCK_FREQ / 2 - 1,
Bin Shi4c1ad702014-05-06 22:42:29 +0800225 sirfsoc_timer_base + SIRFSOC_TIMER_DIV);
Binghua Duan02c981c2011-07-08 17:40:12 +0800226 writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO);
227 writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI);
228 writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS);
229
Daniel Lezcanode234842016-06-06 23:02:59 +0200230 ret = clocksource_register_hz(&sirfsoc_clocksource, PRIMA2_CLOCK_FREQ);
231 if (ret) {
Rafał Miłeckiac9ce6d2017-03-09 10:47:10 +0100232 pr_err("Failed to register clocksource\n");
Daniel Lezcanode234842016-06-06 23:02:59 +0200233 return ret;
234 }
Binghua Duan02c981c2011-07-08 17:40:12 +0800235
Uwe Kleine-König980c51a2013-11-11 21:06:11 +0100236 sched_clock_register(sirfsoc_read_sched_clock, 64, PRIMA2_CLOCK_FREQ);
Marc Zyngierbc8d8492012-01-16 11:44:12 +0000237
Daniel Lezcanode234842016-06-06 23:02:59 +0200238 ret = setup_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq);
239 if (ret) {
Rafał Miłeckiac9ce6d2017-03-09 10:47:10 +0100240 pr_err("Failed to setup irq\n");
Daniel Lezcanode234842016-06-06 23:02:59 +0200241 return ret;
242 }
Binghua Duan02c981c2011-07-08 17:40:12 +0800243
244 sirfsoc_clockevent_init();
Daniel Lezcanode234842016-06-06 23:02:59 +0200245
246 return 0;
Binghua Duan02c981c2011-07-08 17:40:12 +0800247}
Daniel Lezcano17273392017-05-26 16:56:11 +0200248TIMER_OF_DECLARE(sirfsoc_prima2_timer,
Bin Shi4c1ad702014-05-06 22:42:29 +0800249 "sirf,prima2-tick", sirfsoc_prima2_timer_init);