Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 1 | /* |
| 2 | * pata_mpiix.c - Intel MPIIX PATA for new ATA layer |
| 3 | * (C) 2005-2006 Red Hat Inc |
| 4 | * Alan Cox <alan@redhat.com> |
| 5 | * |
| 6 | * The MPIIX is different enough to the PIIX4 and friends that we give it |
| 7 | * a separate driver. The old ide/pci code handles this by just not tuning |
| 8 | * MPIIX at all. |
| 9 | * |
| 10 | * The MPIIX also differs in another important way from the majority of PIIX |
| 11 | * devices. The chip is a bridge (pardon the pun) between the old world of |
| 12 | * ISA IDE and PCI IDE. Although the ATA timings are PCI configured the actual |
| 13 | * IDE controller is not decoded in PCI space and the chip does not claim to |
| 14 | * be IDE class PCI. This requires slightly non-standard probe logic compared |
| 15 | * with PCI IDE and also that we do not disable the device when our driver is |
| 16 | * unloaded (as it has many other functions). |
| 17 | * |
| 18 | * The driver conciously keeps this logic internally to avoid pushing quirky |
| 19 | * PATA history into the clean libata layer. |
| 20 | * |
Alan Cox | c961922 | 2006-09-26 17:53:38 +0100 | [diff] [blame] | 21 | * Thinkpad specific note: If you boot an MPIIX using a thinkpad with a PCMCIA |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 22 | * hard disk present this driver will not detect it. This is not a bug. In this |
| 23 | * configuration the secondary port of the MPIIX is disabled and the addresses |
| 24 | * are decoded by the PCMCIA bridge and therefore are for a generic IDE driver |
| 25 | * to operate. |
| 26 | */ |
| 27 | |
| 28 | #include <linux/kernel.h> |
| 29 | #include <linux/module.h> |
| 30 | #include <linux/pci.h> |
| 31 | #include <linux/init.h> |
| 32 | #include <linux/blkdev.h> |
| 33 | #include <linux/delay.h> |
| 34 | #include <scsi/scsi_host.h> |
| 35 | #include <linux/libata.h> |
| 36 | |
| 37 | #define DRV_NAME "pata_mpiix" |
Jeff Garzik | a0fcdc0 | 2007-03-09 07:24:15 -0500 | [diff] [blame] | 38 | #define DRV_VERSION "0.7.6" |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 39 | |
| 40 | enum { |
| 41 | IDETIM = 0x6C, /* IDE control register */ |
| 42 | IORDY = (1 << 1), |
| 43 | PPE = (1 << 2), |
| 44 | FTIM = (1 << 0), |
| 45 | ENABLED = (1 << 15), |
| 46 | SECONDARY = (1 << 14) |
| 47 | }; |
| 48 | |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 49 | static int mpiix_pre_reset(struct ata_link *link, unsigned long deadline) |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 50 | { |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 51 | struct ata_port *ap = link->ap; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 52 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
Sergei Shtylyov | 92ae784 | 2007-02-05 21:08:55 +0300 | [diff] [blame] | 53 | static const struct pci_bits mpiix_enable_bits = { 0x6D, 1, 0x80, 0x80 }; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 54 | |
Sergei Shtylyov | 92ae784 | 2007-02-05 21:08:55 +0300 | [diff] [blame] | 55 | if (!pci_test_config_bits(pdev, &mpiix_enable_bits)) |
Alan Cox | c961922 | 2006-09-26 17:53:38 +0100 | [diff] [blame] | 56 | return -ENOENT; |
Tejun Heo | d4b2bab | 2007-02-02 16:50:52 +0900 | [diff] [blame] | 57 | |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 58 | return ata_std_prereset(link, deadline); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 59 | } |
| 60 | |
| 61 | /** |
| 62 | * mpiix_error_handler - probe reset |
| 63 | * @ap: ATA port |
| 64 | * |
| 65 | * Perform the ATA probe and bus reset sequence plus specific handling |
| 66 | * for this hardware. The MPIIX has the enable bits in a different place |
| 67 | * to PIIX4 and friends. As a pure PIO device it has no cable detect |
| 68 | */ |
| 69 | |
| 70 | static void mpiix_error_handler(struct ata_port *ap) |
| 71 | { |
| 72 | ata_bmdma_drive_eh(ap, mpiix_pre_reset, ata_std_softreset, NULL, ata_std_postreset); |
| 73 | } |
| 74 | |
| 75 | /** |
| 76 | * mpiix_set_piomode - set initial PIO mode data |
| 77 | * @ap: ATA interface |
| 78 | * @adev: ATA device |
| 79 | * |
| 80 | * Called to do the PIO mode setup. The MPIIX allows us to program the |
Sergei Shtylyov | 7b4f1a1 | 2007-02-05 20:24:57 +0300 | [diff] [blame] | 81 | * IORDY sample point (2-5 clocks), recovery (1-4 clocks) and whether |
| 82 | * prefetching or IORDY are used. |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 83 | * |
| 84 | * This would get very ugly because we can only program timing for one |
| 85 | * device at a time, the other gets PIO0. Fortunately libata calls |
| 86 | * our qc_issue_prot command before a command is issued so we can |
| 87 | * flip the timings back and forth to reduce the pain. |
| 88 | */ |
| 89 | |
| 90 | static void mpiix_set_piomode(struct ata_port *ap, struct ata_device *adev) |
| 91 | { |
| 92 | int control = 0; |
| 93 | int pio = adev->pio_mode - XFER_PIO_0; |
| 94 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
| 95 | u16 idetim; |
| 96 | static const /* ISP RTC */ |
| 97 | u8 timings[][2] = { { 0, 0 }, |
| 98 | { 0, 0 }, |
| 99 | { 1, 0 }, |
| 100 | { 2, 1 }, |
| 101 | { 2, 3 }, }; |
| 102 | |
| 103 | pci_read_config_word(pdev, IDETIM, &idetim); |
Sergei Shtylyov | 7b4f1a1 | 2007-02-05 20:24:57 +0300 | [diff] [blame] | 104 | |
| 105 | /* Mask the IORDY/TIME/PPE for this device */ |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 106 | if (adev->class == ATA_DEV_ATA) |
Sergei Shtylyov | 7b4f1a1 | 2007-02-05 20:24:57 +0300 | [diff] [blame] | 107 | control |= PPE; /* Enable prefetch/posting for disk */ |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 108 | if (ata_pio_need_iordy(adev)) |
Sergei Shtylyov | 7b4f1a1 | 2007-02-05 20:24:57 +0300 | [diff] [blame] | 109 | control |= IORDY; |
| 110 | if (pio > 1) |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 111 | control |= FTIM; /* This drive is on the fast timing bank */ |
| 112 | |
| 113 | /* Mask out timing and clear both TIME bank selects */ |
| 114 | idetim &= 0xCCEE; |
Sergei Shtylyov | 7b4f1a1 | 2007-02-05 20:24:57 +0300 | [diff] [blame] | 115 | idetim &= ~(0x07 << (4 * adev->devno)); |
| 116 | idetim |= control << (4 * adev->devno); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 117 | |
| 118 | idetim |= (timings[pio][0] << 12) | (timings[pio][1] << 8); |
| 119 | pci_write_config_word(pdev, IDETIM, idetim); |
| 120 | |
| 121 | /* We use ap->private_data as a pointer to the device currently |
| 122 | loaded for timing */ |
| 123 | ap->private_data = adev; |
| 124 | } |
| 125 | |
| 126 | /** |
| 127 | * mpiix_qc_issue_prot - command issue |
| 128 | * @qc: command pending |
| 129 | * |
| 130 | * Called when the libata layer is about to issue a command. We wrap |
| 131 | * this interface so that we can load the correct ATA timings if |
| 132 | * neccessary. Our logic also clears TIME0/TIME1 for the other device so |
| 133 | * that, even if we get this wrong, cycles to the other device will |
| 134 | * be made PIO0. |
| 135 | */ |
| 136 | |
| 137 | static unsigned int mpiix_qc_issue_prot(struct ata_queued_cmd *qc) |
| 138 | { |
| 139 | struct ata_port *ap = qc->ap; |
| 140 | struct ata_device *adev = qc->dev; |
| 141 | |
| 142 | /* If modes have been configured and the channel data is not loaded |
| 143 | then load it. We have to check if pio_mode is set as the core code |
| 144 | does not set adev->pio_mode to XFER_PIO_0 while probing as would be |
| 145 | logical */ |
| 146 | |
| 147 | if (adev->pio_mode && adev != ap->private_data) |
| 148 | mpiix_set_piomode(ap, adev); |
| 149 | |
| 150 | return ata_qc_issue_prot(qc); |
| 151 | } |
| 152 | |
| 153 | static struct scsi_host_template mpiix_sht = { |
| 154 | .module = THIS_MODULE, |
| 155 | .name = DRV_NAME, |
| 156 | .ioctl = ata_scsi_ioctl, |
| 157 | .queuecommand = ata_scsi_queuecmd, |
| 158 | .can_queue = ATA_DEF_QUEUE, |
| 159 | .this_id = ATA_SHT_THIS_ID, |
| 160 | .sg_tablesize = LIBATA_MAX_PRD, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 161 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
| 162 | .emulated = ATA_SHT_EMULATED, |
| 163 | .use_clustering = ATA_SHT_USE_CLUSTERING, |
| 164 | .proc_name = DRV_NAME, |
| 165 | .dma_boundary = ATA_DMA_BOUNDARY, |
| 166 | .slave_configure = ata_scsi_slave_config, |
Tejun Heo | afdfe89 | 2006-11-29 11:26:47 +0900 | [diff] [blame] | 167 | .slave_destroy = ata_scsi_slave_destroy, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 168 | .bios_param = ata_std_bios_param, |
| 169 | }; |
| 170 | |
| 171 | static struct ata_port_operations mpiix_port_ops = { |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 172 | .set_piomode = mpiix_set_piomode, |
| 173 | |
| 174 | .tf_load = ata_tf_load, |
| 175 | .tf_read = ata_tf_read, |
| 176 | .check_status = ata_check_status, |
| 177 | .exec_command = ata_exec_command, |
| 178 | .dev_select = ata_std_dev_select, |
| 179 | |
| 180 | .freeze = ata_bmdma_freeze, |
| 181 | .thaw = ata_bmdma_thaw, |
| 182 | .error_handler = mpiix_error_handler, |
| 183 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
Jeff Garzik | a0fcdc0 | 2007-03-09 07:24:15 -0500 | [diff] [blame] | 184 | .cable_detect = ata_cable_40wire, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 185 | |
| 186 | .qc_prep = ata_qc_prep, |
| 187 | .qc_issue = mpiix_qc_issue_prot, |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 188 | .data_xfer = ata_data_xfer, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 189 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 190 | .irq_clear = ata_bmdma_irq_clear, |
Akira Iguchi | 246ce3b | 2007-01-26 16:27:58 +0900 | [diff] [blame] | 191 | .irq_on = ata_irq_on, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 192 | |
Alan Cox | 81ad183 | 2007-08-22 22:55:41 +0100 | [diff] [blame] | 193 | .port_start = ata_sff_port_start, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 194 | }; |
| 195 | |
| 196 | static int mpiix_init_one(struct pci_dev *dev, const struct pci_device_id *id) |
| 197 | { |
| 198 | /* Single threaded by the PCI probe logic */ |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 199 | static int printed_version; |
Tejun Heo | 5d72882 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 200 | struct ata_host *host; |
| 201 | struct ata_port *ap; |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 202 | void __iomem *cmd_addr, *ctl_addr; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 203 | u16 idetim; |
Tejun Heo | cbcdd87 | 2007-08-18 13:14:55 +0900 | [diff] [blame] | 204 | int cmd, ctl, irq; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 205 | |
| 206 | if (!printed_version++) |
| 207 | dev_printk(KERN_DEBUG, &dev->dev, "version " DRV_VERSION "\n"); |
| 208 | |
Tejun Heo | 5d72882 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 209 | host = ata_host_alloc(&dev->dev, 1); |
| 210 | if (!host) |
| 211 | return -ENOMEM; |
Tejun Heo | cbcdd87 | 2007-08-18 13:14:55 +0900 | [diff] [blame] | 212 | ap = host->ports[0]; |
Tejun Heo | 5d72882 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 213 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 214 | /* MPIIX has many functions which can be turned on or off according |
| 215 | to other devices present. Make sure IDE is enabled before we try |
| 216 | and use it */ |
| 217 | |
| 218 | pci_read_config_word(dev, IDETIM, &idetim); |
| 219 | if (!(idetim & ENABLED)) |
| 220 | return -ENODEV; |
| 221 | |
Sergei Shtylyov | 92ae784 | 2007-02-05 21:08:55 +0300 | [diff] [blame] | 222 | /* See if it's primary or secondary channel... */ |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 223 | if (!(idetim & SECONDARY)) { |
Tejun Heo | cbcdd87 | 2007-08-18 13:14:55 +0900 | [diff] [blame] | 224 | cmd = 0x1F0; |
| 225 | ctl = 0x3F6; |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 226 | irq = 14; |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 227 | } else { |
Tejun Heo | cbcdd87 | 2007-08-18 13:14:55 +0900 | [diff] [blame] | 228 | cmd = 0x170; |
| 229 | ctl = 0x376; |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 230 | irq = 15; |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 231 | } |
| 232 | |
Tejun Heo | cbcdd87 | 2007-08-18 13:14:55 +0900 | [diff] [blame] | 233 | cmd_addr = devm_ioport_map(&dev->dev, cmd, 8); |
| 234 | ctl_addr = devm_ioport_map(&dev->dev, ctl, 1); |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 235 | if (!cmd_addr || !ctl_addr) |
| 236 | return -ENOMEM; |
| 237 | |
Tejun Heo | cbcdd87 | 2007-08-18 13:14:55 +0900 | [diff] [blame] | 238 | ata_port_desc(ap, "cmd 0x%x ctl 0x%x", cmd, ctl); |
| 239 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 240 | /* We do our own plumbing to avoid leaking special cases for whacko |
| 241 | ancient hardware into the core code. There are two issues to |
| 242 | worry about. #1 The chip is a bridge so if in legacy mode and |
| 243 | without BARs set fools the setup. #2 If you pci_disable_device |
| 244 | the MPIIX your box goes castors up */ |
| 245 | |
Tejun Heo | 5d72882 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 246 | ap->ops = &mpiix_port_ops; |
| 247 | ap->pio_mask = 0x1F; |
| 248 | ap->flags |= ATA_FLAG_SLAVE_POSS; |
Sergei Shtylyov | 92ae784 | 2007-02-05 21:08:55 +0300 | [diff] [blame] | 249 | |
Tejun Heo | 5d72882 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 250 | ap->ioaddr.cmd_addr = cmd_addr; |
| 251 | ap->ioaddr.ctl_addr = ctl_addr; |
| 252 | ap->ioaddr.altstatus_addr = ctl_addr; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 253 | |
| 254 | /* Let libata fill in the port details */ |
Tejun Heo | 5d72882 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 255 | ata_std_ports(&ap->ioaddr); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 256 | |
Tejun Heo | 5d72882 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 257 | /* activate host */ |
| 258 | return ata_host_activate(host, irq, ata_interrupt, IRQF_SHARED, |
| 259 | &mpiix_sht); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 260 | } |
| 261 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 262 | static const struct pci_device_id mpiix[] = { |
Jeff Garzik | 2d2744f | 2006-09-28 20:21:59 -0400 | [diff] [blame] | 263 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371MX), }, |
| 264 | |
| 265 | { }, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 266 | }; |
| 267 | |
| 268 | static struct pci_driver mpiix_pci_driver = { |
| 269 | .name = DRV_NAME, |
| 270 | .id_table = mpiix, |
| 271 | .probe = mpiix_init_one, |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 272 | .remove = ata_pci_remove_one, |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 273 | #ifdef CONFIG_PM |
Alan | 30ced0f | 2006-11-22 16:57:36 +0000 | [diff] [blame] | 274 | .suspend = ata_pci_device_suspend, |
| 275 | .resume = ata_pci_device_resume, |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 276 | #endif |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 277 | }; |
| 278 | |
| 279 | static int __init mpiix_init(void) |
| 280 | { |
| 281 | return pci_register_driver(&mpiix_pci_driver); |
| 282 | } |
| 283 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 284 | static void __exit mpiix_exit(void) |
| 285 | { |
| 286 | pci_unregister_driver(&mpiix_pci_driver); |
| 287 | } |
| 288 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 289 | MODULE_AUTHOR("Alan Cox"); |
| 290 | MODULE_DESCRIPTION("low-level driver for Intel MPIIX"); |
| 291 | MODULE_LICENSE("GPL"); |
| 292 | MODULE_DEVICE_TABLE(pci, mpiix); |
| 293 | MODULE_VERSION(DRV_VERSION); |
| 294 | |
| 295 | module_init(mpiix_init); |
| 296 | module_exit(mpiix_exit); |