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Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001/*
2 * Driver for the Atmel Extensible DMA Controller (aka XDMAC on AT91 systems)
3 *
4 * Copyright (C) 2014 Atmel Corporation
5 *
6 * Author: Ludovic Desroches <ludovic.desroches@atmel.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published by
10 * the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#include <asm/barrier.h>
22#include <dt-bindings/dma/at91.h>
23#include <linux/clk.h>
24#include <linux/dmaengine.h>
25#include <linux/dmapool.h>
26#include <linux/interrupt.h>
27#include <linux/irq.h>
Ludovic Desroches6d3a7d92015-01-27 16:30:32 +010028#include <linux/kernel.h>
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +020029#include <linux/list.h>
30#include <linux/module.h>
31#include <linux/of_dma.h>
32#include <linux/of_platform.h>
33#include <linux/platform_device.h>
34#include <linux/pm.h>
35
36#include "dmaengine.h"
37
38/* Global registers */
39#define AT_XDMAC_GTYPE 0x00 /* Global Type Register */
40#define AT_XDMAC_NB_CH(i) (((i) & 0x1F) + 1) /* Number of Channels Minus One */
41#define AT_XDMAC_FIFO_SZ(i) (((i) >> 5) & 0x7FF) /* Number of Bytes */
42#define AT_XDMAC_NB_REQ(i) ((((i) >> 16) & 0x3F) + 1) /* Number of Peripheral Requests Minus One */
43#define AT_XDMAC_GCFG 0x04 /* Global Configuration Register */
44#define AT_XDMAC_GWAC 0x08 /* Global Weighted Arbiter Configuration Register */
45#define AT_XDMAC_GIE 0x0C /* Global Interrupt Enable Register */
46#define AT_XDMAC_GID 0x10 /* Global Interrupt Disable Register */
47#define AT_XDMAC_GIM 0x14 /* Global Interrupt Mask Register */
48#define AT_XDMAC_GIS 0x18 /* Global Interrupt Status Register */
49#define AT_XDMAC_GE 0x1C /* Global Channel Enable Register */
50#define AT_XDMAC_GD 0x20 /* Global Channel Disable Register */
51#define AT_XDMAC_GS 0x24 /* Global Channel Status Register */
52#define AT_XDMAC_GRS 0x28 /* Global Channel Read Suspend Register */
53#define AT_XDMAC_GWS 0x2C /* Global Write Suspend Register */
54#define AT_XDMAC_GRWS 0x30 /* Global Channel Read Write Suspend Register */
55#define AT_XDMAC_GRWR 0x34 /* Global Channel Read Write Resume Register */
56#define AT_XDMAC_GSWR 0x38 /* Global Channel Software Request Register */
57#define AT_XDMAC_GSWS 0x3C /* Global channel Software Request Status Register */
58#define AT_XDMAC_GSWF 0x40 /* Global Channel Software Flush Request Register */
59#define AT_XDMAC_VERSION 0xFFC /* XDMAC Version Register */
60
61/* Channel relative registers offsets */
62#define AT_XDMAC_CIE 0x00 /* Channel Interrupt Enable Register */
63#define AT_XDMAC_CIE_BIE BIT(0) /* End of Block Interrupt Enable Bit */
64#define AT_XDMAC_CIE_LIE BIT(1) /* End of Linked List Interrupt Enable Bit */
65#define AT_XDMAC_CIE_DIE BIT(2) /* End of Disable Interrupt Enable Bit */
66#define AT_XDMAC_CIE_FIE BIT(3) /* End of Flush Interrupt Enable Bit */
67#define AT_XDMAC_CIE_RBEIE BIT(4) /* Read Bus Error Interrupt Enable Bit */
68#define AT_XDMAC_CIE_WBEIE BIT(5) /* Write Bus Error Interrupt Enable Bit */
69#define AT_XDMAC_CIE_ROIE BIT(6) /* Request Overflow Interrupt Enable Bit */
70#define AT_XDMAC_CID 0x04 /* Channel Interrupt Disable Register */
71#define AT_XDMAC_CID_BID BIT(0) /* End of Block Interrupt Disable Bit */
72#define AT_XDMAC_CID_LID BIT(1) /* End of Linked List Interrupt Disable Bit */
73#define AT_XDMAC_CID_DID BIT(2) /* End of Disable Interrupt Disable Bit */
74#define AT_XDMAC_CID_FID BIT(3) /* End of Flush Interrupt Disable Bit */
75#define AT_XDMAC_CID_RBEID BIT(4) /* Read Bus Error Interrupt Disable Bit */
76#define AT_XDMAC_CID_WBEID BIT(5) /* Write Bus Error Interrupt Disable Bit */
77#define AT_XDMAC_CID_ROID BIT(6) /* Request Overflow Interrupt Disable Bit */
78#define AT_XDMAC_CIM 0x08 /* Channel Interrupt Mask Register */
79#define AT_XDMAC_CIM_BIM BIT(0) /* End of Block Interrupt Mask Bit */
80#define AT_XDMAC_CIM_LIM BIT(1) /* End of Linked List Interrupt Mask Bit */
81#define AT_XDMAC_CIM_DIM BIT(2) /* End of Disable Interrupt Mask Bit */
82#define AT_XDMAC_CIM_FIM BIT(3) /* End of Flush Interrupt Mask Bit */
83#define AT_XDMAC_CIM_RBEIM BIT(4) /* Read Bus Error Interrupt Mask Bit */
84#define AT_XDMAC_CIM_WBEIM BIT(5) /* Write Bus Error Interrupt Mask Bit */
85#define AT_XDMAC_CIM_ROIM BIT(6) /* Request Overflow Interrupt Mask Bit */
86#define AT_XDMAC_CIS 0x0C /* Channel Interrupt Status Register */
87#define AT_XDMAC_CIS_BIS BIT(0) /* End of Block Interrupt Status Bit */
88#define AT_XDMAC_CIS_LIS BIT(1) /* End of Linked List Interrupt Status Bit */
89#define AT_XDMAC_CIS_DIS BIT(2) /* End of Disable Interrupt Status Bit */
90#define AT_XDMAC_CIS_FIS BIT(3) /* End of Flush Interrupt Status Bit */
91#define AT_XDMAC_CIS_RBEIS BIT(4) /* Read Bus Error Interrupt Status Bit */
92#define AT_XDMAC_CIS_WBEIS BIT(5) /* Write Bus Error Interrupt Status Bit */
93#define AT_XDMAC_CIS_ROIS BIT(6) /* Request Overflow Interrupt Status Bit */
94#define AT_XDMAC_CSA 0x10 /* Channel Source Address Register */
95#define AT_XDMAC_CDA 0x14 /* Channel Destination Address Register */
96#define AT_XDMAC_CNDA 0x18 /* Channel Next Descriptor Address Register */
97#define AT_XDMAC_CNDA_NDAIF(i) ((i) & 0x1) /* Channel x Next Descriptor Interface */
98#define AT_XDMAC_CNDA_NDA(i) ((i) & 0xfffffffc) /* Channel x Next Descriptor Address */
99#define AT_XDMAC_CNDC 0x1C /* Channel Next Descriptor Control Register */
100#define AT_XDMAC_CNDC_NDE (0x1 << 0) /* Channel x Next Descriptor Enable */
101#define AT_XDMAC_CNDC_NDSUP (0x1 << 1) /* Channel x Next Descriptor Source Update */
102#define AT_XDMAC_CNDC_NDDUP (0x1 << 2) /* Channel x Next Descriptor Destination Update */
103#define AT_XDMAC_CNDC_NDVIEW_NDV0 (0x0 << 3) /* Channel x Next Descriptor View 0 */
104#define AT_XDMAC_CNDC_NDVIEW_NDV1 (0x1 << 3) /* Channel x Next Descriptor View 1 */
105#define AT_XDMAC_CNDC_NDVIEW_NDV2 (0x2 << 3) /* Channel x Next Descriptor View 2 */
106#define AT_XDMAC_CNDC_NDVIEW_NDV3 (0x3 << 3) /* Channel x Next Descriptor View 3 */
107#define AT_XDMAC_CUBC 0x20 /* Channel Microblock Control Register */
108#define AT_XDMAC_CBC 0x24 /* Channel Block Control Register */
109#define AT_XDMAC_CC 0x28 /* Channel Configuration Register */
110#define AT_XDMAC_CC_TYPE (0x1 << 0) /* Channel Transfer Type */
111#define AT_XDMAC_CC_TYPE_MEM_TRAN (0x0 << 0) /* Memory to Memory Transfer */
112#define AT_XDMAC_CC_TYPE_PER_TRAN (0x1 << 0) /* Peripheral to Memory or Memory to Peripheral Transfer */
113#define AT_XDMAC_CC_MBSIZE_MASK (0x3 << 1)
114#define AT_XDMAC_CC_MBSIZE_SINGLE (0x0 << 1)
115#define AT_XDMAC_CC_MBSIZE_FOUR (0x1 << 1)
116#define AT_XDMAC_CC_MBSIZE_EIGHT (0x2 << 1)
117#define AT_XDMAC_CC_MBSIZE_SIXTEEN (0x3 << 1)
118#define AT_XDMAC_CC_DSYNC (0x1 << 4) /* Channel Synchronization */
119#define AT_XDMAC_CC_DSYNC_PER2MEM (0x0 << 4)
120#define AT_XDMAC_CC_DSYNC_MEM2PER (0x1 << 4)
121#define AT_XDMAC_CC_PROT (0x1 << 5) /* Channel Protection */
122#define AT_XDMAC_CC_PROT_SEC (0x0 << 5)
123#define AT_XDMAC_CC_PROT_UNSEC (0x1 << 5)
124#define AT_XDMAC_CC_SWREQ (0x1 << 6) /* Channel Software Request Trigger */
125#define AT_XDMAC_CC_SWREQ_HWR_CONNECTED (0x0 << 6)
126#define AT_XDMAC_CC_SWREQ_SWR_CONNECTED (0x1 << 6)
127#define AT_XDMAC_CC_MEMSET (0x1 << 7) /* Channel Fill Block of memory */
128#define AT_XDMAC_CC_MEMSET_NORMAL_MODE (0x0 << 7)
129#define AT_XDMAC_CC_MEMSET_HW_MODE (0x1 << 7)
130#define AT_XDMAC_CC_CSIZE(i) ((0x7 & (i)) << 8) /* Channel Chunk Size */
131#define AT_XDMAC_CC_DWIDTH_OFFSET 11
132#define AT_XDMAC_CC_DWIDTH_MASK (0x3 << AT_XDMAC_CC_DWIDTH_OFFSET)
133#define AT_XDMAC_CC_DWIDTH(i) ((0x3 & (i)) << AT_XDMAC_CC_DWIDTH_OFFSET) /* Channel Data Width */
134#define AT_XDMAC_CC_DWIDTH_BYTE 0x0
135#define AT_XDMAC_CC_DWIDTH_HALFWORD 0x1
136#define AT_XDMAC_CC_DWIDTH_WORD 0x2
137#define AT_XDMAC_CC_DWIDTH_DWORD 0x3
138#define AT_XDMAC_CC_SIF(i) ((0x1 & (i)) << 13) /* Channel Source Interface Identifier */
139#define AT_XDMAC_CC_DIF(i) ((0x1 & (i)) << 14) /* Channel Destination Interface Identifier */
140#define AT_XDMAC_CC_SAM_MASK (0x3 << 16) /* Channel Source Addressing Mode */
141#define AT_XDMAC_CC_SAM_FIXED_AM (0x0 << 16)
142#define AT_XDMAC_CC_SAM_INCREMENTED_AM (0x1 << 16)
143#define AT_XDMAC_CC_SAM_UBS_AM (0x2 << 16)
144#define AT_XDMAC_CC_SAM_UBS_DS_AM (0x3 << 16)
145#define AT_XDMAC_CC_DAM_MASK (0x3 << 18) /* Channel Source Addressing Mode */
146#define AT_XDMAC_CC_DAM_FIXED_AM (0x0 << 18)
147#define AT_XDMAC_CC_DAM_INCREMENTED_AM (0x1 << 18)
148#define AT_XDMAC_CC_DAM_UBS_AM (0x2 << 18)
149#define AT_XDMAC_CC_DAM_UBS_DS_AM (0x3 << 18)
150#define AT_XDMAC_CC_INITD (0x1 << 21) /* Channel Initialization Terminated (read only) */
151#define AT_XDMAC_CC_INITD_TERMINATED (0x0 << 21)
152#define AT_XDMAC_CC_INITD_IN_PROGRESS (0x1 << 21)
153#define AT_XDMAC_CC_RDIP (0x1 << 22) /* Read in Progress (read only) */
154#define AT_XDMAC_CC_RDIP_DONE (0x0 << 22)
155#define AT_XDMAC_CC_RDIP_IN_PROGRESS (0x1 << 22)
156#define AT_XDMAC_CC_WRIP (0x1 << 23) /* Write in Progress (read only) */
157#define AT_XDMAC_CC_WRIP_DONE (0x0 << 23)
158#define AT_XDMAC_CC_WRIP_IN_PROGRESS (0x1 << 23)
159#define AT_XDMAC_CC_PERID(i) (0x7f & (h) << 24) /* Channel Peripheral Identifier */
160#define AT_XDMAC_CDS_MSP 0x2C /* Channel Data Stride Memory Set Pattern */
161#define AT_XDMAC_CSUS 0x30 /* Channel Source Microblock Stride */
162#define AT_XDMAC_CDUS 0x34 /* Channel Destination Microblock Stride */
163
164#define AT_XDMAC_CHAN_REG_BASE 0x50 /* Channel registers base address */
165
166/* Microblock control members */
167#define AT_XDMAC_MBR_UBC_UBLEN_MAX 0xFFFFFFUL /* Maximum Microblock Length */
168#define AT_XDMAC_MBR_UBC_NDE (0x1 << 24) /* Next Descriptor Enable */
169#define AT_XDMAC_MBR_UBC_NSEN (0x1 << 25) /* Next Descriptor Source Update */
170#define AT_XDMAC_MBR_UBC_NDEN (0x1 << 26) /* Next Descriptor Destination Update */
171#define AT_XDMAC_MBR_UBC_NDV0 (0x0 << 27) /* Next Descriptor View 0 */
172#define AT_XDMAC_MBR_UBC_NDV1 (0x1 << 27) /* Next Descriptor View 1 */
173#define AT_XDMAC_MBR_UBC_NDV2 (0x2 << 27) /* Next Descriptor View 2 */
174#define AT_XDMAC_MBR_UBC_NDV3 (0x3 << 27) /* Next Descriptor View 3 */
175
176#define AT_XDMAC_MAX_CHAN 0x20
Ludovic Desroches765c37d2015-06-08 10:33:15 +0200177#define AT_XDMAC_MAX_CSIZE 16 /* 16 data */
178#define AT_XDMAC_MAX_DWIDTH 8 /* 64 bits */
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200179
Ludovic Desroches8ac82f82014-11-17 14:42:44 +0100180#define AT_XDMAC_DMA_BUSWIDTHS\
181 (BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) |\
182 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |\
183 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |\
184 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |\
185 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES))
186
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200187enum atc_status {
188 AT_XDMAC_CHAN_IS_CYCLIC = 0,
189 AT_XDMAC_CHAN_IS_PAUSED,
190};
191
192/* ----- Channels ----- */
193struct at_xdmac_chan {
194 struct dma_chan chan;
195 void __iomem *ch_regs;
196 u32 mask; /* Channel Mask */
Ludovic Desroches765c37d2015-06-08 10:33:15 +0200197 u32 cfg; /* Channel Configuration Register */
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200198 u8 perid; /* Peripheral ID */
199 u8 perif; /* Peripheral Interface */
200 u8 memif; /* Memory Interface */
Ludovic Desroches734bb9a2015-01-27 16:30:30 +0100201 u32 save_cc;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200202 u32 save_cim;
203 u32 save_cnda;
204 u32 save_cndc;
205 unsigned long status;
206 struct tasklet_struct tasklet;
Ludovic Desroches765c37d2015-06-08 10:33:15 +0200207 struct dma_slave_config sconfig;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200208
209 spinlock_t lock;
210
211 struct list_head xfers_list;
212 struct list_head free_descs_list;
213};
214
215
216/* ----- Controller ----- */
217struct at_xdmac {
218 struct dma_device dma;
219 void __iomem *regs;
220 int irq;
221 struct clk *clk;
222 u32 save_gim;
223 u32 save_gs;
224 struct dma_pool *at_xdmac_desc_pool;
225 struct at_xdmac_chan chan[0];
226};
227
228
229/* ----- Descriptors ----- */
230
231/* Linked List Descriptor */
232struct at_xdmac_lld {
233 dma_addr_t mbr_nda; /* Next Descriptor Member */
234 u32 mbr_ubc; /* Microblock Control Member */
235 dma_addr_t mbr_sa; /* Source Address Member */
236 dma_addr_t mbr_da; /* Destination Address Member */
237 u32 mbr_cfg; /* Configuration Register */
Maxime Ripardee0fe352015-05-07 17:38:08 +0200238 u32 mbr_bc; /* Block Control Register */
239 u32 mbr_ds; /* Data Stride Register */
240 u32 mbr_sus; /* Source Microblock Stride Register */
241 u32 mbr_dus; /* Destination Microblock Stride Register */
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200242};
243
244
245struct at_xdmac_desc {
246 struct at_xdmac_lld lld;
247 enum dma_transfer_direction direction;
248 struct dma_async_tx_descriptor tx_dma_desc;
249 struct list_head desc_node;
250 /* Following members are only used by the first descriptor */
251 bool active_xfer;
252 unsigned int xfer_size;
253 struct list_head descs_list;
254 struct list_head xfer_node;
255};
256
257static inline void __iomem *at_xdmac_chan_reg_base(struct at_xdmac *atxdmac, unsigned int chan_nb)
258{
259 return atxdmac->regs + (AT_XDMAC_CHAN_REG_BASE + chan_nb * 0x40);
260}
261
Ludovic Desroches6e5ae292014-11-13 11:52:39 +0100262#define at_xdmac_read(atxdmac, reg) readl_relaxed((atxdmac)->regs + (reg))
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200263#define at_xdmac_write(atxdmac, reg, value) \
Ludovic Desroches6e5ae292014-11-13 11:52:39 +0100264 writel_relaxed((value), (atxdmac)->regs + (reg))
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200265
Ludovic Desroches6e5ae292014-11-13 11:52:39 +0100266#define at_xdmac_chan_read(atchan, reg) readl_relaxed((atchan)->ch_regs + (reg))
267#define at_xdmac_chan_write(atchan, reg, value) writel_relaxed((value), (atchan)->ch_regs + (reg))
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200268
269static inline struct at_xdmac_chan *to_at_xdmac_chan(struct dma_chan *dchan)
270{
271 return container_of(dchan, struct at_xdmac_chan, chan);
272}
273
274static struct device *chan2dev(struct dma_chan *chan)
275{
276 return &chan->dev->device;
277}
278
279static inline struct at_xdmac *to_at_xdmac(struct dma_device *ddev)
280{
281 return container_of(ddev, struct at_xdmac, dma);
282}
283
284static inline struct at_xdmac_desc *txd_to_at_desc(struct dma_async_tx_descriptor *txd)
285{
286 return container_of(txd, struct at_xdmac_desc, tx_dma_desc);
287}
288
289static inline int at_xdmac_chan_is_cyclic(struct at_xdmac_chan *atchan)
290{
291 return test_bit(AT_XDMAC_CHAN_IS_CYCLIC, &atchan->status);
292}
293
294static inline int at_xdmac_chan_is_paused(struct at_xdmac_chan *atchan)
295{
296 return test_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status);
297}
298
299static inline int at_xdmac_csize(u32 maxburst)
300{
301 int csize;
302
303 csize = ffs(maxburst) - 1;
304 if (csize > 4)
305 csize = -EINVAL;
306
307 return csize;
308};
309
310static inline u8 at_xdmac_get_dwidth(u32 cfg)
311{
312 return (cfg & AT_XDMAC_CC_DWIDTH_MASK) >> AT_XDMAC_CC_DWIDTH_OFFSET;
313};
314
315static unsigned int init_nr_desc_per_channel = 64;
316module_param(init_nr_desc_per_channel, uint, 0644);
317MODULE_PARM_DESC(init_nr_desc_per_channel,
318 "initial descriptors per channel (default: 64)");
319
320
321static bool at_xdmac_chan_is_enabled(struct at_xdmac_chan *atchan)
322{
323 return at_xdmac_chan_read(atchan, AT_XDMAC_GS) & atchan->mask;
324}
325
326static void at_xdmac_off(struct at_xdmac *atxdmac)
327{
328 at_xdmac_write(atxdmac, AT_XDMAC_GD, -1L);
329
330 /* Wait that all chans are disabled. */
331 while (at_xdmac_read(atxdmac, AT_XDMAC_GS))
332 cpu_relax();
333
334 at_xdmac_write(atxdmac, AT_XDMAC_GID, -1L);
335}
336
337/* Call with lock hold. */
338static void at_xdmac_start_xfer(struct at_xdmac_chan *atchan,
339 struct at_xdmac_desc *first)
340{
341 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
342 u32 reg;
343
344 dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, first);
345
346 if (at_xdmac_chan_is_enabled(atchan))
347 return;
348
349 /* Set transfer as active to not try to start it again. */
350 first->active_xfer = true;
351
352 /* Tell xdmac where to get the first descriptor. */
353 reg = AT_XDMAC_CNDA_NDA(first->tx_dma_desc.phys)
354 | AT_XDMAC_CNDA_NDAIF(atchan->memif);
355 at_xdmac_chan_write(atchan, AT_XDMAC_CNDA, reg);
356
357 /*
Ludovic Desroches6d3a7d92015-01-27 16:30:32 +0100358 * When doing non cyclic transfer we need to use the next
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200359 * descriptor view 2 since some fields of the configuration register
360 * depend on transfer size and src/dest addresses.
361 */
Ludovic Desroches20cadcb42015-06-17 16:22:26 +0200362 if (at_xdmac_chan_is_cyclic(atchan))
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200363 reg = AT_XDMAC_CNDC_NDVIEW_NDV1;
Ludovic Desroches20cadcb42015-06-17 16:22:26 +0200364 else if (first->lld.mbr_ubc & AT_XDMAC_MBR_UBC_NDV3)
Maxime Ripardee0fe352015-05-07 17:38:08 +0200365 reg = AT_XDMAC_CNDC_NDVIEW_NDV3;
Ludovic Desroches20cadcb42015-06-17 16:22:26 +0200366 else
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200367 reg = AT_XDMAC_CNDC_NDVIEW_NDV2;
Ludovic Desroches20cadcb42015-06-17 16:22:26 +0200368 /*
369 * Even if the register will be updated from the configuration in the
370 * descriptor when using view 2 or higher, the PROT bit won't be set
371 * properly. This bit can be modified only by using the channel
372 * configuration register.
373 */
374 at_xdmac_chan_write(atchan, AT_XDMAC_CC, first->lld.mbr_cfg);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200375
376 reg |= AT_XDMAC_CNDC_NDDUP
377 | AT_XDMAC_CNDC_NDSUP
378 | AT_XDMAC_CNDC_NDE;
379 at_xdmac_chan_write(atchan, AT_XDMAC_CNDC, reg);
380
381 dev_vdbg(chan2dev(&atchan->chan),
382 "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n",
383 __func__, at_xdmac_chan_read(atchan, AT_XDMAC_CC),
384 at_xdmac_chan_read(atchan, AT_XDMAC_CNDA),
385 at_xdmac_chan_read(atchan, AT_XDMAC_CNDC),
386 at_xdmac_chan_read(atchan, AT_XDMAC_CSA),
387 at_xdmac_chan_read(atchan, AT_XDMAC_CDA),
388 at_xdmac_chan_read(atchan, AT_XDMAC_CUBC));
389
390 at_xdmac_chan_write(atchan, AT_XDMAC_CID, 0xffffffff);
391 reg = AT_XDMAC_CIE_RBEIE | AT_XDMAC_CIE_WBEIE | AT_XDMAC_CIE_ROIE;
392 /*
393 * There is no end of list when doing cyclic dma, we need to get
394 * an interrupt after each periods.
395 */
396 if (at_xdmac_chan_is_cyclic(atchan))
397 at_xdmac_chan_write(atchan, AT_XDMAC_CIE,
398 reg | AT_XDMAC_CIE_BIE);
399 else
400 at_xdmac_chan_write(atchan, AT_XDMAC_CIE,
401 reg | AT_XDMAC_CIE_LIE);
402 at_xdmac_write(atxdmac, AT_XDMAC_GIE, atchan->mask);
403 dev_vdbg(chan2dev(&atchan->chan),
404 "%s: enable channel (0x%08x)\n", __func__, atchan->mask);
405 wmb();
406 at_xdmac_write(atxdmac, AT_XDMAC_GE, atchan->mask);
407
408 dev_vdbg(chan2dev(&atchan->chan),
409 "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n",
410 __func__, at_xdmac_chan_read(atchan, AT_XDMAC_CC),
411 at_xdmac_chan_read(atchan, AT_XDMAC_CNDA),
412 at_xdmac_chan_read(atchan, AT_XDMAC_CNDC),
413 at_xdmac_chan_read(atchan, AT_XDMAC_CSA),
414 at_xdmac_chan_read(atchan, AT_XDMAC_CDA),
415 at_xdmac_chan_read(atchan, AT_XDMAC_CUBC));
416
417}
418
419static dma_cookie_t at_xdmac_tx_submit(struct dma_async_tx_descriptor *tx)
420{
421 struct at_xdmac_desc *desc = txd_to_at_desc(tx);
422 struct at_xdmac_chan *atchan = to_at_xdmac_chan(tx->chan);
423 dma_cookie_t cookie;
Ludovic Desroches4c374fc2015-06-08 10:33:14 +0200424 unsigned long irqflags;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200425
Ludovic Desroches4c374fc2015-06-08 10:33:14 +0200426 spin_lock_irqsave(&atchan->lock, irqflags);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200427 cookie = dma_cookie_assign(tx);
428
429 dev_vdbg(chan2dev(tx->chan), "%s: atchan 0x%p, add desc 0x%p to xfers_list\n",
430 __func__, atchan, desc);
431 list_add_tail(&desc->xfer_node, &atchan->xfers_list);
432 if (list_is_singular(&atchan->xfers_list))
433 at_xdmac_start_xfer(atchan, desc);
434
Ludovic Desroches4c374fc2015-06-08 10:33:14 +0200435 spin_unlock_irqrestore(&atchan->lock, irqflags);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200436 return cookie;
437}
438
439static struct at_xdmac_desc *at_xdmac_alloc_desc(struct dma_chan *chan,
440 gfp_t gfp_flags)
441{
442 struct at_xdmac_desc *desc;
443 struct at_xdmac *atxdmac = to_at_xdmac(chan->device);
444 dma_addr_t phys;
445
446 desc = dma_pool_alloc(atxdmac->at_xdmac_desc_pool, gfp_flags, &phys);
447 if (desc) {
448 memset(desc, 0, sizeof(*desc));
449 INIT_LIST_HEAD(&desc->descs_list);
450 dma_async_tx_descriptor_init(&desc->tx_dma_desc, chan);
451 desc->tx_dma_desc.tx_submit = at_xdmac_tx_submit;
452 desc->tx_dma_desc.phys = phys;
453 }
454
455 return desc;
456}
457
Ludovic Desroches0be21362015-09-15 15:39:11 +0200458void at_xdmac_init_used_desc(struct at_xdmac_desc *desc)
459{
460 memset(&desc->lld, 0, sizeof(desc->lld));
461 INIT_LIST_HEAD(&desc->descs_list);
462 desc->direction = DMA_TRANS_NONE;
463 desc->xfer_size = 0;
464 desc->active_xfer = false;
465}
466
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200467/* Call must be protected by lock. */
468static struct at_xdmac_desc *at_xdmac_get_desc(struct at_xdmac_chan *atchan)
469{
470 struct at_xdmac_desc *desc;
471
472 if (list_empty(&atchan->free_descs_list)) {
473 desc = at_xdmac_alloc_desc(&atchan->chan, GFP_NOWAIT);
474 } else {
475 desc = list_first_entry(&atchan->free_descs_list,
476 struct at_xdmac_desc, desc_node);
477 list_del(&desc->desc_node);
Ludovic Desroches0be21362015-09-15 15:39:11 +0200478 at_xdmac_init_used_desc(desc);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200479 }
480
481 return desc;
482}
483
Maxime Ripard0d0ee752015-05-07 17:38:10 +0200484static void at_xdmac_queue_desc(struct dma_chan *chan,
485 struct at_xdmac_desc *prev,
486 struct at_xdmac_desc *desc)
487{
488 if (!prev || !desc)
489 return;
490
491 prev->lld.mbr_nda = desc->tx_dma_desc.phys;
492 prev->lld.mbr_ubc |= AT_XDMAC_MBR_UBC_NDE;
493
494 dev_dbg(chan2dev(chan), "%s: chain lld: prev=0x%p, mbr_nda=%pad\n",
495 __func__, prev, &prev->lld.mbr_nda);
496}
497
Maxime Ripard6007ccb2015-05-07 17:38:11 +0200498static inline void at_xdmac_increment_block_count(struct dma_chan *chan,
499 struct at_xdmac_desc *desc)
500{
501 if (!desc)
502 return;
503
504 desc->lld.mbr_bc++;
505
506 dev_dbg(chan2dev(chan),
507 "%s: incrementing the block count of the desc 0x%p\n",
508 __func__, desc);
509}
510
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200511static struct dma_chan *at_xdmac_xlate(struct of_phandle_args *dma_spec,
512 struct of_dma *of_dma)
513{
514 struct at_xdmac *atxdmac = of_dma->of_dma_data;
515 struct at_xdmac_chan *atchan;
516 struct dma_chan *chan;
517 struct device *dev = atxdmac->dma.dev;
518
519 if (dma_spec->args_count != 1) {
520 dev_err(dev, "dma phandler args: bad number of args\n");
521 return NULL;
522 }
523
524 chan = dma_get_any_slave_channel(&atxdmac->dma);
525 if (!chan) {
526 dev_err(dev, "can't get a dma channel\n");
527 return NULL;
528 }
529
530 atchan = to_at_xdmac_chan(chan);
531 atchan->memif = AT91_XDMAC_DT_GET_MEM_IF(dma_spec->args[0]);
532 atchan->perif = AT91_XDMAC_DT_GET_PER_IF(dma_spec->args[0]);
533 atchan->perid = AT91_XDMAC_DT_GET_PERID(dma_spec->args[0]);
534 dev_dbg(dev, "chan dt cfg: memif=%u perif=%u perid=%u\n",
535 atchan->memif, atchan->perif, atchan->perid);
536
537 return chan;
538}
539
Ludovic Desroches765c37d2015-06-08 10:33:15 +0200540static int at_xdmac_compute_chan_conf(struct dma_chan *chan,
541 enum dma_transfer_direction direction)
542{
543 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
544 int csize, dwidth;
545
546 if (direction == DMA_DEV_TO_MEM) {
547 atchan->cfg =
548 AT91_XDMAC_DT_PERID(atchan->perid)
549 | AT_XDMAC_CC_DAM_INCREMENTED_AM
550 | AT_XDMAC_CC_SAM_FIXED_AM
551 | AT_XDMAC_CC_DIF(atchan->memif)
552 | AT_XDMAC_CC_SIF(atchan->perif)
553 | AT_XDMAC_CC_SWREQ_HWR_CONNECTED
554 | AT_XDMAC_CC_DSYNC_PER2MEM
555 | AT_XDMAC_CC_MBSIZE_SIXTEEN
556 | AT_XDMAC_CC_TYPE_PER_TRAN;
557 csize = ffs(atchan->sconfig.src_maxburst) - 1;
558 if (csize < 0) {
559 dev_err(chan2dev(chan), "invalid src maxburst value\n");
560 return -EINVAL;
561 }
562 atchan->cfg |= AT_XDMAC_CC_CSIZE(csize);
563 dwidth = ffs(atchan->sconfig.src_addr_width) - 1;
564 if (dwidth < 0) {
565 dev_err(chan2dev(chan), "invalid src addr width value\n");
566 return -EINVAL;
567 }
568 atchan->cfg |= AT_XDMAC_CC_DWIDTH(dwidth);
569 } else if (direction == DMA_MEM_TO_DEV) {
570 atchan->cfg =
571 AT91_XDMAC_DT_PERID(atchan->perid)
572 | AT_XDMAC_CC_DAM_FIXED_AM
573 | AT_XDMAC_CC_SAM_INCREMENTED_AM
574 | AT_XDMAC_CC_DIF(atchan->perif)
575 | AT_XDMAC_CC_SIF(atchan->memif)
576 | AT_XDMAC_CC_SWREQ_HWR_CONNECTED
577 | AT_XDMAC_CC_DSYNC_MEM2PER
578 | AT_XDMAC_CC_MBSIZE_SIXTEEN
579 | AT_XDMAC_CC_TYPE_PER_TRAN;
580 csize = ffs(atchan->sconfig.dst_maxburst) - 1;
581 if (csize < 0) {
582 dev_err(chan2dev(chan), "invalid src maxburst value\n");
583 return -EINVAL;
584 }
585 atchan->cfg |= AT_XDMAC_CC_CSIZE(csize);
586 dwidth = ffs(atchan->sconfig.dst_addr_width) - 1;
587 if (dwidth < 0) {
588 dev_err(chan2dev(chan), "invalid dst addr width value\n");
589 return -EINVAL;
590 }
591 atchan->cfg |= AT_XDMAC_CC_DWIDTH(dwidth);
592 }
593
594 dev_dbg(chan2dev(chan), "%s: cfg=0x%08x\n", __func__, atchan->cfg);
595
596 return 0;
597}
598
599/*
600 * Only check that maxburst and addr width values are supported by the
601 * the controller but not that the configuration is good to perform the
602 * transfer since we don't know the direction at this stage.
603 */
604static int at_xdmac_check_slave_config(struct dma_slave_config *sconfig)
605{
606 if ((sconfig->src_maxburst > AT_XDMAC_MAX_CSIZE)
607 || (sconfig->dst_maxburst > AT_XDMAC_MAX_CSIZE))
608 return -EINVAL;
609
610 if ((sconfig->src_addr_width > AT_XDMAC_MAX_DWIDTH)
611 || (sconfig->dst_addr_width > AT_XDMAC_MAX_DWIDTH))
612 return -EINVAL;
613
614 return 0;
615}
616
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200617static int at_xdmac_set_slave_config(struct dma_chan *chan,
618 struct dma_slave_config *sconfig)
619{
620 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200621
Ludovic Desroches765c37d2015-06-08 10:33:15 +0200622 if (at_xdmac_check_slave_config(sconfig)) {
623 dev_err(chan2dev(chan), "invalid slave configuration\n");
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200624 return -EINVAL;
625 }
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200626
Ludovic Desroches765c37d2015-06-08 10:33:15 +0200627 memcpy(&atchan->sconfig, sconfig, sizeof(atchan->sconfig));
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200628
629 return 0;
630}
631
632static struct dma_async_tx_descriptor *
633at_xdmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
634 unsigned int sg_len, enum dma_transfer_direction direction,
635 unsigned long flags, void *context)
636{
Ludovic Desroches35ca0ee2015-06-08 10:33:16 +0200637 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
638 struct at_xdmac_desc *first = NULL, *prev = NULL;
639 struct scatterlist *sg;
640 int i;
641 unsigned int xfer_size = 0;
642 unsigned long irqflags;
Ludovic Desroches4c374fc2015-06-08 10:33:14 +0200643 struct dma_async_tx_descriptor *ret = NULL;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200644
645 if (!sgl)
646 return NULL;
647
648 if (!is_slave_direction(direction)) {
649 dev_err(chan2dev(chan), "invalid DMA direction\n");
650 return NULL;
651 }
652
653 dev_dbg(chan2dev(chan), "%s: sg_len=%d, dir=%s, flags=0x%lx\n",
654 __func__, sg_len,
655 direction == DMA_MEM_TO_DEV ? "to device" : "from device",
656 flags);
657
658 /* Protect dma_sconfig field that can be modified by set_slave_conf. */
Ludovic Desroches4c374fc2015-06-08 10:33:14 +0200659 spin_lock_irqsave(&atchan->lock, irqflags);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200660
Ludovic Desroches765c37d2015-06-08 10:33:15 +0200661 if (at_xdmac_compute_chan_conf(chan, direction))
662 goto spin_unlock;
663
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200664 /* Prepare descriptors. */
665 for_each_sg(sgl, sg, sg_len, i) {
666 struct at_xdmac_desc *desc = NULL;
Ludovic Desroches6d3a7d92015-01-27 16:30:32 +0100667 u32 len, mem, dwidth, fixed_dwidth;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200668
669 len = sg_dma_len(sg);
670 mem = sg_dma_address(sg);
671 if (unlikely(!len)) {
672 dev_err(chan2dev(chan), "sg data length is zero\n");
Ludovic Desroches4c374fc2015-06-08 10:33:14 +0200673 goto spin_unlock;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200674 }
675 dev_dbg(chan2dev(chan), "%s: * sg%d len=%u, mem=0x%08x\n",
676 __func__, i, len, mem);
677
678 desc = at_xdmac_get_desc(atchan);
679 if (!desc) {
680 dev_err(chan2dev(chan), "can't get descriptor\n");
681 if (first)
682 list_splice_init(&first->descs_list, &atchan->free_descs_list);
Ludovic Desroches4c374fc2015-06-08 10:33:14 +0200683 goto spin_unlock;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200684 }
685
686 /* Linked list descriptor setup. */
687 if (direction == DMA_DEV_TO_MEM) {
Ludovic Desroches765c37d2015-06-08 10:33:15 +0200688 desc->lld.mbr_sa = atchan->sconfig.src_addr;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200689 desc->lld.mbr_da = mem;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200690 } else {
691 desc->lld.mbr_sa = mem;
Ludovic Desroches765c37d2015-06-08 10:33:15 +0200692 desc->lld.mbr_da = atchan->sconfig.dst_addr;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200693 }
Cyrille Pitchen1c8a38b2015-06-30 14:36:57 +0200694 dwidth = at_xdmac_get_dwidth(atchan->cfg);
Ludovic Desroches6d3a7d92015-01-27 16:30:32 +0100695 fixed_dwidth = IS_ALIGNED(len, 1 << dwidth)
Cyrille Pitchen1c8a38b2015-06-30 14:36:57 +0200696 ? dwidth
Ludovic Desroches6d3a7d92015-01-27 16:30:32 +0100697 : AT_XDMAC_CC_DWIDTH_BYTE;
698 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV2 /* next descriptor view */
Ludovic Desrochesbe835072015-01-27 16:30:31 +0100699 | AT_XDMAC_MBR_UBC_NDEN /* next descriptor dst parameter update */
700 | AT_XDMAC_MBR_UBC_NSEN /* next descriptor src parameter update */
Ludovic Desroches6d3a7d92015-01-27 16:30:32 +0100701 | (len >> fixed_dwidth); /* microblock length */
Cyrille Pitchen1c8a38b2015-06-30 14:36:57 +0200702 desc->lld.mbr_cfg = (atchan->cfg & ~AT_XDMAC_CC_DWIDTH_MASK) |
703 AT_XDMAC_CC_DWIDTH(fixed_dwidth);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200704 dev_dbg(chan2dev(chan),
Vinod Koul82e24242014-11-06 18:02:52 +0530705 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x\n",
706 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200707
708 /* Chain lld. */
Maxime Ripard0d0ee752015-05-07 17:38:10 +0200709 if (prev)
710 at_xdmac_queue_desc(chan, prev, desc);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200711
712 prev = desc;
713 if (!first)
714 first = desc;
715
716 dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n",
717 __func__, desc, first);
718 list_add_tail(&desc->desc_node, &first->descs_list);
Cyrille Pitchen57819272014-11-13 11:52:42 +0100719 xfer_size += len;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200720 }
721
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200722
723 first->tx_dma_desc.flags = flags;
Cyrille Pitchen57819272014-11-13 11:52:42 +0100724 first->xfer_size = xfer_size;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200725 first->direction = direction;
Ludovic Desroches4c374fc2015-06-08 10:33:14 +0200726 ret = &first->tx_dma_desc;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200727
Ludovic Desroches4c374fc2015-06-08 10:33:14 +0200728spin_unlock:
729 spin_unlock_irqrestore(&atchan->lock, irqflags);
730 return ret;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200731}
732
733static struct dma_async_tx_descriptor *
734at_xdmac_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr,
735 size_t buf_len, size_t period_len,
736 enum dma_transfer_direction direction,
737 unsigned long flags)
738{
739 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
740 struct at_xdmac_desc *first = NULL, *prev = NULL;
741 unsigned int periods = buf_len / period_len;
742 int i;
Ludovic Desroches4c374fc2015-06-08 10:33:14 +0200743 unsigned long irqflags;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200744
Vinod Koul82e24242014-11-06 18:02:52 +0530745 dev_dbg(chan2dev(chan), "%s: buf_addr=%pad, buf_len=%zd, period_len=%zd, dir=%s, flags=0x%lx\n",
746 __func__, &buf_addr, buf_len, period_len,
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200747 direction == DMA_MEM_TO_DEV ? "mem2per" : "per2mem", flags);
748
749 if (!is_slave_direction(direction)) {
750 dev_err(chan2dev(chan), "invalid DMA direction\n");
751 return NULL;
752 }
753
754 if (test_and_set_bit(AT_XDMAC_CHAN_IS_CYCLIC, &atchan->status)) {
755 dev_err(chan2dev(chan), "channel currently used\n");
756 return NULL;
757 }
758
Ludovic Desroches765c37d2015-06-08 10:33:15 +0200759 if (at_xdmac_compute_chan_conf(chan, direction))
760 return NULL;
761
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200762 for (i = 0; i < periods; i++) {
763 struct at_xdmac_desc *desc = NULL;
764
Ludovic Desroches4c374fc2015-06-08 10:33:14 +0200765 spin_lock_irqsave(&atchan->lock, irqflags);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200766 desc = at_xdmac_get_desc(atchan);
767 if (!desc) {
768 dev_err(chan2dev(chan), "can't get descriptor\n");
769 if (first)
770 list_splice_init(&first->descs_list, &atchan->free_descs_list);
Ludovic Desroches4c374fc2015-06-08 10:33:14 +0200771 spin_unlock_irqrestore(&atchan->lock, irqflags);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200772 return NULL;
773 }
Ludovic Desroches4c374fc2015-06-08 10:33:14 +0200774 spin_unlock_irqrestore(&atchan->lock, irqflags);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200775 dev_dbg(chan2dev(chan),
Vinod Koul82e24242014-11-06 18:02:52 +0530776 "%s: desc=0x%p, tx_dma_desc.phys=%pad\n",
777 __func__, desc, &desc->tx_dma_desc.phys);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200778
779 if (direction == DMA_DEV_TO_MEM) {
Ludovic Desroches765c37d2015-06-08 10:33:15 +0200780 desc->lld.mbr_sa = atchan->sconfig.src_addr;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200781 desc->lld.mbr_da = buf_addr + i * period_len;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200782 } else {
783 desc->lld.mbr_sa = buf_addr + i * period_len;
Ludovic Desroches765c37d2015-06-08 10:33:15 +0200784 desc->lld.mbr_da = atchan->sconfig.dst_addr;
kbuild test robot5ac7d582014-11-06 17:28:08 +0800785 }
Ludovic Desroches765c37d2015-06-08 10:33:15 +0200786 desc->lld.mbr_cfg = atchan->cfg;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200787 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV1
788 | AT_XDMAC_MBR_UBC_NDEN
789 | AT_XDMAC_MBR_UBC_NSEN
Ludovic Desroches6eb9d3c2015-02-12 16:30:30 +0100790 | period_len >> at_xdmac_get_dwidth(desc->lld.mbr_cfg);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200791
792 dev_dbg(chan2dev(chan),
Vinod Koul82e24242014-11-06 18:02:52 +0530793 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x\n",
794 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200795
796 /* Chain lld. */
Maxime Ripard0d0ee752015-05-07 17:38:10 +0200797 if (prev)
798 at_xdmac_queue_desc(chan, prev, desc);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200799
800 prev = desc;
801 if (!first)
802 first = desc;
803
804 dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n",
805 __func__, desc, first);
806 list_add_tail(&desc->desc_node, &first->descs_list);
807 }
808
Ludovic Desrochese900c302015-07-22 16:12:29 +0200809 at_xdmac_queue_desc(chan, prev, first);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200810 first->tx_dma_desc.flags = flags;
811 first->xfer_size = buf_len;
812 first->direction = direction;
813
814 return &first->tx_dma_desc;
815}
816
Maxime Ripardf0816a32015-05-07 17:38:09 +0200817static inline u32 at_xdmac_align_width(struct dma_chan *chan, dma_addr_t addr)
818{
819 u32 width;
820
821 /*
822 * Check address alignment to select the greater data width we
823 * can use.
824 *
825 * Some XDMAC implementations don't provide dword transfer, in
826 * this case selecting dword has the same behavior as
827 * selecting word transfers.
828 */
829 if (!(addr & 7)) {
830 width = AT_XDMAC_CC_DWIDTH_DWORD;
831 dev_dbg(chan2dev(chan), "%s: dwidth: double word\n", __func__);
832 } else if (!(addr & 3)) {
833 width = AT_XDMAC_CC_DWIDTH_WORD;
834 dev_dbg(chan2dev(chan), "%s: dwidth: word\n", __func__);
835 } else if (!(addr & 1)) {
836 width = AT_XDMAC_CC_DWIDTH_HALFWORD;
837 dev_dbg(chan2dev(chan), "%s: dwidth: half word\n", __func__);
838 } else {
839 width = AT_XDMAC_CC_DWIDTH_BYTE;
840 dev_dbg(chan2dev(chan), "%s: dwidth: byte\n", __func__);
841 }
842
843 return width;
844}
845
Maxime Ripard6007ccb2015-05-07 17:38:11 +0200846static struct at_xdmac_desc *
847at_xdmac_interleaved_queue_desc(struct dma_chan *chan,
848 struct at_xdmac_chan *atchan,
849 struct at_xdmac_desc *prev,
850 dma_addr_t src, dma_addr_t dst,
851 struct dma_interleaved_template *xt,
852 struct data_chunk *chunk)
853{
854 struct at_xdmac_desc *desc;
855 u32 dwidth;
856 unsigned long flags;
857 size_t ublen;
858 /*
859 * WARNING: The channel configuration is set here since there is no
860 * dmaengine_slave_config call in this case. Moreover we don't know the
861 * direction, it involves we can't dynamically set the source and dest
862 * interface so we have to use the same one. Only interface 0 allows EBI
863 * access. Hopefully we can access DDR through both ports (at least on
864 * SAMA5D4x), so we can use the same interface for source and dest,
865 * that solves the fact we don't know the direction.
Ludovic Desroches95da0c12015-11-23 14:09:39 +0100866 * ERRATA: Even if useless for memory transfers, the PERID has to not
867 * match the one of another channel. If not, it could lead to spurious
868 * flag status.
Maxime Ripard6007ccb2015-05-07 17:38:11 +0200869 */
Ludovic Desroches95da0c12015-11-23 14:09:39 +0100870 u32 chan_cc = AT_XDMAC_CC_PERID(0x3f)
871 | AT_XDMAC_CC_DIF(0)
Maxime Ripard6007ccb2015-05-07 17:38:11 +0200872 | AT_XDMAC_CC_SIF(0)
873 | AT_XDMAC_CC_MBSIZE_SIXTEEN
874 | AT_XDMAC_CC_TYPE_MEM_TRAN;
875
876 dwidth = at_xdmac_align_width(chan, src | dst | chunk->size);
877 if (chunk->size >= (AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth)) {
878 dev_dbg(chan2dev(chan),
879 "%s: chunk too big (%d, max size %lu)...\n",
880 __func__, chunk->size,
881 AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth);
882 return NULL;
883 }
884
885 if (prev)
886 dev_dbg(chan2dev(chan),
887 "Adding items at the end of desc 0x%p\n", prev);
888
889 if (xt->src_inc) {
890 if (xt->src_sgl)
Maxime Riparda1cf09032015-09-15 15:36:00 +0200891 chan_cc |= AT_XDMAC_CC_SAM_UBS_AM;
Maxime Ripard6007ccb2015-05-07 17:38:11 +0200892 else
893 chan_cc |= AT_XDMAC_CC_SAM_INCREMENTED_AM;
894 }
895
896 if (xt->dst_inc) {
897 if (xt->dst_sgl)
Maxime Riparda1cf09032015-09-15 15:36:00 +0200898 chan_cc |= AT_XDMAC_CC_DAM_UBS_AM;
Maxime Ripard6007ccb2015-05-07 17:38:11 +0200899 else
900 chan_cc |= AT_XDMAC_CC_DAM_INCREMENTED_AM;
901 }
902
903 spin_lock_irqsave(&atchan->lock, flags);
904 desc = at_xdmac_get_desc(atchan);
905 spin_unlock_irqrestore(&atchan->lock, flags);
906 if (!desc) {
907 dev_err(chan2dev(chan), "can't get descriptor\n");
908 return NULL;
909 }
910
911 chan_cc |= AT_XDMAC_CC_DWIDTH(dwidth);
912
913 ublen = chunk->size >> dwidth;
914
915 desc->lld.mbr_sa = src;
916 desc->lld.mbr_da = dst;
Maxime Ripard87d001e2015-05-27 16:01:52 +0200917 desc->lld.mbr_sus = dmaengine_get_src_icg(xt, chunk);
918 desc->lld.mbr_dus = dmaengine_get_dst_icg(xt, chunk);
Maxime Ripard6007ccb2015-05-07 17:38:11 +0200919
920 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV3
921 | AT_XDMAC_MBR_UBC_NDEN
922 | AT_XDMAC_MBR_UBC_NSEN
923 | ublen;
924 desc->lld.mbr_cfg = chan_cc;
925
926 dev_dbg(chan2dev(chan),
927 "%s: lld: mbr_sa=0x%08x, mbr_da=0x%08x, mbr_ubc=0x%08x, mbr_cfg=0x%08x\n",
928 __func__, desc->lld.mbr_sa, desc->lld.mbr_da,
929 desc->lld.mbr_ubc, desc->lld.mbr_cfg);
930
931 /* Chain lld. */
932 if (prev)
933 at_xdmac_queue_desc(chan, prev, desc);
934
935 return desc;
936}
937
Maxime Ripard6007ccb2015-05-07 17:38:11 +0200938static struct dma_async_tx_descriptor *
939at_xdmac_prep_interleaved(struct dma_chan *chan,
940 struct dma_interleaved_template *xt,
941 unsigned long flags)
942{
943 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
944 struct at_xdmac_desc *prev = NULL, *first = NULL;
Maxime Ripard6007ccb2015-05-07 17:38:11 +0200945 dma_addr_t dst_addr, src_addr;
Maxime Ripard4e5385782015-09-15 15:29:27 +0200946 size_t src_skip = 0, dst_skip = 0, len = 0;
947 struct data_chunk *chunk;
Maxime Ripard6007ccb2015-05-07 17:38:11 +0200948 int i;
949
Maxime Ripard4e5385782015-09-15 15:29:27 +0200950 if (!xt || !xt->numf || (xt->dir != DMA_MEM_TO_MEM))
951 return NULL;
952
953 /*
954 * TODO: Handle the case where we have to repeat a chain of
955 * descriptors...
956 */
957 if ((xt->numf > 1) && (xt->frame_size > 1))
Maxime Ripard6007ccb2015-05-07 17:38:11 +0200958 return NULL;
959
960 dev_dbg(chan2dev(chan), "%s: src=0x%08x, dest=0x%08x, numf=%d, frame_size=%d, flags=0x%lx\n",
961 __func__, xt->src_start, xt->dst_start, xt->numf,
962 xt->frame_size, flags);
963
964 src_addr = xt->src_start;
965 dst_addr = xt->dst_start;
966
Maxime Ripard4e5385782015-09-15 15:29:27 +0200967 if (xt->numf > 1) {
968 first = at_xdmac_interleaved_queue_desc(chan, atchan,
969 NULL,
970 src_addr, dst_addr,
971 xt, xt->sgl);
972 for (i = 0; i < xt->numf; i++)
973 at_xdmac_increment_block_count(chan, first);
Maxime Ripard6007ccb2015-05-07 17:38:11 +0200974
975 dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n",
Ludovic Desroches62b5cb72015-09-15 15:38:24 +0200976 __func__, first, first);
977 list_add_tail(&first->desc_node, &first->descs_list);
Maxime Ripard4e5385782015-09-15 15:29:27 +0200978 } else {
979 for (i = 0; i < xt->frame_size; i++) {
980 size_t src_icg = 0, dst_icg = 0;
981 struct at_xdmac_desc *desc;
Maxime Ripard6007ccb2015-05-07 17:38:11 +0200982
Maxime Ripard4e5385782015-09-15 15:29:27 +0200983 chunk = xt->sgl + i;
Maxime Ripard6007ccb2015-05-07 17:38:11 +0200984
Maxime Ripard4e5385782015-09-15 15:29:27 +0200985 dst_icg = dmaengine_get_dst_icg(xt, chunk);
986 src_icg = dmaengine_get_src_icg(xt, chunk);
Maxime Ripard6007ccb2015-05-07 17:38:11 +0200987
Maxime Ripard4e5385782015-09-15 15:29:27 +0200988 src_skip = chunk->size + src_icg;
989 dst_skip = chunk->size + dst_icg;
Maxime Ripard6007ccb2015-05-07 17:38:11 +0200990
Maxime Ripard6007ccb2015-05-07 17:38:11 +0200991 dev_dbg(chan2dev(chan),
Maxime Ripard4e5385782015-09-15 15:29:27 +0200992 "%s: chunk size=%d, src icg=%d, dst icg=%d\n",
993 __func__, chunk->size, src_icg, dst_icg);
994
995 desc = at_xdmac_interleaved_queue_desc(chan, atchan,
996 prev,
997 src_addr, dst_addr,
998 xt, chunk);
999 if (!desc) {
1000 list_splice_init(&first->descs_list,
1001 &atchan->free_descs_list);
1002 return NULL;
1003 }
1004
1005 if (!first)
1006 first = desc;
1007
1008 dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n",
1009 __func__, desc, first);
1010 list_add_tail(&desc->desc_node, &first->descs_list);
1011
1012 if (xt->src_sgl)
1013 src_addr += src_skip;
1014
1015 if (xt->dst_sgl)
1016 dst_addr += dst_skip;
1017
1018 len += chunk->size;
1019 prev = desc;
Maxime Ripard6007ccb2015-05-07 17:38:11 +02001020 }
Maxime Ripard6007ccb2015-05-07 17:38:11 +02001021 }
1022
1023 first->tx_dma_desc.cookie = -EBUSY;
1024 first->tx_dma_desc.flags = flags;
1025 first->xfer_size = len;
1026
1027 return &first->tx_dma_desc;
1028}
1029
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001030static struct dma_async_tx_descriptor *
1031at_xdmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
1032 size_t len, unsigned long flags)
1033{
1034 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1035 struct at_xdmac_desc *first = NULL, *prev = NULL;
1036 size_t remaining_size = len, xfer_size = 0, ublen;
1037 dma_addr_t src_addr = src, dst_addr = dest;
1038 u32 dwidth;
1039 /*
1040 * WARNING: We don't know the direction, it involves we can't
1041 * dynamically set the source and dest interface so we have to use the
1042 * same one. Only interface 0 allows EBI access. Hopefully we can
1043 * access DDR through both ports (at least on SAMA5D4x), so we can use
1044 * the same interface for source and dest, that solves the fact we
1045 * don't know the direction.
Ludovic Desroches95da0c12015-11-23 14:09:39 +01001046 * ERRATA: Even if useless for memory transfers, the PERID has to not
1047 * match the one of another channel. If not, it could lead to spurious
1048 * flag status.
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001049 */
Ludovic Desroches95da0c12015-11-23 14:09:39 +01001050 u32 chan_cc = AT_XDMAC_CC_PERID(0x3f)
1051 | AT_XDMAC_CC_DAM_INCREMENTED_AM
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001052 | AT_XDMAC_CC_SAM_INCREMENTED_AM
1053 | AT_XDMAC_CC_DIF(0)
1054 | AT_XDMAC_CC_SIF(0)
1055 | AT_XDMAC_CC_MBSIZE_SIXTEEN
1056 | AT_XDMAC_CC_TYPE_MEM_TRAN;
Ludovic Desroches4c374fc2015-06-08 10:33:14 +02001057 unsigned long irqflags;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001058
Vinod Koul82e24242014-11-06 18:02:52 +05301059 dev_dbg(chan2dev(chan), "%s: src=%pad, dest=%pad, len=%zd, flags=0x%lx\n",
1060 __func__, &src, &dest, len, flags);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001061
1062 if (unlikely(!len))
1063 return NULL;
1064
Maxime Ripardf0816a32015-05-07 17:38:09 +02001065 dwidth = at_xdmac_align_width(chan, src_addr | dst_addr);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001066
1067 /* Prepare descriptors. */
1068 while (remaining_size) {
1069 struct at_xdmac_desc *desc = NULL;
1070
Vinod Koulc66ec042014-11-06 17:37:48 +05301071 dev_dbg(chan2dev(chan), "%s: remaining_size=%zu\n", __func__, remaining_size);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001072
Ludovic Desroches4c374fc2015-06-08 10:33:14 +02001073 spin_lock_irqsave(&atchan->lock, irqflags);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001074 desc = at_xdmac_get_desc(atchan);
Ludovic Desroches4c374fc2015-06-08 10:33:14 +02001075 spin_unlock_irqrestore(&atchan->lock, irqflags);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001076 if (!desc) {
1077 dev_err(chan2dev(chan), "can't get descriptor\n");
1078 if (first)
1079 list_splice_init(&first->descs_list, &atchan->free_descs_list);
1080 return NULL;
1081 }
1082
1083 /* Update src and dest addresses. */
1084 src_addr += xfer_size;
1085 dst_addr += xfer_size;
1086
1087 if (remaining_size >= AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth)
1088 xfer_size = AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth;
1089 else
1090 xfer_size = remaining_size;
1091
Vinod Koulc66ec042014-11-06 17:37:48 +05301092 dev_dbg(chan2dev(chan), "%s: xfer_size=%zu\n", __func__, xfer_size);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001093
1094 /* Check remaining length and change data width if needed. */
Maxime Ripardf0816a32015-05-07 17:38:09 +02001095 dwidth = at_xdmac_align_width(chan,
1096 src_addr | dst_addr | xfer_size);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001097 chan_cc |= AT_XDMAC_CC_DWIDTH(dwidth);
1098
1099 ublen = xfer_size >> dwidth;
1100 remaining_size -= xfer_size;
1101
1102 desc->lld.mbr_sa = src_addr;
1103 desc->lld.mbr_da = dst_addr;
1104 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV2
1105 | AT_XDMAC_MBR_UBC_NDEN
1106 | AT_XDMAC_MBR_UBC_NSEN
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001107 | ublen;
1108 desc->lld.mbr_cfg = chan_cc;
1109
1110 dev_dbg(chan2dev(chan),
Vinod Koul82e24242014-11-06 18:02:52 +05301111 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x, mbr_cfg=0x%08x\n",
1112 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc, desc->lld.mbr_cfg);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001113
1114 /* Chain lld. */
Maxime Ripard0d0ee752015-05-07 17:38:10 +02001115 if (prev)
1116 at_xdmac_queue_desc(chan, prev, desc);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001117
1118 prev = desc;
1119 if (!first)
1120 first = desc;
1121
1122 dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n",
1123 __func__, desc, first);
1124 list_add_tail(&desc->desc_node, &first->descs_list);
1125 }
1126
1127 first->tx_dma_desc.flags = flags;
1128 first->xfer_size = len;
1129
1130 return &first->tx_dma_desc;
1131}
1132
Maxime Ripardb206d9a2015-05-18 13:46:16 +02001133static struct at_xdmac_desc *at_xdmac_memset_create_desc(struct dma_chan *chan,
1134 struct at_xdmac_chan *atchan,
1135 dma_addr_t dst_addr,
1136 size_t len,
1137 int value)
1138{
1139 struct at_xdmac_desc *desc;
1140 unsigned long flags;
1141 size_t ublen;
1142 u32 dwidth;
1143 /*
1144 * WARNING: The channel configuration is set here since there is no
1145 * dmaengine_slave_config call in this case. Moreover we don't know the
1146 * direction, it involves we can't dynamically set the source and dest
1147 * interface so we have to use the same one. Only interface 0 allows EBI
1148 * access. Hopefully we can access DDR through both ports (at least on
1149 * SAMA5D4x), so we can use the same interface for source and dest,
1150 * that solves the fact we don't know the direction.
Ludovic Desroches95da0c12015-11-23 14:09:39 +01001151 * ERRATA: Even if useless for memory transfers, the PERID has to not
1152 * match the one of another channel. If not, it could lead to spurious
1153 * flag status.
Maxime Ripardb206d9a2015-05-18 13:46:16 +02001154 */
Ludovic Desroches95da0c12015-11-23 14:09:39 +01001155 u32 chan_cc = AT_XDMAC_CC_PERID(0x3f)
1156 | AT_XDMAC_CC_DAM_UBS_AM
Maxime Ripardb206d9a2015-05-18 13:46:16 +02001157 | AT_XDMAC_CC_SAM_INCREMENTED_AM
1158 | AT_XDMAC_CC_DIF(0)
1159 | AT_XDMAC_CC_SIF(0)
1160 | AT_XDMAC_CC_MBSIZE_SIXTEEN
1161 | AT_XDMAC_CC_MEMSET_HW_MODE
1162 | AT_XDMAC_CC_TYPE_MEM_TRAN;
1163
1164 dwidth = at_xdmac_align_width(chan, dst_addr);
1165
1166 if (len >= (AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth)) {
1167 dev_err(chan2dev(chan),
1168 "%s: Transfer too large, aborting...\n",
1169 __func__);
1170 return NULL;
1171 }
1172
1173 spin_lock_irqsave(&atchan->lock, flags);
1174 desc = at_xdmac_get_desc(atchan);
1175 spin_unlock_irqrestore(&atchan->lock, flags);
1176 if (!desc) {
1177 dev_err(chan2dev(chan), "can't get descriptor\n");
1178 return NULL;
1179 }
1180
1181 chan_cc |= AT_XDMAC_CC_DWIDTH(dwidth);
1182
1183 ublen = len >> dwidth;
1184
1185 desc->lld.mbr_da = dst_addr;
1186 desc->lld.mbr_ds = value;
1187 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV3
1188 | AT_XDMAC_MBR_UBC_NDEN
1189 | AT_XDMAC_MBR_UBC_NSEN
1190 | ublen;
1191 desc->lld.mbr_cfg = chan_cc;
1192
1193 dev_dbg(chan2dev(chan),
1194 "%s: lld: mbr_da=0x%08x, mbr_ds=0x%08x, mbr_ubc=0x%08x, mbr_cfg=0x%08x\n",
1195 __func__, desc->lld.mbr_da, desc->lld.mbr_ds, desc->lld.mbr_ubc,
1196 desc->lld.mbr_cfg);
1197
1198 return desc;
1199}
1200
1201struct dma_async_tx_descriptor *
1202at_xdmac_prep_dma_memset(struct dma_chan *chan, dma_addr_t dest, int value,
1203 size_t len, unsigned long flags)
1204{
1205 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1206 struct at_xdmac_desc *desc;
1207
1208 dev_dbg(chan2dev(chan), "%s: dest=0x%08x, len=%d, pattern=0x%x, flags=0x%lx\n",
1209 __func__, dest, len, value, flags);
1210
1211 if (unlikely(!len))
1212 return NULL;
1213
1214 desc = at_xdmac_memset_create_desc(chan, atchan, dest, len, value);
1215 list_add_tail(&desc->desc_node, &desc->descs_list);
1216
1217 desc->tx_dma_desc.cookie = -EBUSY;
1218 desc->tx_dma_desc.flags = flags;
1219 desc->xfer_size = len;
1220
1221 return &desc->tx_dma_desc;
1222}
1223
Maxime Ripard67a6eed2015-07-06 12:19:24 +02001224static struct dma_async_tx_descriptor *
1225at_xdmac_prep_dma_memset_sg(struct dma_chan *chan, struct scatterlist *sgl,
1226 unsigned int sg_len, int value,
1227 unsigned long flags)
1228{
1229 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1230 struct at_xdmac_desc *desc, *pdesc = NULL,
1231 *ppdesc = NULL, *first = NULL;
1232 struct scatterlist *sg, *psg = NULL, *ppsg = NULL;
1233 size_t stride = 0, pstride = 0, len = 0;
1234 int i;
1235
1236 if (!sgl)
1237 return NULL;
1238
1239 dev_dbg(chan2dev(chan), "%s: sg_len=%d, value=0x%x, flags=0x%lx\n",
1240 __func__, sg_len, value, flags);
1241
1242 /* Prepare descriptors. */
1243 for_each_sg(sgl, sg, sg_len, i) {
1244 dev_dbg(chan2dev(chan), "%s: dest=0x%08x, len=%d, pattern=0x%x, flags=0x%lx\n",
1245 __func__, sg_dma_address(sg), sg_dma_len(sg),
1246 value, flags);
1247 desc = at_xdmac_memset_create_desc(chan, atchan,
1248 sg_dma_address(sg),
1249 sg_dma_len(sg),
1250 value);
1251 if (!desc && first)
1252 list_splice_init(&first->descs_list,
1253 &atchan->free_descs_list);
1254
1255 if (!first)
1256 first = desc;
1257
1258 /* Update our strides */
1259 pstride = stride;
1260 if (psg)
1261 stride = sg_dma_address(sg) -
1262 (sg_dma_address(psg) + sg_dma_len(psg));
1263
1264 /*
1265 * The scatterlist API gives us only the address and
1266 * length of each elements.
1267 *
1268 * Unfortunately, we don't have the stride, which we
1269 * will need to compute.
1270 *
1271 * That make us end up in a situation like this one:
1272 * len stride len stride len
1273 * +-------+ +-------+ +-------+
1274 * | N-2 | | N-1 | | N |
1275 * +-------+ +-------+ +-------+
1276 *
1277 * We need all these three elements (N-2, N-1 and N)
1278 * to actually take the decision on whether we need to
1279 * queue N-1 or reuse N-2.
1280 *
1281 * We will only consider N if it is the last element.
1282 */
1283 if (ppdesc && pdesc) {
1284 if ((stride == pstride) &&
1285 (sg_dma_len(ppsg) == sg_dma_len(psg))) {
1286 dev_dbg(chan2dev(chan),
1287 "%s: desc 0x%p can be merged with desc 0x%p\n",
1288 __func__, pdesc, ppdesc);
1289
1290 /*
1291 * Increment the block count of the
1292 * N-2 descriptor
1293 */
1294 at_xdmac_increment_block_count(chan, ppdesc);
1295 ppdesc->lld.mbr_dus = stride;
1296
1297 /*
1298 * Put back the N-1 descriptor in the
1299 * free descriptor list
1300 */
1301 list_add_tail(&pdesc->desc_node,
1302 &atchan->free_descs_list);
1303
1304 /*
1305 * Make our N-1 descriptor pointer
1306 * point to the N-2 since they were
1307 * actually merged.
1308 */
1309 pdesc = ppdesc;
1310
1311 /*
1312 * Rule out the case where we don't have
1313 * pstride computed yet (our second sg
1314 * element)
1315 *
1316 * We also want to catch the case where there
1317 * would be a negative stride,
1318 */
1319 } else if (pstride ||
1320 sg_dma_address(sg) < sg_dma_address(psg)) {
1321 /*
1322 * Queue the N-1 descriptor after the
1323 * N-2
1324 */
1325 at_xdmac_queue_desc(chan, ppdesc, pdesc);
1326
1327 /*
1328 * Add the N-1 descriptor to the list
1329 * of the descriptors used for this
1330 * transfer
1331 */
1332 list_add_tail(&desc->desc_node,
1333 &first->descs_list);
1334 dev_dbg(chan2dev(chan),
1335 "%s: add desc 0x%p to descs_list 0x%p\n",
1336 __func__, desc, first);
1337 }
1338 }
1339
1340 /*
1341 * If we are the last element, just see if we have the
1342 * same size than the previous element.
1343 *
1344 * If so, we can merge it with the previous descriptor
1345 * since we don't care about the stride anymore.
1346 */
1347 if ((i == (sg_len - 1)) &&
1348 sg_dma_len(ppsg) == sg_dma_len(psg)) {
1349 dev_dbg(chan2dev(chan),
1350 "%s: desc 0x%p can be merged with desc 0x%p\n",
1351 __func__, desc, pdesc);
1352
1353 /*
1354 * Increment the block count of the N-1
1355 * descriptor
1356 */
1357 at_xdmac_increment_block_count(chan, pdesc);
1358 pdesc->lld.mbr_dus = stride;
1359
1360 /*
1361 * Put back the N descriptor in the free
1362 * descriptor list
1363 */
1364 list_add_tail(&desc->desc_node,
1365 &atchan->free_descs_list);
1366 }
1367
1368 /* Update our descriptors */
1369 ppdesc = pdesc;
1370 pdesc = desc;
1371
1372 /* Update our scatter pointers */
1373 ppsg = psg;
1374 psg = sg;
1375
1376 len += sg_dma_len(sg);
1377 }
1378
1379 first->tx_dma_desc.cookie = -EBUSY;
1380 first->tx_dma_desc.flags = flags;
1381 first->xfer_size = len;
1382
1383 return &first->tx_dma_desc;
1384}
1385
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001386static enum dma_status
1387at_xdmac_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
1388 struct dma_tx_state *txstate)
1389{
1390 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1391 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
1392 struct at_xdmac_desc *desc, *_desc;
1393 struct list_head *descs_list;
1394 enum dma_status ret;
1395 int residue;
Cyrille Pitchen4e097822014-11-13 11:52:41 +01001396 u32 cur_nda, mask, value;
Ludovic Desrochesbe835072015-01-27 16:30:31 +01001397 u8 dwidth = 0;
Ludovic Desroches4c374fc2015-06-08 10:33:14 +02001398 unsigned long flags;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001399
1400 ret = dma_cookie_status(chan, cookie, txstate);
1401 if (ret == DMA_COMPLETE)
1402 return ret;
1403
1404 if (!txstate)
1405 return ret;
1406
Ludovic Desroches4c374fc2015-06-08 10:33:14 +02001407 spin_lock_irqsave(&atchan->lock, flags);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001408
1409 desc = list_first_entry(&atchan->xfers_list, struct at_xdmac_desc, xfer_node);
1410
1411 /*
1412 * If the transfer has not been started yet, don't need to compute the
1413 * residue, it's the transfer length.
1414 */
1415 if (!desc->active_xfer) {
1416 dma_set_residue(txstate, desc->xfer_size);
Ludovic Desroches4c374fc2015-06-08 10:33:14 +02001417 goto spin_unlock;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001418 }
1419
1420 residue = desc->xfer_size;
Cyrille Pitchen4e097822014-11-13 11:52:41 +01001421 /*
1422 * Flush FIFO: only relevant when the transfer is source peripheral
1423 * synchronized.
1424 */
1425 mask = AT_XDMAC_CC_TYPE | AT_XDMAC_CC_DSYNC;
1426 value = AT_XDMAC_CC_TYPE_PER_TRAN | AT_XDMAC_CC_DSYNC_PER2MEM;
Ludovic Desrochesbe835072015-01-27 16:30:31 +01001427 if ((desc->lld.mbr_cfg & mask) == value) {
Cyrille Pitchen4e097822014-11-13 11:52:41 +01001428 at_xdmac_write(atxdmac, AT_XDMAC_GSWF, atchan->mask);
1429 while (!(at_xdmac_chan_read(atchan, AT_XDMAC_CIS) & AT_XDMAC_CIS_FIS))
1430 cpu_relax();
1431 }
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001432
1433 cur_nda = at_xdmac_chan_read(atchan, AT_XDMAC_CNDA) & 0xfffffffc;
1434 /*
1435 * Remove size of all microblocks already transferred and the current
1436 * one. Then add the remaining size to transfer of the current
1437 * microblock.
1438 */
1439 descs_list = &desc->descs_list;
1440 list_for_each_entry_safe(desc, _desc, descs_list, desc_node) {
Ludovic Desrochesbe835072015-01-27 16:30:31 +01001441 dwidth = at_xdmac_get_dwidth(desc->lld.mbr_cfg);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001442 residue -= (desc->lld.mbr_ubc & 0xffffff) << dwidth;
1443 if ((desc->lld.mbr_nda & 0xfffffffc) == cur_nda)
1444 break;
1445 }
1446 residue += at_xdmac_chan_read(atchan, AT_XDMAC_CUBC) << dwidth;
1447
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001448 dma_set_residue(txstate, residue);
1449
1450 dev_dbg(chan2dev(chan),
Vinod Koul82e24242014-11-06 18:02:52 +05301451 "%s: desc=0x%p, tx_dma_desc.phys=%pad, tx_status=%d, cookie=%d, residue=%d\n",
1452 __func__, desc, &desc->tx_dma_desc.phys, ret, cookie, residue);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001453
Ludovic Desroches4c374fc2015-06-08 10:33:14 +02001454spin_unlock:
1455 spin_unlock_irqrestore(&atchan->lock, flags);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001456 return ret;
1457}
1458
1459/* Call must be protected by lock. */
1460static void at_xdmac_remove_xfer(struct at_xdmac_chan *atchan,
1461 struct at_xdmac_desc *desc)
1462{
1463 dev_dbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc);
1464
1465 /*
1466 * Remove the transfer from the transfer list then move the transfer
1467 * descriptors into the free descriptors list.
1468 */
1469 list_del(&desc->xfer_node);
1470 list_splice_init(&desc->descs_list, &atchan->free_descs_list);
1471}
1472
1473static void at_xdmac_advance_work(struct at_xdmac_chan *atchan)
1474{
1475 struct at_xdmac_desc *desc;
Ludovic Desroches4c374fc2015-06-08 10:33:14 +02001476 unsigned long flags;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001477
Ludovic Desroches4c374fc2015-06-08 10:33:14 +02001478 spin_lock_irqsave(&atchan->lock, flags);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001479
1480 /*
1481 * If channel is enabled, do nothing, advance_work will be triggered
1482 * after the interruption.
1483 */
1484 if (!at_xdmac_chan_is_enabled(atchan) && !list_empty(&atchan->xfers_list)) {
1485 desc = list_first_entry(&atchan->xfers_list,
1486 struct at_xdmac_desc,
1487 xfer_node);
1488 dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc);
1489 if (!desc->active_xfer)
1490 at_xdmac_start_xfer(atchan, desc);
1491 }
1492
Ludovic Desroches4c374fc2015-06-08 10:33:14 +02001493 spin_unlock_irqrestore(&atchan->lock, flags);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001494}
1495
1496static void at_xdmac_handle_cyclic(struct at_xdmac_chan *atchan)
1497{
1498 struct at_xdmac_desc *desc;
1499 struct dma_async_tx_descriptor *txd;
1500
1501 desc = list_first_entry(&atchan->xfers_list, struct at_xdmac_desc, xfer_node);
1502 txd = &desc->tx_dma_desc;
1503
1504 if (txd->callback && (txd->flags & DMA_PREP_INTERRUPT))
1505 txd->callback(txd->callback_param);
1506}
1507
1508static void at_xdmac_tasklet(unsigned long data)
1509{
1510 struct at_xdmac_chan *atchan = (struct at_xdmac_chan *)data;
1511 struct at_xdmac_desc *desc;
1512 u32 error_mask;
1513
1514 dev_dbg(chan2dev(&atchan->chan), "%s: status=0x%08lx\n",
1515 __func__, atchan->status);
1516
1517 error_mask = AT_XDMAC_CIS_RBEIS
1518 | AT_XDMAC_CIS_WBEIS
1519 | AT_XDMAC_CIS_ROIS;
1520
1521 if (at_xdmac_chan_is_cyclic(atchan)) {
1522 at_xdmac_handle_cyclic(atchan);
1523 } else if ((atchan->status & AT_XDMAC_CIS_LIS)
1524 || (atchan->status & error_mask)) {
1525 struct dma_async_tx_descriptor *txd;
1526
1527 if (atchan->status & AT_XDMAC_CIS_RBEIS)
1528 dev_err(chan2dev(&atchan->chan), "read bus error!!!");
1529 if (atchan->status & AT_XDMAC_CIS_WBEIS)
1530 dev_err(chan2dev(&atchan->chan), "write bus error!!!");
1531 if (atchan->status & AT_XDMAC_CIS_ROIS)
1532 dev_err(chan2dev(&atchan->chan), "request overflow error!!!");
1533
1534 spin_lock_bh(&atchan->lock);
1535 desc = list_first_entry(&atchan->xfers_list,
1536 struct at_xdmac_desc,
1537 xfer_node);
1538 dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc);
1539 BUG_ON(!desc->active_xfer);
1540
1541 txd = &desc->tx_dma_desc;
1542
1543 at_xdmac_remove_xfer(atchan, desc);
1544 spin_unlock_bh(&atchan->lock);
1545
1546 if (!at_xdmac_chan_is_cyclic(atchan)) {
1547 dma_cookie_complete(txd);
1548 if (txd->callback && (txd->flags & DMA_PREP_INTERRUPT))
1549 txd->callback(txd->callback_param);
1550 }
1551
1552 dma_run_dependencies(txd);
1553
1554 at_xdmac_advance_work(atchan);
1555 }
1556}
1557
1558static irqreturn_t at_xdmac_interrupt(int irq, void *dev_id)
1559{
1560 struct at_xdmac *atxdmac = (struct at_xdmac *)dev_id;
1561 struct at_xdmac_chan *atchan;
1562 u32 imr, status, pending;
1563 u32 chan_imr, chan_status;
1564 int i, ret = IRQ_NONE;
1565
1566 do {
1567 imr = at_xdmac_read(atxdmac, AT_XDMAC_GIM);
1568 status = at_xdmac_read(atxdmac, AT_XDMAC_GIS);
1569 pending = status & imr;
1570
1571 dev_vdbg(atxdmac->dma.dev,
1572 "%s: status=0x%08x, imr=0x%08x, pending=0x%08x\n",
1573 __func__, status, imr, pending);
1574
1575 if (!pending)
1576 break;
1577
1578 /* We have to find which channel has generated the interrupt. */
1579 for (i = 0; i < atxdmac->dma.chancnt; i++) {
1580 if (!((1 << i) & pending))
1581 continue;
1582
1583 atchan = &atxdmac->chan[i];
1584 chan_imr = at_xdmac_chan_read(atchan, AT_XDMAC_CIM);
1585 chan_status = at_xdmac_chan_read(atchan, AT_XDMAC_CIS);
1586 atchan->status = chan_status & chan_imr;
1587 dev_vdbg(atxdmac->dma.dev,
1588 "%s: chan%d: imr=0x%x, status=0x%x\n",
1589 __func__, i, chan_imr, chan_status);
1590 dev_vdbg(chan2dev(&atchan->chan),
1591 "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n",
1592 __func__,
1593 at_xdmac_chan_read(atchan, AT_XDMAC_CC),
1594 at_xdmac_chan_read(atchan, AT_XDMAC_CNDA),
1595 at_xdmac_chan_read(atchan, AT_XDMAC_CNDC),
1596 at_xdmac_chan_read(atchan, AT_XDMAC_CSA),
1597 at_xdmac_chan_read(atchan, AT_XDMAC_CDA),
1598 at_xdmac_chan_read(atchan, AT_XDMAC_CUBC));
1599
1600 if (atchan->status & (AT_XDMAC_CIS_RBEIS | AT_XDMAC_CIS_WBEIS))
1601 at_xdmac_write(atxdmac, AT_XDMAC_GD, atchan->mask);
1602
1603 tasklet_schedule(&atchan->tasklet);
1604 ret = IRQ_HANDLED;
1605 }
1606
1607 } while (pending);
1608
1609 return ret;
1610}
1611
1612static void at_xdmac_issue_pending(struct dma_chan *chan)
1613{
1614 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1615
1616 dev_dbg(chan2dev(&atchan->chan), "%s\n", __func__);
1617
1618 if (!at_xdmac_chan_is_cyclic(atchan))
1619 at_xdmac_advance_work(atchan);
1620
1621 return;
1622}
1623
Ludovic Desroches3d138872014-11-17 14:42:07 +01001624static int at_xdmac_device_config(struct dma_chan *chan,
1625 struct dma_slave_config *config)
1626{
1627 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1628 int ret;
Ludovic Desroches4c374fc2015-06-08 10:33:14 +02001629 unsigned long flags;
Ludovic Desroches3d138872014-11-17 14:42:07 +01001630
1631 dev_dbg(chan2dev(chan), "%s\n", __func__);
1632
Ludovic Desroches4c374fc2015-06-08 10:33:14 +02001633 spin_lock_irqsave(&atchan->lock, flags);
Ludovic Desroches3d138872014-11-17 14:42:07 +01001634 ret = at_xdmac_set_slave_config(chan, config);
Ludovic Desroches4c374fc2015-06-08 10:33:14 +02001635 spin_unlock_irqrestore(&atchan->lock, flags);
Ludovic Desroches3d138872014-11-17 14:42:07 +01001636
1637 return ret;
1638}
1639
1640static int at_xdmac_device_pause(struct dma_chan *chan)
1641{
1642 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1643 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
Ludovic Desroches4c374fc2015-06-08 10:33:14 +02001644 unsigned long flags;
Ludovic Desroches3d138872014-11-17 14:42:07 +01001645
1646 dev_dbg(chan2dev(chan), "%s\n", __func__);
1647
Cyrille Pitchencbb85e62015-01-27 16:30:29 +01001648 if (test_and_set_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status))
1649 return 0;
1650
Ludovic Desroches4c374fc2015-06-08 10:33:14 +02001651 spin_lock_irqsave(&atchan->lock, flags);
Ludovic Desroches3d138872014-11-17 14:42:07 +01001652 at_xdmac_write(atxdmac, AT_XDMAC_GRWS, atchan->mask);
Cyrille Pitchencbb85e62015-01-27 16:30:29 +01001653 while (at_xdmac_chan_read(atchan, AT_XDMAC_CC)
1654 & (AT_XDMAC_CC_WRIP | AT_XDMAC_CC_RDIP))
1655 cpu_relax();
Ludovic Desroches4c374fc2015-06-08 10:33:14 +02001656 spin_unlock_irqrestore(&atchan->lock, flags);
Ludovic Desroches3d138872014-11-17 14:42:07 +01001657
1658 return 0;
1659}
1660
1661static int at_xdmac_device_resume(struct dma_chan *chan)
1662{
1663 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1664 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
Ludovic Desroches4c374fc2015-06-08 10:33:14 +02001665 unsigned long flags;
Ludovic Desroches3d138872014-11-17 14:42:07 +01001666
1667 dev_dbg(chan2dev(chan), "%s\n", __func__);
1668
Ludovic Desroches4c374fc2015-06-08 10:33:14 +02001669 spin_lock_irqsave(&atchan->lock, flags);
Niklas Cassel0434a232015-04-07 16:42:45 +02001670 if (!at_xdmac_chan_is_paused(atchan)) {
Ludovic Desroches4c374fc2015-06-08 10:33:14 +02001671 spin_unlock_irqrestore(&atchan->lock, flags);
Ludovic Desroches3d138872014-11-17 14:42:07 +01001672 return 0;
Niklas Cassel0434a232015-04-07 16:42:45 +02001673 }
Ludovic Desroches3d138872014-11-17 14:42:07 +01001674
1675 at_xdmac_write(atxdmac, AT_XDMAC_GRWR, atchan->mask);
1676 clear_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status);
Ludovic Desroches4c374fc2015-06-08 10:33:14 +02001677 spin_unlock_irqrestore(&atchan->lock, flags);
Ludovic Desroches3d138872014-11-17 14:42:07 +01001678
1679 return 0;
1680}
1681
1682static int at_xdmac_device_terminate_all(struct dma_chan *chan)
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001683{
1684 struct at_xdmac_desc *desc, *_desc;
1685 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1686 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
Ludovic Desroches4c374fc2015-06-08 10:33:14 +02001687 unsigned long flags;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001688
Ludovic Desroches3d138872014-11-17 14:42:07 +01001689 dev_dbg(chan2dev(chan), "%s\n", __func__);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001690
Ludovic Desroches4c374fc2015-06-08 10:33:14 +02001691 spin_lock_irqsave(&atchan->lock, flags);
Ludovic Desroches3d138872014-11-17 14:42:07 +01001692 at_xdmac_write(atxdmac, AT_XDMAC_GD, atchan->mask);
1693 while (at_xdmac_read(atxdmac, AT_XDMAC_GS) & atchan->mask)
1694 cpu_relax();
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001695
Ludovic Desroches3d138872014-11-17 14:42:07 +01001696 /* Cancel all pending transfers. */
1697 list_for_each_entry_safe(desc, _desc, &atchan->xfers_list, xfer_node)
1698 at_xdmac_remove_xfer(atchan, desc);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001699
Songjun Wu611dcad2016-01-18 11:14:44 +01001700 clear_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status);
Ludovic Desroches3d138872014-11-17 14:42:07 +01001701 clear_bit(AT_XDMAC_CHAN_IS_CYCLIC, &atchan->status);
Ludovic Desroches4c374fc2015-06-08 10:33:14 +02001702 spin_unlock_irqrestore(&atchan->lock, flags);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001703
Ludovic Desroches3d138872014-11-17 14:42:07 +01001704 return 0;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001705}
1706
1707static int at_xdmac_alloc_chan_resources(struct dma_chan *chan)
1708{
1709 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1710 struct at_xdmac_desc *desc;
1711 int i;
Ludovic Desroches4c374fc2015-06-08 10:33:14 +02001712 unsigned long flags;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001713
Ludovic Desroches4c374fc2015-06-08 10:33:14 +02001714 spin_lock_irqsave(&atchan->lock, flags);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001715
1716 if (at_xdmac_chan_is_enabled(atchan)) {
1717 dev_err(chan2dev(chan),
1718 "can't allocate channel resources (channel enabled)\n");
1719 i = -EIO;
1720 goto spin_unlock;
1721 }
1722
1723 if (!list_empty(&atchan->free_descs_list)) {
1724 dev_err(chan2dev(chan),
1725 "can't allocate channel resources (channel not free from a previous use)\n");
1726 i = -EIO;
1727 goto spin_unlock;
1728 }
1729
1730 for (i = 0; i < init_nr_desc_per_channel; i++) {
1731 desc = at_xdmac_alloc_desc(chan, GFP_ATOMIC);
1732 if (!desc) {
1733 dev_warn(chan2dev(chan),
1734 "only %d descriptors have been allocated\n", i);
1735 break;
1736 }
1737 list_add_tail(&desc->desc_node, &atchan->free_descs_list);
1738 }
1739
1740 dma_cookie_init(chan);
1741
1742 dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i);
1743
1744spin_unlock:
Ludovic Desroches4c374fc2015-06-08 10:33:14 +02001745 spin_unlock_irqrestore(&atchan->lock, flags);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001746 return i;
1747}
1748
1749static void at_xdmac_free_chan_resources(struct dma_chan *chan)
1750{
1751 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1752 struct at_xdmac *atxdmac = to_at_xdmac(chan->device);
1753 struct at_xdmac_desc *desc, *_desc;
1754
1755 list_for_each_entry_safe(desc, _desc, &atchan->free_descs_list, desc_node) {
1756 dev_dbg(chan2dev(chan), "%s: freeing descriptor %p\n", __func__, desc);
1757 list_del(&desc->desc_node);
1758 dma_pool_free(atxdmac->at_xdmac_desc_pool, desc, desc->tx_dma_desc.phys);
1759 }
1760
1761 return;
1762}
1763
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001764#ifdef CONFIG_PM
1765static int atmel_xdmac_prepare(struct device *dev)
1766{
1767 struct platform_device *pdev = to_platform_device(dev);
1768 struct at_xdmac *atxdmac = platform_get_drvdata(pdev);
1769 struct dma_chan *chan, *_chan;
1770
1771 list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) {
1772 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1773
1774 /* Wait for transfer completion, except in cyclic case. */
1775 if (at_xdmac_chan_is_enabled(atchan) && !at_xdmac_chan_is_cyclic(atchan))
1776 return -EAGAIN;
1777 }
1778 return 0;
1779}
1780#else
1781# define atmel_xdmac_prepare NULL
1782#endif
1783
1784#ifdef CONFIG_PM_SLEEP
1785static int atmel_xdmac_suspend(struct device *dev)
1786{
1787 struct platform_device *pdev = to_platform_device(dev);
1788 struct at_xdmac *atxdmac = platform_get_drvdata(pdev);
1789 struct dma_chan *chan, *_chan;
1790
1791 list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) {
1792 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1793
Ludovic Desroches734bb9a2015-01-27 16:30:30 +01001794 atchan->save_cc = at_xdmac_chan_read(atchan, AT_XDMAC_CC);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001795 if (at_xdmac_chan_is_cyclic(atchan)) {
1796 if (!at_xdmac_chan_is_paused(atchan))
Ludovic Desroches3d138872014-11-17 14:42:07 +01001797 at_xdmac_device_pause(chan);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001798 atchan->save_cim = at_xdmac_chan_read(atchan, AT_XDMAC_CIM);
1799 atchan->save_cnda = at_xdmac_chan_read(atchan, AT_XDMAC_CNDA);
1800 atchan->save_cndc = at_xdmac_chan_read(atchan, AT_XDMAC_CNDC);
1801 }
1802 }
1803 atxdmac->save_gim = at_xdmac_read(atxdmac, AT_XDMAC_GIM);
1804
1805 at_xdmac_off(atxdmac);
1806 clk_disable_unprepare(atxdmac->clk);
1807 return 0;
1808}
1809
1810static int atmel_xdmac_resume(struct device *dev)
1811{
1812 struct platform_device *pdev = to_platform_device(dev);
1813 struct at_xdmac *atxdmac = platform_get_drvdata(pdev);
1814 struct at_xdmac_chan *atchan;
1815 struct dma_chan *chan, *_chan;
1816 int i;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001817
1818 clk_prepare_enable(atxdmac->clk);
1819
1820 /* Clear pending interrupts. */
1821 for (i = 0; i < atxdmac->dma.chancnt; i++) {
1822 atchan = &atxdmac->chan[i];
1823 while (at_xdmac_chan_read(atchan, AT_XDMAC_CIS))
1824 cpu_relax();
1825 }
1826
1827 at_xdmac_write(atxdmac, AT_XDMAC_GIE, atxdmac->save_gim);
1828 at_xdmac_write(atxdmac, AT_XDMAC_GE, atxdmac->save_gs);
1829 list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) {
1830 atchan = to_at_xdmac_chan(chan);
Ludovic Desroches734bb9a2015-01-27 16:30:30 +01001831 at_xdmac_chan_write(atchan, AT_XDMAC_CC, atchan->save_cc);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001832 if (at_xdmac_chan_is_cyclic(atchan)) {
Songjun Wu611dcad2016-01-18 11:14:44 +01001833 if (at_xdmac_chan_is_paused(atchan))
1834 at_xdmac_device_resume(chan);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001835 at_xdmac_chan_write(atchan, AT_XDMAC_CNDA, atchan->save_cnda);
1836 at_xdmac_chan_write(atchan, AT_XDMAC_CNDC, atchan->save_cndc);
1837 at_xdmac_chan_write(atchan, AT_XDMAC_CIE, atchan->save_cim);
1838 wmb();
1839 at_xdmac_write(atxdmac, AT_XDMAC_GE, atchan->mask);
1840 }
1841 }
1842 return 0;
1843}
1844#endif /* CONFIG_PM_SLEEP */
1845
1846static int at_xdmac_probe(struct platform_device *pdev)
1847{
1848 struct resource *res;
1849 struct at_xdmac *atxdmac;
1850 int irq, size, nr_channels, i, ret;
1851 void __iomem *base;
1852 u32 reg;
1853
1854 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1855 if (!res)
1856 return -EINVAL;
1857
1858 irq = platform_get_irq(pdev, 0);
1859 if (irq < 0)
1860 return irq;
1861
1862 base = devm_ioremap_resource(&pdev->dev, res);
1863 if (IS_ERR(base))
1864 return PTR_ERR(base);
1865
1866 /*
1867 * Read number of xdmac channels, read helper function can't be used
1868 * since atxdmac is not yet allocated and we need to know the number
1869 * of channels to do the allocation.
1870 */
1871 reg = readl_relaxed(base + AT_XDMAC_GTYPE);
1872 nr_channels = AT_XDMAC_NB_CH(reg);
1873 if (nr_channels > AT_XDMAC_MAX_CHAN) {
1874 dev_err(&pdev->dev, "invalid number of channels (%u)\n",
1875 nr_channels);
1876 return -EINVAL;
1877 }
1878
1879 size = sizeof(*atxdmac);
1880 size += nr_channels * sizeof(struct at_xdmac_chan);
1881 atxdmac = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
1882 if (!atxdmac) {
1883 dev_err(&pdev->dev, "can't allocate at_xdmac structure\n");
1884 return -ENOMEM;
1885 }
1886
1887 atxdmac->regs = base;
1888 atxdmac->irq = irq;
1889
1890 atxdmac->clk = devm_clk_get(&pdev->dev, "dma_clk");
1891 if (IS_ERR(atxdmac->clk)) {
1892 dev_err(&pdev->dev, "can't get dma_clk\n");
1893 return PTR_ERR(atxdmac->clk);
1894 }
1895
1896 /* Do not use dev res to prevent races with tasklet */
1897 ret = request_irq(atxdmac->irq, at_xdmac_interrupt, 0, "at_xdmac", atxdmac);
1898 if (ret) {
1899 dev_err(&pdev->dev, "can't request irq\n");
1900 return ret;
1901 }
1902
1903 ret = clk_prepare_enable(atxdmac->clk);
1904 if (ret) {
1905 dev_err(&pdev->dev, "can't prepare or enable clock\n");
1906 goto err_free_irq;
1907 }
1908
1909 atxdmac->at_xdmac_desc_pool =
1910 dmam_pool_create(dev_name(&pdev->dev), &pdev->dev,
1911 sizeof(struct at_xdmac_desc), 4, 0);
1912 if (!atxdmac->at_xdmac_desc_pool) {
1913 dev_err(&pdev->dev, "no memory for descriptors dma pool\n");
1914 ret = -ENOMEM;
1915 goto err_clk_disable;
1916 }
1917
1918 dma_cap_set(DMA_CYCLIC, atxdmac->dma.cap_mask);
Maxime Ripard6007ccb2015-05-07 17:38:11 +02001919 dma_cap_set(DMA_INTERLEAVE, atxdmac->dma.cap_mask);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001920 dma_cap_set(DMA_MEMCPY, atxdmac->dma.cap_mask);
Maxime Ripardb206d9a2015-05-18 13:46:16 +02001921 dma_cap_set(DMA_MEMSET, atxdmac->dma.cap_mask);
Maxime Ripard67a6eed2015-07-06 12:19:24 +02001922 dma_cap_set(DMA_MEMSET_SG, atxdmac->dma.cap_mask);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001923 dma_cap_set(DMA_SLAVE, atxdmac->dma.cap_mask);
Ludovic Desrochesfef4cbf2014-11-13 11:52:45 +01001924 /*
1925 * Without DMA_PRIVATE the driver is not able to allocate more than
1926 * one channel, second allocation fails in private_candidate.
1927 */
1928 dma_cap_set(DMA_PRIVATE, atxdmac->dma.cap_mask);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001929 atxdmac->dma.dev = &pdev->dev;
1930 atxdmac->dma.device_alloc_chan_resources = at_xdmac_alloc_chan_resources;
1931 atxdmac->dma.device_free_chan_resources = at_xdmac_free_chan_resources;
1932 atxdmac->dma.device_tx_status = at_xdmac_tx_status;
1933 atxdmac->dma.device_issue_pending = at_xdmac_issue_pending;
1934 atxdmac->dma.device_prep_dma_cyclic = at_xdmac_prep_dma_cyclic;
Maxime Ripard6007ccb2015-05-07 17:38:11 +02001935 atxdmac->dma.device_prep_interleaved_dma = at_xdmac_prep_interleaved;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001936 atxdmac->dma.device_prep_dma_memcpy = at_xdmac_prep_dma_memcpy;
Maxime Ripardb206d9a2015-05-18 13:46:16 +02001937 atxdmac->dma.device_prep_dma_memset = at_xdmac_prep_dma_memset;
Maxime Ripard67a6eed2015-07-06 12:19:24 +02001938 atxdmac->dma.device_prep_dma_memset_sg = at_xdmac_prep_dma_memset_sg;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001939 atxdmac->dma.device_prep_slave_sg = at_xdmac_prep_slave_sg;
Ludovic Desroches3d138872014-11-17 14:42:07 +01001940 atxdmac->dma.device_config = at_xdmac_device_config;
1941 atxdmac->dma.device_pause = at_xdmac_device_pause;
1942 atxdmac->dma.device_resume = at_xdmac_device_resume;
1943 atxdmac->dma.device_terminate_all = at_xdmac_device_terminate_all;
Ludovic Desroches8ac82f82014-11-17 14:42:44 +01001944 atxdmac->dma.src_addr_widths = AT_XDMAC_DMA_BUSWIDTHS;
1945 atxdmac->dma.dst_addr_widths = AT_XDMAC_DMA_BUSWIDTHS;
1946 atxdmac->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1947 atxdmac->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001948
1949 /* Disable all chans and interrupts. */
1950 at_xdmac_off(atxdmac);
1951
1952 /* Init channels. */
1953 INIT_LIST_HEAD(&atxdmac->dma.channels);
1954 for (i = 0; i < nr_channels; i++) {
1955 struct at_xdmac_chan *atchan = &atxdmac->chan[i];
1956
1957 atchan->chan.device = &atxdmac->dma;
1958 list_add_tail(&atchan->chan.device_node,
1959 &atxdmac->dma.channels);
1960
1961 atchan->ch_regs = at_xdmac_chan_reg_base(atxdmac, i);
1962 atchan->mask = 1 << i;
1963
1964 spin_lock_init(&atchan->lock);
1965 INIT_LIST_HEAD(&atchan->xfers_list);
1966 INIT_LIST_HEAD(&atchan->free_descs_list);
1967 tasklet_init(&atchan->tasklet, at_xdmac_tasklet,
1968 (unsigned long)atchan);
1969
1970 /* Clear pending interrupts. */
1971 while (at_xdmac_chan_read(atchan, AT_XDMAC_CIS))
1972 cpu_relax();
1973 }
1974 platform_set_drvdata(pdev, atxdmac);
1975
1976 ret = dma_async_device_register(&atxdmac->dma);
1977 if (ret) {
1978 dev_err(&pdev->dev, "fail to register DMA engine device\n");
1979 goto err_clk_disable;
1980 }
1981
1982 ret = of_dma_controller_register(pdev->dev.of_node,
1983 at_xdmac_xlate, atxdmac);
1984 if (ret) {
1985 dev_err(&pdev->dev, "could not register of dma controller\n");
1986 goto err_dma_unregister;
1987 }
1988
1989 dev_info(&pdev->dev, "%d channels, mapped at 0x%p\n",
1990 nr_channels, atxdmac->regs);
1991
1992 return 0;
1993
1994err_dma_unregister:
1995 dma_async_device_unregister(&atxdmac->dma);
1996err_clk_disable:
1997 clk_disable_unprepare(atxdmac->clk);
1998err_free_irq:
1999 free_irq(atxdmac->irq, atxdmac->dma.dev);
2000 return ret;
2001}
2002
2003static int at_xdmac_remove(struct platform_device *pdev)
2004{
2005 struct at_xdmac *atxdmac = (struct at_xdmac *)platform_get_drvdata(pdev);
2006 int i;
2007
2008 at_xdmac_off(atxdmac);
2009 of_dma_controller_free(pdev->dev.of_node);
2010 dma_async_device_unregister(&atxdmac->dma);
2011 clk_disable_unprepare(atxdmac->clk);
2012
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02002013 free_irq(atxdmac->irq, atxdmac->dma.dev);
2014
2015 for (i = 0; i < atxdmac->dma.chancnt; i++) {
2016 struct at_xdmac_chan *atchan = &atxdmac->chan[i];
2017
2018 tasklet_kill(&atchan->tasklet);
2019 at_xdmac_free_chan_resources(&atchan->chan);
2020 }
2021
2022 return 0;
2023}
2024
2025static const struct dev_pm_ops atmel_xdmac_dev_pm_ops = {
2026 .prepare = atmel_xdmac_prepare,
2027 SET_LATE_SYSTEM_SLEEP_PM_OPS(atmel_xdmac_suspend, atmel_xdmac_resume)
2028};
2029
2030static const struct of_device_id atmel_xdmac_dt_ids[] = {
2031 {
2032 .compatible = "atmel,sama5d4-dma",
2033 }, {
2034 /* sentinel */
2035 }
2036};
2037MODULE_DEVICE_TABLE(of, atmel_xdmac_dt_ids);
2038
2039static struct platform_driver at_xdmac_driver = {
2040 .probe = at_xdmac_probe,
2041 .remove = at_xdmac_remove,
2042 .driver = {
2043 .name = "at_xdmac",
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02002044 .of_match_table = of_match_ptr(atmel_xdmac_dt_ids),
2045 .pm = &atmel_xdmac_dev_pm_ops,
2046 }
2047};
2048
2049static int __init at_xdmac_init(void)
2050{
2051 return platform_driver_probe(&at_xdmac_driver, at_xdmac_probe);
2052}
2053subsys_initcall(at_xdmac_init);
2054
2055MODULE_DESCRIPTION("Atmel Extended DMA Controller driver");
2056MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>");
2057MODULE_LICENSE("GPL");