blob: 3067673d54f69cadf896e19f7aee1d3ed11e9117 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
David Brownell75862692005-09-23 17:14:37 -070010 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
12 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070013 * The bridge optimization stuff has been removed. If you really
14 * have a silly BIOS which is unable to set your host bridge right,
15 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
16 */
17
Linus Torvalds1da177e2005-04-16 15:20:36 -070018#include <linux/types.h>
19#include <linux/kernel.h>
20#include <linux/pci.h>
21#include <linux/init.h>
22#include <linux/delay.h>
Len Brown25be5e62005-05-27 04:21:50 -040023#include <linux/acpi.h>
bjorn.helgaas@hp.com9f23ed32007-12-17 14:09:38 -070024#include <linux/kallsyms.h>
Andreas Petlund75e07fc2008-11-20 20:42:25 -080025#include <linux/dmi.h>
Alexander Duyck649426e2009-03-05 13:57:28 -050026#include <linux/pci-aspm.h>
Yuji Shimada32a9a6822009-03-16 17:13:39 +090027#include <linux/ioport.h>
Greg KHbc56b9e2005-04-08 14:53:31 +090028#include "pci.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
Thomas Petazzoni3d137312008-08-19 10:28:24 +020030int isa_dma_bridge_buggy;
31EXPORT_SYMBOL(isa_dma_bridge_buggy);
32int pci_pci_problems;
33EXPORT_SYMBOL(pci_pci_problems);
34int pcie_mch_quirk;
35EXPORT_SYMBOL(pcie_mch_quirk);
36
37#ifdef CONFIG_PCI_QUIRKS
Yuji Shimada32a9a6822009-03-16 17:13:39 +090038/*
Yuji Shimada0cdbe302009-04-06 10:24:21 +090039 * This quirk function disables memory decoding and releases memory resources
40 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
Yuji Shimada32a9a6822009-03-16 17:13:39 +090041 * It also rounds up size to specified alignment.
42 * Later on, the kernel will assign page-aligned memory resource back
Yuji Shimada0cdbe302009-04-06 10:24:21 +090043 * to the device.
Yuji Shimada32a9a6822009-03-16 17:13:39 +090044 */
45static void __devinit quirk_resource_alignment(struct pci_dev *dev)
46{
47 int i;
48 struct resource *r;
49 resource_size_t align, size;
Yuji Shimada0cdbe302009-04-06 10:24:21 +090050 u16 command;
Yuji Shimada32a9a6822009-03-16 17:13:39 +090051
52 if (!pci_is_reassigndev(dev))
53 return;
54
55 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
56 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
57 dev_warn(&dev->dev,
58 "Can't reassign resources to host bridge.\n");
59 return;
60 }
61
Yuji Shimada0cdbe302009-04-06 10:24:21 +090062 dev_info(&dev->dev,
63 "Disabling memory decoding and releasing memory resources.\n");
64 pci_read_config_word(dev, PCI_COMMAND, &command);
65 command &= ~PCI_COMMAND_MEMORY;
66 pci_write_config_word(dev, PCI_COMMAND, command);
Yuji Shimada32a9a6822009-03-16 17:13:39 +090067
68 align = pci_specified_resource_alignment(dev);
69 for (i=0; i < PCI_BRIDGE_RESOURCES; i++) {
70 r = &dev->resource[i];
71 if (!(r->flags & IORESOURCE_MEM))
72 continue;
73 size = resource_size(r);
74 if (size < align) {
75 size = align;
76 dev_info(&dev->dev,
77 "Rounding up size of resource #%d to %#llx.\n",
78 i, (unsigned long long)size);
79 }
80 r->end = size - 1;
81 r->start = 0;
82 }
83 /* Need to disable bridge's resource window,
84 * to enable the kernel to reassign new resource
85 * window later on.
86 */
87 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
88 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
89 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
90 r = &dev->resource[i];
91 if (!(r->flags & IORESOURCE_MEM))
92 continue;
93 r->end = resource_size(r) - 1;
94 r->start = 0;
95 }
96 pci_disable_bridge_window(dev);
97 }
98}
99DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_resource_alignment);
100
Doug Thompsonbd8481e2006-05-08 17:06:09 -0700101/* The Mellanox Tavor device gives false positive parity errors
102 * Mark this device with a broken_parity_status, to allow
103 * PCI scanning code to "skip" this now blacklisted device.
104 */
105static void __devinit quirk_mellanox_tavor(struct pci_dev *dev)
106{
107 dev->broken_parity_status = 1; /* This device gives false positives */
108}
109DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor);
110DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor);
111
Linus Torvalds1da177e2005-04-16 15:20:36 -0700112/* Deal with broken BIOS'es that neglect to enable passive release,
113 which can cause problems in combination with the 82441FX/PPro MTRRs */
Alan Cox1597cac2006-12-04 15:14:45 -0800114static void quirk_passive_release(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700115{
116 struct pci_dev *d = NULL;
117 unsigned char dlc;
118
119 /* We have to make sure a particular bit is set in the PIIX3
120 ISA bridge, so we have to go out and find it. */
121 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
122 pci_read_config_byte(d, 0x82, &dlc);
123 if (!(dlc & 1<<1)) {
Adam Jackson999da9f2008-12-01 14:30:29 -0800124 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700125 dlc |= 1<<1;
126 pci_write_config_byte(d, 0x82, dlc);
127 }
128 }
129}
Andrew Morton652c5382007-11-21 15:07:13 -0800130DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
131DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700132
133/* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
134 but VIA don't answer queries. If you happen to have good contacts at VIA
135 ask them for me please -- Alan
136
137 This appears to be BIOS not version dependent. So presumably there is a
138 chipset level fix */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700139
140static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
141{
142 if (!isa_dma_bridge_buggy) {
143 isa_dma_bridge_buggy=1;
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700144 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700145 }
146}
147 /*
148 * Its not totally clear which chipsets are the problematic ones
149 * We know 82C586 and 82C596 variants are affected.
150 */
Andrew Morton652c5382007-11-21 15:07:13 -0800151DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
152DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
153DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
154DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
155DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
156DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
157DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700158
Linus Torvalds1da177e2005-04-16 15:20:36 -0700159/*
160 * Chipsets where PCI->PCI transfers vanish or hang
161 */
162static void __devinit quirk_nopcipci(struct pci_dev *dev)
163{
164 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700165 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700166 pci_pci_problems |= PCIPCI_FAIL;
167 }
168}
Andrew Morton652c5382007-11-21 15:07:13 -0800169DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
170DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
Alan Cox236561e2006-09-30 23:27:03 -0700171
172static void __devinit quirk_nopciamd(struct pci_dev *dev)
173{
174 u8 rev;
175 pci_read_config_byte(dev, 0x08, &rev);
176 if (rev == 0x13) {
177 /* Erratum 24 */
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700178 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
Alan Cox236561e2006-09-30 23:27:03 -0700179 pci_pci_problems |= PCIAGP_FAIL;
180 }
181}
Andrew Morton652c5382007-11-21 15:07:13 -0800182DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700183
184/*
185 * Triton requires workarounds to be used by the drivers
186 */
187static void __devinit quirk_triton(struct pci_dev *dev)
188{
189 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700190 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700191 pci_pci_problems |= PCIPCI_TRITON;
192 }
193}
Andrew Morton652c5382007-11-21 15:07:13 -0800194DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
195DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
196DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
197DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700198
199/*
200 * VIA Apollo KT133 needs PCI latency patch
201 * Made according to a windows driver based patch by George E. Breese
202 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
203 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
204 * the info on which Mr Breese based his work.
205 *
206 * Updated based on further information from the site and also on
207 * information provided by VIA
208 */
Alan Cox1597cac2006-12-04 15:14:45 -0800209static void quirk_vialatency(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700210{
211 struct pci_dev *p;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700212 u8 busarb;
213 /* Ok we have a potential problem chipset here. Now see if we have
214 a buggy southbridge */
215
216 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
217 if (p!=NULL) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700218 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
219 /* Check for buggy part revisions */
Auke Kok2b1afa82007-10-29 14:55:02 -0700220 if (p->revision < 0x40 || p->revision > 0x42)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700221 goto exit;
222 } else {
223 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
224 if (p==NULL) /* No problem parts */
225 goto exit;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700226 /* Check for buggy part revisions */
Auke Kok2b1afa82007-10-29 14:55:02 -0700227 if (p->revision < 0x10 || p->revision > 0x12)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700228 goto exit;
229 }
230
231 /*
232 * Ok we have the problem. Now set the PCI master grant to
233 * occur every master grant. The apparent bug is that under high
234 * PCI load (quite common in Linux of course) you can get data
235 * loss when the CPU is held off the bus for 3 bus master requests
236 * This happens to include the IDE controllers....
237 *
238 * VIA only apply this fix when an SB Live! is present but under
239 * both Linux and Windows this isnt enough, and we have seen
240 * corruption without SB Live! but with things like 3 UDMA IDE
241 * controllers. So we ignore that bit of the VIA recommendation..
242 */
243
244 pci_read_config_byte(dev, 0x76, &busarb);
245 /* Set bit 4 and bi 5 of byte 76 to 0x01
246 "Master priority rotation on every PCI master grant */
247 busarb &= ~(1<<5);
248 busarb |= (1<<4);
249 pci_write_config_byte(dev, 0x76, busarb);
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700250 dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700251exit:
252 pci_dev_put(p);
253}
Andrew Morton652c5382007-11-21 15:07:13 -0800254DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
255DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
256DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
Alan Cox1597cac2006-12-04 15:14:45 -0800257/* Must restore this on a resume from RAM */
Andrew Morton652c5382007-11-21 15:07:13 -0800258DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
259DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
260DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700261
262/*
263 * VIA Apollo VP3 needs ETBF on BT848/878
264 */
265static void __devinit quirk_viaetbf(struct pci_dev *dev)
266{
267 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700268 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700269 pci_pci_problems |= PCIPCI_VIAETBF;
270 }
271}
Andrew Morton652c5382007-11-21 15:07:13 -0800272DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700273
274static void __devinit quirk_vsfx(struct pci_dev *dev)
275{
276 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700277 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700278 pci_pci_problems |= PCIPCI_VSFX;
279 }
280}
Andrew Morton652c5382007-11-21 15:07:13 -0800281DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700282
283/*
284 * Ali Magik requires workarounds to be used by the drivers
285 * that DMA to AGP space. Latency must be set to 0xA and triton
286 * workaround applied too
287 * [Info kindly provided by ALi]
288 */
289static void __init quirk_alimagik(struct pci_dev *dev)
290{
291 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700292 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700293 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
294 }
295}
Andrew Morton652c5382007-11-21 15:07:13 -0800296DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
297DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700298
299/*
300 * Natoma has some interesting boundary conditions with Zoran stuff
301 * at least
302 */
303static void __devinit quirk_natoma(struct pci_dev *dev)
304{
305 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700306 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700307 pci_pci_problems |= PCIPCI_NATOMA;
308 }
309}
Andrew Morton652c5382007-11-21 15:07:13 -0800310DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
311DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
312DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
313DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
314DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
315DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700316
317/*
318 * This chip can cause PCI parity errors if config register 0xA0 is read
319 * while DMAs are occurring.
320 */
321static void __devinit quirk_citrine(struct pci_dev *dev)
322{
323 dev->cfg_size = 0xA0;
324}
Andrew Morton652c5382007-11-21 15:07:13 -0800325DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700326
327/*
328 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
329 * If it's needed, re-allocate the region.
330 */
331static void __devinit quirk_s3_64M(struct pci_dev *dev)
332{
333 struct resource *r = &dev->resource[0];
334
335 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
336 r->start = 0;
337 r->end = 0x3ffffff;
338 }
339}
Andrew Morton652c5382007-11-21 15:07:13 -0800340DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
341DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700342
Linus Torvalds6693e742005-10-25 20:40:09 -0700343static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region,
344 unsigned size, int nr, const char *name)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700345{
346 region &= ~(size-1);
347 if (region) {
David S. Miller085ae412005-08-08 13:19:08 -0700348 struct pci_bus_region bus_region;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700349 struct resource *res = dev->resource + nr;
350
351 res->name = pci_name(dev);
352 res->start = region;
353 res->end = region + size - 1;
354 res->flags = IORESOURCE_IO;
David S. Miller085ae412005-08-08 13:19:08 -0700355
356 /* Convert from PCI bus to resource space. */
357 bus_region.start = res->start;
358 bus_region.end = res->end;
359 pcibios_bus_to_resource(dev, res, &bus_region);
360
Linus Torvalds1da177e2005-04-16 15:20:36 -0700361 pci_claim_resource(dev, nr);
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700362 dev_info(&dev->dev, "quirk: region %04x-%04x claimed by %s\n", region, region + size - 1, name);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700363 }
364}
365
366/*
367 * ATI Northbridge setups MCE the processor if you even
368 * read somewhere between 0x3b0->0x3bb or read 0x3d3
369 */
370static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
371{
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700372 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700373 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
374 request_region(0x3b0, 0x0C, "RadeonIGP");
375 request_region(0x3d3, 0x01, "RadeonIGP");
376}
Andrew Morton652c5382007-11-21 15:07:13 -0800377DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700378
379/*
380 * Let's make the southbridge information explicit instead
381 * of having to worry about people probing the ACPI areas,
382 * for example.. (Yes, it happens, and if you read the wrong
383 * ACPI register it will put the machine to sleep with no
384 * way of waking it up again. Bummer).
385 *
386 * ALI M7101: Two IO regions pointed to by words at
387 * 0xE0 (64 bytes of ACPI registers)
388 * 0xE2 (32 bytes of SMB registers)
389 */
390static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
391{
392 u16 region;
393
394 pci_read_config_word(dev, 0xE0, &region);
Linus Torvalds6693e742005-10-25 20:40:09 -0700395 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700396 pci_read_config_word(dev, 0xE2, &region);
Linus Torvalds6693e742005-10-25 20:40:09 -0700397 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700398}
Andrew Morton652c5382007-11-21 15:07:13 -0800399DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700400
Linus Torvalds6693e742005-10-25 20:40:09 -0700401static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
402{
403 u32 devres;
404 u32 mask, size, base;
405
406 pci_read_config_dword(dev, port, &devres);
407 if ((devres & enable) != enable)
408 return;
409 mask = (devres >> 16) & 15;
410 base = devres & 0xffff;
411 size = 16;
412 for (;;) {
413 unsigned bit = size >> 1;
414 if ((bit & mask) == bit)
415 break;
416 size = bit;
417 }
418 /*
419 * For now we only print it out. Eventually we'll want to
420 * reserve it (at least if it's in the 0x1000+ range), but
421 * let's get enough confirmation reports first.
422 */
423 base &= -size;
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700424 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
Linus Torvalds6693e742005-10-25 20:40:09 -0700425}
426
427static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
428{
429 u32 devres;
430 u32 mask, size, base;
431
432 pci_read_config_dword(dev, port, &devres);
433 if ((devres & enable) != enable)
434 return;
435 base = devres & 0xffff0000;
436 mask = (devres & 0x3f) << 16;
437 size = 128 << 16;
438 for (;;) {
439 unsigned bit = size >> 1;
440 if ((bit & mask) == bit)
441 break;
442 size = bit;
443 }
444 /*
445 * For now we only print it out. Eventually we'll want to
446 * reserve it, but let's get enough confirmation reports first.
447 */
448 base &= -size;
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700449 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
Linus Torvalds6693e742005-10-25 20:40:09 -0700450}
451
Linus Torvalds1da177e2005-04-16 15:20:36 -0700452/*
453 * PIIX4 ACPI: Two IO regions pointed to by longwords at
454 * 0x40 (64 bytes of ACPI registers)
Linus Torvalds08db2a72005-10-30 14:40:07 -0800455 * 0x90 (16 bytes of SMB registers)
Linus Torvalds6693e742005-10-25 20:40:09 -0700456 * and a few strange programmable PIIX4 device resources.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700457 */
458static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
459{
Linus Torvalds6693e742005-10-25 20:40:09 -0700460 u32 region, res_a;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700461
462 pci_read_config_dword(dev, 0x40, &region);
Linus Torvalds6693e742005-10-25 20:40:09 -0700463 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700464 pci_read_config_dword(dev, 0x90, &region);
Linus Torvalds08db2a72005-10-30 14:40:07 -0800465 quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
Linus Torvalds6693e742005-10-25 20:40:09 -0700466
467 /* Device resource A has enables for some of the other ones */
468 pci_read_config_dword(dev, 0x5c, &res_a);
469
470 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
471 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
472
473 /* Device resource D is just bitfields for static resources */
474
475 /* Device 12 enabled? */
476 if (res_a & (1 << 29)) {
477 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
478 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
479 }
480 /* Device 13 enabled? */
481 if (res_a & (1 << 30)) {
482 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
483 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
484 }
485 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
486 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700487}
Andrew Morton652c5382007-11-21 15:07:13 -0800488DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
489DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700490
491/*
492 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
493 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
494 * 0x58 (64 bytes of GPIO I/O space)
495 */
496static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
497{
498 u32 region;
499
500 pci_read_config_dword(dev, 0x40, &region);
Linus Torvalds6693e742005-10-25 20:40:09 -0700501 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700502
503 pci_read_config_dword(dev, 0x58, &region);
Linus Torvalds6693e742005-10-25 20:40:09 -0700504 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700505}
Andrew Morton652c5382007-11-21 15:07:13 -0800506DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
507DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
508DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
509DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
510DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
511DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
512DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
513DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
514DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
515DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700516
Linus Torvalds894886e2008-12-06 10:10:10 -0800517static void __devinit ich6_lpc_acpi_gpio(struct pci_dev *dev)
R.Marek@sh.cvut.cz2cea7522005-09-27 21:54:51 +0000518{
519 u32 region;
520
521 pci_read_config_dword(dev, 0x40, &region);
522 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO");
523
524 pci_read_config_dword(dev, 0x48, &region);
525 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO");
526}
Linus Torvalds894886e2008-12-06 10:10:10 -0800527
528static void __devinit ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)
529{
530 u32 val;
531 u32 size, base;
532
533 pci_read_config_dword(dev, reg, &val);
534
535 /* Enabled? */
536 if (!(val & 1))
537 return;
538 base = val & 0xfffc;
539 if (dynsize) {
540 /*
541 * This is not correct. It is 16, 32 or 64 bytes depending on
542 * register D31:F0:ADh bits 5:4.
543 *
544 * But this gets us at least _part_ of it.
545 */
546 size = 16;
547 } else {
548 size = 128;
549 }
550 base &= ~(size-1);
551
552 /* Just print it out for now. We should reserve it after more debugging */
553 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
554}
555
556static void __devinit quirk_ich6_lpc(struct pci_dev *dev)
557{
558 /* Shared ACPI/GPIO decode with all ICH6+ */
559 ich6_lpc_acpi_gpio(dev);
560
561 /* ICH6-specific generic IO decode */
562 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
563 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
564}
565DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
566DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
567
568static void __devinit ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name)
569{
570 u32 val;
571 u32 mask, base;
572
573 pci_read_config_dword(dev, reg, &val);
574
575 /* Enabled? */
576 if (!(val & 1))
577 return;
578
579 /*
580 * IO base in bits 15:2, mask in bits 23:18, both
581 * are dword-based
582 */
583 base = val & 0xfffc;
584 mask = (val >> 16) & 0xfc;
585 mask |= 3;
586
587 /* Just print it out for now. We should reserve it after more debugging */
588 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
589}
590
591/* ICH7-10 has the same common LPC generic IO decode registers */
592static void __devinit quirk_ich7_lpc(struct pci_dev *dev)
593{
594 /* We share the common ACPI/DPIO decode with ICH6 */
595 ich6_lpc_acpi_gpio(dev);
596
597 /* And have 4 ICH7+ generic decodes */
598 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
599 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
600 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
601 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
602}
603DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
604DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
605DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
606DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
607DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
608DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
609DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
610DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
611DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
612DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
613DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
614DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
615DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
R.Marek@sh.cvut.cz2cea7522005-09-27 21:54:51 +0000616
Linus Torvalds1da177e2005-04-16 15:20:36 -0700617/*
618 * VIA ACPI: One IO region pointed to by longword at
619 * 0x48 or 0x20 (256 bytes of ACPI registers)
620 */
621static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
622{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700623 u32 region;
624
Auke Kok651472f2007-08-27 16:18:10 -0700625 if (dev->revision & 0x10) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700626 pci_read_config_dword(dev, 0x48, &region);
627 region &= PCI_BASE_ADDRESS_IO_MASK;
Linus Torvalds6693e742005-10-25 20:40:09 -0700628 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700629 }
630}
Andrew Morton652c5382007-11-21 15:07:13 -0800631DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700632
633/*
634 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
635 * 0x48 (256 bytes of ACPI registers)
636 * 0x70 (128 bytes of hardware monitoring register)
637 * 0x90 (16 bytes of SMB registers)
638 */
639static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
640{
641 u16 hm;
642 u32 smb;
643
644 quirk_vt82c586_acpi(dev);
645
646 pci_read_config_word(dev, 0x70, &hm);
647 hm &= PCI_BASE_ADDRESS_IO_MASK;
Meelis Roos02f313b2005-10-29 13:31:49 +0300648 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700649
650 pci_read_config_dword(dev, 0x90, &smb);
651 smb &= PCI_BASE_ADDRESS_IO_MASK;
Meelis Roos02f313b2005-10-29 13:31:49 +0300652 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700653}
Andrew Morton652c5382007-11-21 15:07:13 -0800654DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700655
Ivan Kokshaysky6d85f292005-08-08 12:55:54 +0400656/*
657 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
658 * 0x88 (128 bytes of power management registers)
659 * 0xd0 (16 bytes of SMB registers)
660 */
661static void __devinit quirk_vt8235_acpi(struct pci_dev *dev)
662{
663 u16 pm, smb;
664
665 pci_read_config_word(dev, 0x88, &pm);
666 pm &= PCI_BASE_ADDRESS_IO_MASK;
Linus Torvalds6693e742005-10-25 20:40:09 -0700667 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
Ivan Kokshaysky6d85f292005-08-08 12:55:54 +0400668
669 pci_read_config_word(dev, 0xd0, &smb);
670 smb &= PCI_BASE_ADDRESS_IO_MASK;
Linus Torvalds6693e742005-10-25 20:40:09 -0700671 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB");
Ivan Kokshaysky6d85f292005-08-08 12:55:54 +0400672}
673DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
674
Linus Torvalds1da177e2005-04-16 15:20:36 -0700675
676#ifdef CONFIG_X86_IO_APIC
677
678#include <asm/io_apic.h>
679
680/*
681 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
682 * devices to the external APIC.
683 *
684 * TODO: When we have device-specific interrupt routers,
685 * this code will go away from quirks.
686 */
Alan Cox1597cac2006-12-04 15:14:45 -0800687static void quirk_via_ioapic(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700688{
689 u8 tmp;
690
691 if (nr_ioapics < 1)
692 tmp = 0; /* nothing routed to external APIC */
693 else
694 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
695
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700696 dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -0700697 tmp == 0 ? "Disa" : "Ena");
698
699 /* Offset 0x58: External APIC IRQ output control */
700 pci_write_config_byte (dev, 0x58, tmp);
701}
Andrew Morton652c5382007-11-21 15:07:13 -0800702DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +0200703DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700704
705/*
Karsten Wiesea1740912005-09-03 15:56:33 -0700706 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
707 * This leads to doubled level interrupt rates.
708 * Set this bit to get rid of cycle wastage.
709 * Otherwise uncritical.
710 */
Alan Cox1597cac2006-12-04 15:14:45 -0800711static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
Karsten Wiesea1740912005-09-03 15:56:33 -0700712{
713 u8 misc_control2;
714#define BYPASS_APIC_DEASSERT 8
715
716 pci_read_config_byte(dev, 0x5B, &misc_control2);
717 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700718 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
Karsten Wiesea1740912005-09-03 15:56:33 -0700719 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
720 }
721}
722DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +0200723DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
Karsten Wiesea1740912005-09-03 15:56:33 -0700724
725/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700726 * The AMD io apic can hang the box when an apic irq is masked.
727 * We check all revs >= B0 (yet not in the pre production!) as the bug
728 * is currently marked NoFix
729 *
730 * We have multiple reports of hangs with this chipset that went away with
Alan Cox236561e2006-09-30 23:27:03 -0700731 * noapic specified. For the moment we assume it's the erratum. We may be wrong
Linus Torvalds1da177e2005-04-16 15:20:36 -0700732 * of course. However the advice is demonstrably good even if so..
733 */
734static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
735{
Auke Kok44c10132007-06-08 15:46:36 -0700736 if (dev->revision >= 0x02) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700737 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
738 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700739 }
740}
Andrew Morton652c5382007-11-21 15:07:13 -0800741DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700742
743static void __init quirk_ioapic_rmw(struct pci_dev *dev)
744{
745 if (dev->devfn == 0 && dev->bus->number == 0)
746 sis_apic_bug = 1;
747}
Andrew Morton652c5382007-11-21 15:07:13 -0800748DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700749#endif /* CONFIG_X86_IO_APIC */
750
Peter Orubad556ad42007-05-15 13:59:13 +0200751/*
752 * Some settings of MMRBC can lead to data corruption so block changes.
753 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
754 */
755static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev)
756{
Auke Kokaa288d42007-08-27 16:17:47 -0700757 if (dev->subordinate && dev->revision <= 0x12) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700758 dev_info(&dev->dev, "AMD8131 rev %x detected; "
759 "disabling PCI-X MMRBC\n", dev->revision);
Peter Orubad556ad42007-05-15 13:59:13 +0200760 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
761 }
762}
763DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700764
765/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700766 * FIXME: it is questionable that quirk_via_acpi
767 * is needed. It shows up as an ISA bridge, and does not
768 * support the PCI_INTERRUPT_LINE register at all. Therefore
769 * it seems like setting the pci_dev's 'irq' to the
770 * value of the ACPI SCI interrupt is only done for convenience.
771 * -jgarzik
772 */
773static void __devinit quirk_via_acpi(struct pci_dev *d)
774{
775 /*
776 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
777 */
778 u8 irq;
779 pci_read_config_byte(d, 0x42, &irq);
780 irq &= 0xf;
781 if (irq && (irq != 2))
782 d->irq = irq;
783}
Andrew Morton652c5382007-11-21 15:07:13 -0800784DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
785DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700786
Daniel Drake09d60292006-09-25 16:52:19 -0700787
788/*
Alan Cox1597cac2006-12-04 15:14:45 -0800789 * VIA bridges which have VLink
Daniel Drake09d60292006-09-25 16:52:19 -0700790 */
Alan Cox1597cac2006-12-04 15:14:45 -0800791
Jean Delvarec06bb5d2007-01-30 14:36:09 -0800792static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
793
794static void quirk_via_bridge(struct pci_dev *dev)
795{
796 /* See what bridge we have and find the device ranges */
797 switch (dev->device) {
798 case PCI_DEVICE_ID_VIA_82C686:
Jean Delvarecb7468e2007-01-31 23:48:12 -0800799 /* The VT82C686 is special, it attaches to PCI and can have
800 any device number. All its subdevices are functions of
801 that single device. */
802 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
803 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
Jean Delvarec06bb5d2007-01-30 14:36:09 -0800804 break;
805 case PCI_DEVICE_ID_VIA_8237:
806 case PCI_DEVICE_ID_VIA_8237A:
807 via_vlink_dev_lo = 15;
808 break;
809 case PCI_DEVICE_ID_VIA_8235:
810 via_vlink_dev_lo = 16;
811 break;
812 case PCI_DEVICE_ID_VIA_8231:
813 case PCI_DEVICE_ID_VIA_8233_0:
814 case PCI_DEVICE_ID_VIA_8233A:
815 case PCI_DEVICE_ID_VIA_8233C_0:
816 via_vlink_dev_lo = 17;
817 break;
818 }
819}
820DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
821DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
822DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
823DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
824DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
825DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
826DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
827DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
Daniel Drake09d60292006-09-25 16:52:19 -0700828
Alan Cox1597cac2006-12-04 15:14:45 -0800829/**
830 * quirk_via_vlink - VIA VLink IRQ number update
831 * @dev: PCI device
832 *
833 * If the device we are dealing with is on a PIC IRQ we need to
834 * ensure that the IRQ line register which usually is not relevant
835 * for PCI cards, is actually written so that interrupts get sent
Jean Delvarec06bb5d2007-01-30 14:36:09 -0800836 * to the right place.
837 * We only do this on systems where a VIA south bridge was detected,
838 * and only for VIA devices on the motherboard (see quirk_via_bridge
839 * above).
Alan Cox1597cac2006-12-04 15:14:45 -0800840 */
841
842static void quirk_via_vlink(struct pci_dev *dev)
Len Brown25be5e62005-05-27 04:21:50 -0400843{
844 u8 irq, new_irq;
845
Jean Delvarec06bb5d2007-01-30 14:36:09 -0800846 /* Check if we have VLink at all */
847 if (via_vlink_dev_lo == -1)
Daniel Drake09d60292006-09-25 16:52:19 -0700848 return;
849
850 new_irq = dev->irq;
851
852 /* Don't quirk interrupts outside the legacy IRQ range */
853 if (!new_irq || new_irq > 15)
854 return;
855
Alan Cox1597cac2006-12-04 15:14:45 -0800856 /* Internal device ? */
Jean Delvarec06bb5d2007-01-30 14:36:09 -0800857 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
858 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
Alan Cox1597cac2006-12-04 15:14:45 -0800859 return;
860
861 /* This is an internal VLink device on a PIC interrupt. The BIOS
862 ought to have set this but may not have, so we redo it */
863
Len Brown25be5e62005-05-27 04:21:50 -0400864 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
865 if (new_irq != irq) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700866 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
867 irq, new_irq);
Len Brown25be5e62005-05-27 04:21:50 -0400868 udelay(15); /* unknown if delay really needed */
869 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
870 }
871}
Alan Cox1597cac2006-12-04 15:14:45 -0800872DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
Len Brown25be5e62005-05-27 04:21:50 -0400873
Linus Torvalds1da177e2005-04-16 15:20:36 -0700874/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700875 * VIA VT82C598 has its device ID settable and many BIOSes
876 * set it to the ID of VT82C597 for backward compatibility.
877 * We need to switch it off to be able to recognize the real
878 * type of the chip.
879 */
880static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
881{
882 pci_write_config_byte(dev, 0xfc, 0);
883 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
884}
Andrew Morton652c5382007-11-21 15:07:13 -0800885DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700886
887/*
888 * CardBus controllers have a legacy base address that enables them
889 * to respond as i82365 pcmcia controllers. We don't want them to
890 * do this even if the Linux CardBus driver is not loaded, because
891 * the Linux i82365 driver does not (and should not) handle CardBus.
892 */
Alan Cox1597cac2006-12-04 15:14:45 -0800893static void quirk_cardbus_legacy(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700894{
895 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
896 return;
897 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
898}
899DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +0200900DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700901
902/*
903 * Following the PCI ordering rules is optional on the AMD762. I'm not
904 * sure what the designers were smoking but let's not inhale...
905 *
906 * To be fair to AMD, it follows the spec by default, its BIOS people
907 * who turn it off!
908 */
Alan Cox1597cac2006-12-04 15:14:45 -0800909static void quirk_amd_ordering(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700910{
911 u32 pcic;
912 pci_read_config_dword(dev, 0x4C, &pcic);
913 if ((pcic&6)!=6) {
914 pcic |= 6;
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700915 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700916 pci_write_config_dword(dev, 0x4C, pcic);
917 pci_read_config_dword(dev, 0x84, &pcic);
918 pcic |= (1<<23); /* Required in this mode */
919 pci_write_config_dword(dev, 0x84, pcic);
920 }
921}
Andrew Morton652c5382007-11-21 15:07:13 -0800922DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +0200923DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700924
925/*
926 * DreamWorks provided workaround for Dunord I-3000 problem
927 *
928 * This card decodes and responds to addresses not apparently
929 * assigned to it. We force a larger allocation to ensure that
930 * nothing gets put too close to it.
931 */
932static void __devinit quirk_dunord ( struct pci_dev * dev )
933{
934 struct resource *r = &dev->resource [1];
935 r->start = 0;
936 r->end = 0xffffff;
937}
Andrew Morton652c5382007-11-21 15:07:13 -0800938DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700939
940/*
941 * i82380FB mobile docking controller: its PCI-to-PCI bridge
942 * is subtractive decoding (transparent), and does indicate this
943 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
944 * instead of 0x01.
945 */
946static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
947{
948 dev->transparent = 1;
949}
Andrew Morton652c5382007-11-21 15:07:13 -0800950DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
951DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700952
953/*
954 * Common misconfiguration of the MediaGX/Geode PCI master that will
955 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
956 * datasheets found at http://www.national.com/ds/GX for info on what
957 * these bits do. <christer@weinigel.se>
958 */
Alan Cox1597cac2006-12-04 15:14:45 -0800959static void quirk_mediagx_master(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700960{
961 u8 reg;
962 pci_read_config_byte(dev, 0x41, &reg);
963 if (reg & 2) {
964 reg &= ~2;
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700965 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700966 pci_write_config_byte(dev, 0x41, reg);
967 }
968}
Andrew Morton652c5382007-11-21 15:07:13 -0800969DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
970DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700971
972/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700973 * Ensure C0 rev restreaming is off. This is normally done by
974 * the BIOS but in the odd case it is not the results are corruption
975 * hence the presence of a Linux check
976 */
Alan Cox1597cac2006-12-04 15:14:45 -0800977static void quirk_disable_pxb(struct pci_dev *pdev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700978{
979 u16 config;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700980
Auke Kok44c10132007-06-08 15:46:36 -0700981 if (pdev->revision != 0x04) /* Only C0 requires this */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700982 return;
983 pci_read_config_word(pdev, 0x40, &config);
984 if (config & (1<<6)) {
985 config &= ~(1<<6);
986 pci_write_config_word(pdev, 0x40, config);
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700987 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700988 }
989}
Andrew Morton652c5382007-11-21 15:07:13 -0800990DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +0200991DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700992
Crane Cai05a7d222008-02-02 13:56:56 +0800993static void __devinit quirk_amd_ide_mode(struct pci_dev *pdev)
Conke Huab174432006-12-19 13:11:37 -0800994{
Crane Cai05a7d222008-02-02 13:56:56 +0800995 /* set sb600/sb700/sb800 sata to ahci mode */
996 u8 tmp;
Conke Huab174432006-12-19 13:11:37 -0800997
Crane Cai05a7d222008-02-02 13:56:56 +0800998 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
999 if (tmp == 0x01) {
Conke Huab174432006-12-19 13:11:37 -08001000 pci_read_config_byte(pdev, 0x40, &tmp);
1001 pci_write_config_byte(pdev, 0x40, tmp|1);
1002 pci_write_config_byte(pdev, 0x9, 1);
1003 pci_write_config_byte(pdev, 0xa, 6);
1004 pci_write_config_byte(pdev, 0x40, tmp);
1005
Conke Huc9f89472007-01-09 05:32:51 -05001006 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
Crane Cai05a7d222008-02-02 13:56:56 +08001007 dev_info(&pdev->dev, "set SATA to AHCI mode\n");
Conke Huab174432006-12-19 13:11:37 -08001008 }
1009}
Crane Cai05a7d222008-02-02 13:56:56 +08001010DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001011DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
Crane Cai05a7d222008-02-02 13:56:56 +08001012DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001013DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
Conke Huab174432006-12-19 13:11:37 -08001014
Linus Torvalds1da177e2005-04-16 15:20:36 -07001015/*
1016 * Serverworks CSB5 IDE does not fully support native mode
1017 */
1018static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
1019{
1020 u8 prog;
1021 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1022 if (prog & 5) {
1023 prog &= ~5;
1024 pdev->class &= ~5;
1025 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
Alan Cox368c73d2006-10-04 00:41:26 +01001026 /* PCI layer will sort out resources */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001027 }
1028}
Andrew Morton652c5382007-11-21 15:07:13 -08001029DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001030
1031/*
1032 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
1033 */
1034static void __init quirk_ide_samemode(struct pci_dev *pdev)
1035{
1036 u8 prog;
1037
1038 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1039
1040 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001041 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001042 prog &= ~5;
1043 pdev->class &= ~5;
1044 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001045 }
1046}
Alan Cox368c73d2006-10-04 00:41:26 +01001047DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001048
Alan Cox979b1792008-07-24 17:18:38 +01001049/*
1050 * Some ATA devices break if put into D3
1051 */
1052
1053static void __devinit quirk_no_ata_d3(struct pci_dev *pdev)
1054{
1055 /* Quirk the legacy ATA devices only. The AHCI ones are ok */
1056 if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE)
1057 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1058}
1059DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, quirk_no_ata_d3);
1060DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, quirk_no_ata_d3);
1061
Linus Torvalds1da177e2005-04-16 15:20:36 -07001062/* This was originally an Alpha specific thing, but it really fits here.
1063 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1064 */
1065static void __init quirk_eisa_bridge(struct pci_dev *dev)
1066{
1067 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1068}
Andrew Morton652c5382007-11-21 15:07:13 -08001069DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001070
Johannes Goecke7daa0c42006-04-20 02:43:17 -07001071
1072/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001073 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1074 * is not activated. The myth is that Asus said that they do not want the
1075 * users to be irritated by just another PCI Device in the Win98 device
1076 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1077 * package 2.7.0 for details)
1078 *
1079 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1080 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
gw.kernel@tnode.comd7698ed2007-08-23 21:22:04 +02001081 * becomes necessary to do this tweak in two steps -- the chosen trigger
1082 * is either the Host bridge (preferred) or on-board VGA controller.
Jean Delvare9208ee82007-03-24 16:56:44 +01001083 *
1084 * Note that we used to unhide the SMBus that way on Toshiba laptops
1085 * (Satellite A40 and Tecra M2) but then found that the thermal management
1086 * was done by SMM code, which could cause unsynchronized concurrent
1087 * accesses to the SMBus registers, with potentially bad effects. Thus you
1088 * should be very careful when adding new entries: if SMM is accessing the
1089 * Intel SMBus, this is a very good reason to leave it hidden.
Jean Delvarea99acc82008-03-28 14:16:04 -07001090 *
1091 * Likewise, many recent laptops use ACPI for thermal management. If the
1092 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1093 * natively, and keeping the SMBus hidden is the right thing to do. If you
1094 * are about to add an entry in the table below, please first disassemble
1095 * the DSDT and double-check that there is no code accessing the SMBus.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001096 */
Vivek Goyal9d24a812007-01-11 01:52:44 +01001097static int asus_hides_smbus;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001098
1099static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
1100{
1101 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1102 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1103 switch(dev->subsystem_device) {
Jean Delvarea00db372005-06-29 17:04:06 +02001104 case 0x8025: /* P4B-LX */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001105 case 0x8070: /* P4B */
1106 case 0x8088: /* P4B533 */
1107 case 0x1626: /* L3C notebook */
1108 asus_hides_smbus = 1;
1109 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001110 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001111 switch(dev->subsystem_device) {
1112 case 0x80b1: /* P4GE-V */
1113 case 0x80b2: /* P4PE */
1114 case 0x8093: /* P4B533-V */
1115 asus_hides_smbus = 1;
1116 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001117 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001118 switch(dev->subsystem_device) {
1119 case 0x8030: /* P4T533 */
1120 asus_hides_smbus = 1;
1121 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001122 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001123 switch (dev->subsystem_device) {
1124 case 0x8070: /* P4G8X Deluxe */
1125 asus_hides_smbus = 1;
1126 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001127 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
Jean Delvare321311a2006-07-31 08:53:15 +02001128 switch (dev->subsystem_device) {
1129 case 0x80c9: /* PU-DLS */
1130 asus_hides_smbus = 1;
1131 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001132 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001133 switch (dev->subsystem_device) {
1134 case 0x1751: /* M2N notebook */
1135 case 0x1821: /* M5N notebook */
1136 asus_hides_smbus = 1;
1137 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001138 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001139 switch (dev->subsystem_device) {
1140 case 0x184b: /* W1N notebook */
1141 case 0x186a: /* M6Ne notebook */
1142 asus_hides_smbus = 1;
1143 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001144 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
Jean Delvare2e457852007-01-05 09:17:56 +01001145 switch (dev->subsystem_device) {
1146 case 0x80f2: /* P4P800-X */
1147 asus_hides_smbus = 1;
1148 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001149 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
R.Marek@sh.cvut.czacc06632005-09-29 08:35:41 +00001150 switch (dev->subsystem_device) {
1151 case 0x1882: /* M6V notebook */
Jean Delvare2d1e1c72006-04-01 16:46:35 +02001152 case 0x1977: /* A6VA notebook */
R.Marek@sh.cvut.czacc06632005-09-29 08:35:41 +00001153 asus_hides_smbus = 1;
1154 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001155 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1156 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1157 switch(dev->subsystem_device) {
1158 case 0x088C: /* HP Compaq nc8000 */
1159 case 0x0890: /* HP Compaq nc6000 */
1160 asus_hides_smbus = 1;
1161 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001162 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001163 switch (dev->subsystem_device) {
1164 case 0x12bc: /* HP D330L */
Jean Delvaree3b1bd52005-09-21 22:26:31 +02001165 case 0x12bd: /* HP D530 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001166 asus_hides_smbus = 1;
1167 }
Jean Delvare677cc642007-11-21 18:29:06 +01001168 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1169 switch (dev->subsystem_device) {
1170 case 0x12bf: /* HP xw4100 */
1171 asus_hides_smbus = 1;
1172 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001173 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1174 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1175 switch(dev->subsystem_device) {
1176 case 0xC00C: /* Samsung P35 notebook */
1177 asus_hides_smbus = 1;
1178 }
Rumen Ivanov Zarevc87f8832005-09-06 13:39:32 -07001179 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1180 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1181 switch(dev->subsystem_device) {
1182 case 0x0058: /* Compaq Evo N620c */
1183 asus_hides_smbus = 1;
1184 }
gw.kernel@tnode.comd7698ed2007-08-23 21:22:04 +02001185 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1186 switch(dev->subsystem_device) {
1187 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1188 /* Motherboard doesn't have Host bridge
1189 * subvendor/subdevice IDs, therefore checking
1190 * its on-board VGA controller */
1191 asus_hides_smbus = 1;
1192 }
David O'Shea8293b0f2009-03-02 09:51:13 +01001193 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
Jean Delvare10260d92008-06-04 13:53:31 +02001194 switch(dev->subsystem_device) {
1195 case 0x00b8: /* Compaq Evo D510 CMT */
1196 case 0x00b9: /* Compaq Evo D510 SFF */
David O'Shea8293b0f2009-03-02 09:51:13 +01001197 /* Motherboard doesn't have Host bridge
1198 * subvendor/subdevice IDs and on-board VGA
1199 * controller is disabled if an AGP card is
1200 * inserted, therefore checking USB UHCI
1201 * Controller #1 */
Jean Delvare10260d92008-06-04 13:53:31 +02001202 asus_hides_smbus = 1;
1203 }
Krzysztof Helt27e46852008-06-08 13:47:02 +02001204 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1205 switch (dev->subsystem_device) {
1206 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1207 /* Motherboard doesn't have host bridge
1208 * subvendor/subdevice IDs, therefore checking
1209 * its on-board VGA controller */
1210 asus_hides_smbus = 1;
1211 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001212 }
1213}
Andrew Morton652c5382007-11-21 15:07:13 -08001214DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1215DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1216DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1217DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
Jean Delvare677cc642007-11-21 18:29:06 +01001218DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
Andrew Morton652c5382007-11-21 15:07:13 -08001219DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1220DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1221DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1222DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1223DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001224
Andrew Morton652c5382007-11-21 15:07:13 -08001225DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
David O'Shea8293b0f2009-03-02 09:51:13 +01001226DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
Krzysztof Helt27e46852008-06-08 13:47:02 +02001227DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
gw.kernel@tnode.comd7698ed2007-08-23 21:22:04 +02001228
Alan Cox1597cac2006-12-04 15:14:45 -08001229static void asus_hides_smbus_lpc(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001230{
1231 u16 val;
1232
1233 if (likely(!asus_hides_smbus))
1234 return;
1235
1236 pci_read_config_word(dev, 0xF2, &val);
1237 if (val & 0x8) {
1238 pci_write_config_word(dev, 0xF2, val & (~0x8));
1239 pci_read_config_word(dev, 0xF2, &val);
1240 if (val & 0x8)
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001241 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001242 else
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001243 dev_info(&dev->dev, "Enabled i801 SMBus device\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001244 }
1245}
Andrew Morton652c5382007-11-21 15:07:13 -08001246DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1247DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1248DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1249DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1250DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1251DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1252DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001253DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1254DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1255DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1256DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1257DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1258DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1259DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001260
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001261/* It appears we just have one such device. If not, we have a warning */
1262static void __iomem *asus_rcba_base;
1263static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
R.Marek@sh.cvut.czacc06632005-09-29 08:35:41 +00001264{
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001265 u32 rcba;
R.Marek@sh.cvut.czacc06632005-09-29 08:35:41 +00001266
1267 if (likely(!asus_hides_smbus))
1268 return;
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001269 WARN_ON(asus_rcba_base);
1270
R.Marek@sh.cvut.czacc06632005-09-29 08:35:41 +00001271 pci_read_config_dword(dev, 0xF0, &rcba);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001272 /* use bits 31:14, 16 kB aligned */
1273 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1274 if (asus_rcba_base == NULL)
1275 return;
1276}
1277
1278static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1279{
1280 u32 val;
1281
1282 if (likely(!asus_hides_smbus || !asus_rcba_base))
1283 return;
1284 /* read the Function Disable register, dword mode only */
1285 val = readl(asus_rcba_base + 0x3418);
1286 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */
1287}
1288
1289static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1290{
1291 if (likely(!asus_hides_smbus || !asus_rcba_base))
1292 return;
1293 iounmap(asus_rcba_base);
1294 asus_rcba_base = NULL;
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001295 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
R.Marek@sh.cvut.czacc06632005-09-29 08:35:41 +00001296}
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001297
1298static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1299{
1300 asus_hides_smbus_lpc_ich6_suspend(dev);
1301 asus_hides_smbus_lpc_ich6_resume_early(dev);
1302 asus_hides_smbus_lpc_ich6_resume(dev);
1303}
Andrew Morton652c5382007-11-21 15:07:13 -08001304DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001305DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1306DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1307DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
Carl-Daniel Hailfingerce007ea2006-05-15 09:44:33 -07001308
Linus Torvalds1da177e2005-04-16 15:20:36 -07001309/*
1310 * SiS 96x south bridge: BIOS typically hides SMBus device...
1311 */
Alan Cox1597cac2006-12-04 15:14:45 -08001312static void quirk_sis_96x_smbus(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001313{
1314 u8 val = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001315 pci_read_config_byte(dev, 0x77, &val);
Mark M. Hoffman2f5c33b2007-01-08 22:11:29 -05001316 if (val & 0x10) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001317 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
Mark M. Hoffman2f5c33b2007-01-08 22:11:29 -05001318 pci_write_config_byte(dev, 0x77, val & ~0x10);
1319 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001320}
Andrew Morton652c5382007-11-21 15:07:13 -08001321DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1322DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1323DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1324DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001325DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1326DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1327DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1328DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001329
Linus Torvalds1da177e2005-04-16 15:20:36 -07001330/*
1331 * ... This is further complicated by the fact that some SiS96x south
1332 * bridges pretend to be 85C503/5513 instead. In that case see if we
1333 * spotted a compatible north bridge to make sure.
1334 * (pci_find_device doesn't work yet)
1335 *
1336 * We can also enable the sis96x bit in the discovery register..
1337 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001338#define SIS_DETECT_REGISTER 0x40
1339
Alan Cox1597cac2006-12-04 15:14:45 -08001340static void quirk_sis_503(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001341{
1342 u8 reg;
1343 u16 devid;
1344
1345 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1346 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1347 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1348 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1349 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1350 return;
1351 }
1352
Linus Torvalds1da177e2005-04-16 15:20:36 -07001353 /*
Mark M. Hoffman2f5c33b2007-01-08 22:11:29 -05001354 * Ok, it now shows up as a 96x.. run the 96x quirk by
1355 * hand in case it has already been processed.
1356 * (depends on link order, which is apparently not guaranteed)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001357 */
1358 dev->device = devid;
Mark M. Hoffman2f5c33b2007-01-08 22:11:29 -05001359 quirk_sis_96x_smbus(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001360}
Andrew Morton652c5382007-11-21 15:07:13 -08001361DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001362DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001363
Linus Torvalds1da177e2005-04-16 15:20:36 -07001364
Bauke Jan Doumae5548e92006-02-28 21:44:36 +01001365/*
1366 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1367 * and MC97 modem controller are disabled when a second PCI soundcard is
1368 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1369 * -- bjd
1370 */
Alan Cox1597cac2006-12-04 15:14:45 -08001371static void asus_hides_ac97_lpc(struct pci_dev *dev)
Bauke Jan Doumae5548e92006-02-28 21:44:36 +01001372{
1373 u8 val;
1374 int asus_hides_ac97 = 0;
1375
1376 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1377 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1378 asus_hides_ac97 = 1;
1379 }
1380
1381 if (!asus_hides_ac97)
1382 return;
1383
1384 pci_read_config_byte(dev, 0x50, &val);
1385 if (val & 0xc0) {
1386 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1387 pci_read_config_byte(dev, 0x50, &val);
1388 if (val & 0xc0)
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001389 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val);
Bauke Jan Doumae5548e92006-02-28 21:44:36 +01001390 else
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001391 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
Bauke Jan Doumae5548e92006-02-28 21:44:36 +01001392 }
1393}
Andrew Morton652c5382007-11-21 15:07:13 -08001394DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001395DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
Alan Cox1597cac2006-12-04 15:14:45 -08001396
Tejun Heo77967052006-08-19 03:54:39 +09001397#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
Alan Cox15e0c692006-07-12 15:05:41 +01001398
1399/*
1400 * If we are using libata we can drive this chip properly but must
1401 * do this early on to make the additional device appear during
1402 * the PCI scanning.
1403 */
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001404static void quirk_jmicron_ata(struct pci_dev *pdev)
Alan Cox15e0c692006-07-12 15:05:41 +01001405{
Tejun Heoe34bb372007-02-26 20:24:03 +09001406 u32 conf1, conf5, class;
Alan Cox15e0c692006-07-12 15:05:41 +01001407 u8 hdr;
1408
1409 /* Only poke fn 0 */
1410 if (PCI_FUNC(pdev->devfn))
1411 return;
1412
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001413 pci_read_config_dword(pdev, 0x40, &conf1);
1414 pci_read_config_dword(pdev, 0x80, &conf5);
Alan Cox15e0c692006-07-12 15:05:41 +01001415
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001416 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1417 conf5 &= ~(1 << 24); /* Clear bit 24 */
Alan Cox15e0c692006-07-12 15:05:41 +01001418
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001419 switch (pdev->device) {
1420 case PCI_DEVICE_ID_JMICRON_JMB360:
1421 /* The controller should be in single function ahci mode */
1422 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1423 break;
Alan Cox15e0c692006-07-12 15:05:41 +01001424
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001425 case PCI_DEVICE_ID_JMICRON_JMB365:
1426 case PCI_DEVICE_ID_JMICRON_JMB366:
1427 /* Redirect IDE second PATA port to the right spot */
1428 conf5 |= (1 << 24);
1429 /* Fall through */
1430 case PCI_DEVICE_ID_JMICRON_JMB361:
1431 case PCI_DEVICE_ID_JMICRON_JMB363:
1432 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1433 /* Set the class codes correctly and then direct IDE 0 */
Tejun Heo3a9e3a52007-10-23 15:27:31 +09001434 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001435 break;
1436
1437 case PCI_DEVICE_ID_JMICRON_JMB368:
1438 /* The controller should be in single function IDE mode */
1439 conf1 |= 0x00C00000; /* Set 22, 23 */
1440 break;
Alan Cox15e0c692006-07-12 15:05:41 +01001441 }
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001442
1443 pci_write_config_dword(pdev, 0x40, conf1);
1444 pci_write_config_dword(pdev, 0x80, conf5);
1445
1446 /* Update pdev accordingly */
1447 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1448 pdev->hdr_type = hdr & 0x7f;
1449 pdev->multifunction = !!(hdr & 0x80);
Tejun Heoe34bb372007-02-26 20:24:03 +09001450
1451 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1452 pdev->class = class >> 8;
Alan Cox15e0c692006-07-12 15:05:41 +01001453}
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001454DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1455DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1456DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1457DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1458DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1459DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001460DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1461DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1462DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1463DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1464DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1465DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
Alan Cox15e0c692006-07-12 15:05:41 +01001466
1467#endif
1468
Linus Torvalds1da177e2005-04-16 15:20:36 -07001469#ifdef CONFIG_X86_IO_APIC
1470static void __init quirk_alder_ioapic(struct pci_dev *pdev)
1471{
1472 int i;
1473
1474 if ((pdev->class >> 8) != 0xff00)
1475 return;
1476
1477 /* the first BAR is the location of the IO APIC...we must
1478 * not touch this (and it's already covered by the fixmap), so
1479 * forcibly insert it into the resource tree */
1480 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1481 insert_resource(&iomem_resource, &pdev->resource[0]);
1482
1483 /* The next five BARs all seem to be rubbish, so just clean
1484 * them out */
1485 for (i=1; i < 6; i++) {
1486 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1487 }
1488
1489}
Andrew Morton652c5382007-11-21 15:07:13 -08001490DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001491#endif
1492
Linus Torvalds1da177e2005-04-16 15:20:36 -07001493static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1494{
1495 pcie_mch_quirk = 1;
1496}
Andrew Morton652c5382007-11-21 15:07:13 -08001497DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1498DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1499DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001500
Kristen Accardi4602b882005-08-16 15:15:58 -07001501
1502/*
1503 * It's possible for the MSI to get corrupted if shpc and acpi
1504 * are used together on certain PXH-based systems.
1505 */
1506static void __devinit quirk_pcie_pxh(struct pci_dev *dev)
1507{
Eric W. Biedermanf5f2b132007-03-05 00:30:07 -08001508 pci_msi_off(dev);
Kristen Accardi4602b882005-08-16 15:15:58 -07001509 dev->no_msi = 1;
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001510 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
Kristen Accardi4602b882005-08-16 15:15:58 -07001511}
1512DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1513DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1514DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1515DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1516DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1517
Kristen Carlson Accardiffadcc22006-07-12 08:59:00 -07001518/*
1519 * Some Intel PCI Express chipsets have trouble with downstream
1520 * device power management.
1521 */
1522static void quirk_intel_pcie_pm(struct pci_dev * dev)
1523{
1524 pci_pm_d3_delay = 120;
1525 dev->no_d1d2 = 1;
1526}
1527
1528DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1529DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1530DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1531DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1532DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1533DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1534DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1535DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1536DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1537DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1538DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1539DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1540DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1541DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1542DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1543DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1544DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1545DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1546DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1547DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1548DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
Kristen Accardi4602b882005-08-16 15:15:58 -07001549
Stefan Assmann426b3b82008-06-11 16:35:16 +02001550#ifdef CONFIG_X86_IO_APIC
1551/*
Stefan Assmanne1d3a902008-06-11 16:35:17 +02001552 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1553 * remap the original interrupt in the linux kernel to the boot interrupt, so
1554 * that a PCI device's interrupt handler is installed on the boot interrupt
1555 * line instead.
1556 */
1557static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1558{
Stefan Assmann41b9eb22008-07-15 13:48:55 +02001559 if (noioapicquirk || noioapicreroute)
Stefan Assmanne1d3a902008-06-11 16:35:17 +02001560 return;
1561
1562 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
1563
1564 printk(KERN_INFO "PCI quirk: reroute interrupts for 0x%04x:0x%04x\n",
1565 dev->vendor, dev->device);
1566 return;
1567}
Olaf Dabrunz88d1dce2008-07-08 15:59:48 +02001568DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1569DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1570DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1571DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1572DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1573DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1574DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1575DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1576DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1577DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1578DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1579DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1580DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1581DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1582DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1583DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
Stefan Assmanne1d3a902008-06-11 16:35:17 +02001584
1585/*
Stefan Assmann426b3b82008-06-11 16:35:16 +02001586 * On some chipsets we can disable the generation of legacy INTx boot
1587 * interrupts.
1588 */
1589
1590/*
1591 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
1592 * 300641-004US, section 5.7.3.
1593 */
1594#define INTEL_6300_IOAPIC_ABAR 0x40
1595#define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1596
1597static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1598{
1599 u16 pci_config_word;
1600
1601 if (noioapicquirk)
1602 return;
1603
1604 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1605 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1606 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1607
1608 printk(KERN_INFO "disabled boot interrupt on device 0x%04x:0x%04x\n",
1609 dev->vendor, dev->device);
1610}
Olaf Dabrunz88d1dce2008-07-08 15:59:48 +02001611DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1612DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
Olaf Dabrunz77251182008-07-08 15:59:47 +02001613
1614/*
1615 * disable boot interrupts on HT-1000
1616 */
1617#define BC_HT1000_FEATURE_REG 0x64
1618#define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1619#define BC_HT1000_MAP_IDX 0xC00
1620#define BC_HT1000_MAP_DATA 0xC01
1621
1622static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1623{
1624 u32 pci_config_dword;
1625 u8 irq;
1626
1627 if (noioapicquirk)
1628 return;
1629
1630 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
1631 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
1632 BC_HT1000_PIC_REGS_ENABLE);
1633
1634 for (irq = 0x10; irq < 0x10 + 32; irq++) {
1635 outb(irq, BC_HT1000_MAP_IDX);
1636 outb(0x00, BC_HT1000_MAP_DATA);
1637 }
1638
1639 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1640
1641 printk(KERN_INFO "disabled boot interrupts on PCI device"
1642 "0x%04x:0x%04x\n", dev->vendor, dev->device);
1643}
Olaf Dabrunz88d1dce2008-07-08 15:59:48 +02001644DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1645DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
Olaf Dabrunz542622d2008-07-08 15:59:48 +02001646
1647/*
1648 * disable boot interrupts on AMD and ATI chipsets
1649 */
1650/*
1651 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1652 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
1653 * (due to an erratum).
1654 */
1655#define AMD_813X_MISC 0x40
1656#define AMD_813X_NOIOAMODE (1<<0)
Stefan Assmannbbe19442009-02-26 10:46:48 -08001657#define AMD_813X_REV_B2 0x13
Olaf Dabrunz542622d2008-07-08 15:59:48 +02001658
1659static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
1660{
1661 u32 pci_config_dword;
1662
1663 if (noioapicquirk)
1664 return;
Stefan Assmannbbe19442009-02-26 10:46:48 -08001665 if (dev->revision == AMD_813X_REV_B2)
1666 return;
Olaf Dabrunz542622d2008-07-08 15:59:48 +02001667
1668 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
1669 pci_config_dword &= ~AMD_813X_NOIOAMODE;
1670 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
1671
1672 printk(KERN_INFO "disabled boot interrupts on PCI device "
1673 "0x%04x:0x%04x\n", dev->vendor, dev->device);
1674}
Olaf Dabrunz88d1dce2008-07-08 15:59:48 +02001675DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1676DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
Olaf Dabrunz542622d2008-07-08 15:59:48 +02001677
1678#define AMD_8111_PCI_IRQ_ROUTING 0x56
1679
1680static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
1681{
1682 u16 pci_config_word;
1683
1684 if (noioapicquirk)
1685 return;
1686
1687 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
1688 if (!pci_config_word) {
1689 printk(KERN_INFO "boot interrupts on PCI device 0x%04x:0x%04x "
1690 "already disabled\n",
1691 dev->vendor, dev->device);
1692 return;
1693 }
1694 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
1695 printk(KERN_INFO "disabled boot interrupts on PCI device "
1696 "0x%04x:0x%04x\n", dev->vendor, dev->device);
1697}
Olaf Dabrunz88d1dce2008-07-08 15:59:48 +02001698DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1699DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
Stefan Assmann426b3b82008-06-11 16:35:16 +02001700#endif /* CONFIG_X86_IO_APIC */
1701
Sergei Shtylyov33dced22007-02-07 18:18:45 +01001702/*
1703 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1704 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1705 * Re-allocate the region if needed...
1706 */
1707static void __init quirk_tc86c001_ide(struct pci_dev *dev)
1708{
1709 struct resource *r = &dev->resource[0];
1710
1711 if (r->start & 0x8) {
1712 r->start = 0;
1713 r->end = 0xf;
1714 }
1715}
1716DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1717 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1718 quirk_tc86c001_ide);
1719
Linus Torvalds1da177e2005-04-16 15:20:36 -07001720static void __devinit quirk_netmos(struct pci_dev *dev)
1721{
1722 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1723 unsigned int num_serial = dev->subsystem_device & 0xf;
1724
1725 /*
1726 * These Netmos parts are multiport serial devices with optional
1727 * parallel ports. Even when parallel ports are present, they
1728 * are identified as class SERIAL, which means the serial driver
1729 * will claim them. To prevent this, mark them as class OTHER.
1730 * These combo devices should be claimed by parport_serial.
1731 *
1732 * The subdevice ID is of the form 0x00PS, where <P> is the number
1733 * of parallel ports and <S> is the number of serial ports.
1734 */
1735 switch (dev->device) {
Jiri Slaby4c9c1682008-12-08 16:19:14 +01001736 case PCI_DEVICE_ID_NETMOS_9835:
1737 /* Well, this rule doesn't hold for the following 9835 device */
1738 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
1739 dev->subsystem_device == 0x0299)
1740 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001741 case PCI_DEVICE_ID_NETMOS_9735:
1742 case PCI_DEVICE_ID_NETMOS_9745:
Linus Torvalds1da177e2005-04-16 15:20:36 -07001743 case PCI_DEVICE_ID_NETMOS_9845:
1744 case PCI_DEVICE_ID_NETMOS_9855:
1745 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL &&
1746 num_parallel) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001747 dev_info(&dev->dev, "Netmos %04x (%u parallel, "
Linus Torvalds1da177e2005-04-16 15:20:36 -07001748 "%u serial); changing class SERIAL to OTHER "
1749 "(use parport_serial)\n",
1750 dev->device, num_parallel, num_serial);
1751 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1752 (dev->class & 0xff);
1753 }
1754 }
1755}
1756DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos);
1757
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001758static void __devinit quirk_e100_interrupt(struct pci_dev *dev)
1759{
Ivan Kokshayskye64aecc2007-12-18 00:39:27 +03001760 u16 command, pmcsr;
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001761 u8 __iomem *csr;
1762 u8 cmd_hi;
Ivan Kokshayskye64aecc2007-12-18 00:39:27 +03001763 int pm;
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001764
1765 switch (dev->device) {
1766 /* PCI IDs taken from drivers/net/e100.c */
1767 case 0x1029:
1768 case 0x1030 ... 0x1034:
1769 case 0x1038 ... 0x103E:
1770 case 0x1050 ... 0x1057:
1771 case 0x1059:
1772 case 0x1064 ... 0x106B:
1773 case 0x1091 ... 0x1095:
1774 case 0x1209:
1775 case 0x1229:
1776 case 0x2449:
1777 case 0x2459:
1778 case 0x245D:
1779 case 0x27DC:
1780 break;
1781 default:
1782 return;
1783 }
1784
1785 /*
1786 * Some firmware hands off the e100 with interrupts enabled,
1787 * which can cause a flood of interrupts if packets are
1788 * received before the driver attaches to the device. So
1789 * disable all e100 interrupts here. The driver will
1790 * re-enable them when it's ready.
1791 */
1792 pci_read_config_word(dev, PCI_COMMAND, &command);
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001793
Benjamin Herrenschmidt1bef7dc2007-09-29 09:06:21 +10001794 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001795 return;
1796
Ivan Kokshayskye64aecc2007-12-18 00:39:27 +03001797 /*
1798 * Check that the device is in the D0 power state. If it's not,
1799 * there is no point to look any further.
1800 */
1801 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1802 if (pm) {
1803 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
1804 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
1805 return;
1806 }
1807
Benjamin Herrenschmidt1bef7dc2007-09-29 09:06:21 +10001808 /* Convert from PCI bus to resource space. */
1809 csr = ioremap(pci_resource_start(dev, 0), 8);
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001810 if (!csr) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001811 dev_warn(&dev->dev, "Can't map e100 registers\n");
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001812 return;
1813 }
1814
1815 cmd_hi = readb(csr + 3);
1816 if (cmd_hi == 0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001817 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; "
1818 "disabling\n");
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001819 writeb(1, csr + 3);
1820 }
1821
1822 iounmap(csr);
1823}
Marian Balakowicz4e68fc92007-07-03 11:03:18 +02001824DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt);
Ivan Kokshayskya5312e22005-11-01 01:43:56 +03001825
Alexander Duyck649426e2009-03-05 13:57:28 -05001826/*
1827 * The 82575 and 82598 may experience data corruption issues when transitioning
1828 * out of L0S. To prevent this we need to disable L0S on the pci-e link
1829 */
1830static void __devinit quirk_disable_aspm_l0s(struct pci_dev *dev)
1831{
1832 dev_info(&dev->dev, "Disabling L0s\n");
1833 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
1834}
1835DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
1836DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
1837DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
1838DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
1839DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
1840DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
1841DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
1842DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
1843DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
1844DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
1845DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
1846DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
1847DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
1848DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
1849
Ivan Kokshayskya5312e22005-11-01 01:43:56 +03001850static void __devinit fixup_rev1_53c810(struct pci_dev* dev)
1851{
1852 /* rev 1 ncr53c810 chips don't set the class at all which means
1853 * they don't get their resources remapped. Fix that here.
1854 */
1855
1856 if (dev->class == PCI_CLASS_NOT_DEFINED) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001857 dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n");
Ivan Kokshayskya5312e22005-11-01 01:43:56 +03001858 dev->class = PCI_CLASS_STORAGE_SCSI;
1859 }
1860}
1861DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
1862
Daniel Yeisley9d265122005-12-05 07:06:43 -05001863/* Enable 1k I/O space granularity on the Intel P64H2 */
1864static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev)
1865{
1866 u16 en1k;
1867 u8 io_base_lo, io_limit_lo;
1868 unsigned long base, limit;
1869 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1870
1871 pci_read_config_word(dev, 0x40, &en1k);
1872
1873 if (en1k & 0x200) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001874 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
Daniel Yeisley9d265122005-12-05 07:06:43 -05001875
1876 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
1877 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
1878 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1879 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1880
1881 if (base <= limit) {
1882 res->start = base;
1883 res->end = limit + 0x3ff;
1884 }
1885 }
1886}
1887DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
1888
Daniel Yeisley15a260d2006-12-21 14:34:57 -05001889/* Fix the IOBL_ADR for 1k I/O space granularity on the Intel P64H2
1890 * The IOBL_ADR gets re-written to 4k boundaries in pci_setup_bridge()
1891 * in drivers/pci/setup-bus.c
1892 */
1893static void __devinit quirk_p64h2_1k_io_fix_iobl(struct pci_dev *dev)
1894{
1895 u16 en1k, iobl_adr, iobl_adr_1k;
1896 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1897
1898 pci_read_config_word(dev, 0x40, &en1k);
1899
1900 if (en1k & 0x200) {
1901 pci_read_config_word(dev, PCI_IO_BASE, &iobl_adr);
1902
1903 iobl_adr_1k = iobl_adr | (res->start >> 8) | (res->end & 0xfc00);
1904
1905 if (iobl_adr != iobl_adr_1k) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001906 dev_info(&dev->dev, "Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1KB granularity\n",
Daniel Yeisley15a260d2006-12-21 14:34:57 -05001907 iobl_adr,iobl_adr_1k);
1908 pci_write_config_word(dev, PCI_IO_BASE, iobl_adr_1k);
1909 }
1910 }
1911}
1912DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io_fix_iobl);
1913
Brice Goglincf34a8e2006-06-13 14:35:42 -04001914/* Under some circumstances, AER is not linked with extended capabilities.
1915 * Force it to be linked by setting the corresponding control bit in the
1916 * config space.
1917 */
Alan Cox1597cac2006-12-04 15:14:45 -08001918static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
Brice Goglincf34a8e2006-06-13 14:35:42 -04001919{
1920 uint8_t b;
1921 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
1922 if (!(b & 0x20)) {
1923 pci_write_config_byte(dev, 0xf41, b | 0x20);
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001924 dev_info(&dev->dev,
1925 "Linking AER extended capability\n");
Brice Goglincf34a8e2006-06-13 14:35:42 -04001926 }
1927 }
1928}
1929DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1930 quirk_nvidia_ck804_pcie_aer_ext_cap);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001931DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
Alan Cox1597cac2006-12-04 15:14:45 -08001932 quirk_nvidia_ck804_pcie_aer_ext_cap);
Brice Goglincf34a8e2006-06-13 14:35:42 -04001933
Tim Yamin53a9bf42007-11-01 23:14:54 +00001934static void __devinit quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
1935{
1936 /*
1937 * Disable PCI Bus Parking and PCI Master read caching on CX700
1938 * which causes unspecified timing errors with a VT6212L on the PCI
1939 * bus leading to USB2.0 packet loss. The defaults are that these
1940 * features are turned off but some BIOSes turn them on.
1941 */
1942
1943 uint8_t b;
1944 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
1945 if (b & 0x40) {
1946 /* Turn off PCI Bus Parking */
1947 pci_write_config_byte(dev, 0x76, b ^ 0x40);
1948
Tim Yaminbc043272008-03-30 20:58:59 +01001949 dev_info(&dev->dev,
1950 "Disabling VIA CX700 PCI parking\n");
1951 }
1952 }
1953
1954 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
1955 if (b != 0) {
Tim Yamin53a9bf42007-11-01 23:14:54 +00001956 /* Turn off PCI Master read caching */
1957 pci_write_config_byte(dev, 0x72, 0x0);
Tim Yaminbc043272008-03-30 20:58:59 +01001958
1959 /* Set PCI Master Bus time-out to "1x16 PCLK" */
Tim Yamin53a9bf42007-11-01 23:14:54 +00001960 pci_write_config_byte(dev, 0x75, 0x1);
Tim Yaminbc043272008-03-30 20:58:59 +01001961
1962 /* Disable "Read FIFO Timer" */
Tim Yamin53a9bf42007-11-01 23:14:54 +00001963 pci_write_config_byte(dev, 0x77, 0x0);
1964
Bjorn Helgaasd6505a52008-02-29 16:12:18 -07001965 dev_info(&dev->dev,
Tim Yaminbc043272008-03-30 20:58:59 +01001966 "Disabling VIA CX700 PCI caching\n");
Tim Yamin53a9bf42007-11-01 23:14:54 +00001967 }
1968 }
1969}
1970DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
1971
Benjamin Li99cb233d2008-07-02 10:59:04 -07001972/*
1973 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
1974 * VPD end tag will hang the device. This problem was initially
1975 * observed when a vpd entry was created in sysfs
1976 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry
1977 * will dump 32k of data. Reading a full 32k will cause an access
1978 * beyond the VPD end tag causing the device to hang. Once the device
1979 * is hung, the bnx2 driver will not be able to reset the device.
1980 * We believe that it is legal to read beyond the end tag and
1981 * therefore the solution is to limit the read/write length.
1982 */
1983static void __devinit quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
1984{
Eric Dumazet9d82d8e2008-07-31 20:27:31 +02001985 /*
Dean Hildebrand35405f22008-08-07 17:31:45 -07001986 * Only disable the VPD capability for 5706, 5706S, 5708,
1987 * 5708S and 5709 rev. A
Eric Dumazet9d82d8e2008-07-31 20:27:31 +02001988 */
Benjamin Li99cb233d2008-07-02 10:59:04 -07001989 if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
Dean Hildebrand35405f22008-08-07 17:31:45 -07001990 (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
Benjamin Li99cb233d2008-07-02 10:59:04 -07001991 (dev->device == PCI_DEVICE_ID_NX2_5708) ||
Eric Dumazet9d82d8e2008-07-31 20:27:31 +02001992 (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
Benjamin Li99cb233d2008-07-02 10:59:04 -07001993 ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
1994 (dev->revision & 0xf0) == 0x0)) {
1995 if (dev->vpd)
1996 dev->vpd->len = 0x80;
1997 }
1998}
1999
Yu Zhaobffadff2008-10-28 14:44:11 +08002000DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2001 PCI_DEVICE_ID_NX2_5706,
2002 quirk_brcm_570x_limit_vpd);
2003DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2004 PCI_DEVICE_ID_NX2_5706S,
2005 quirk_brcm_570x_limit_vpd);
2006DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2007 PCI_DEVICE_ID_NX2_5708,
2008 quirk_brcm_570x_limit_vpd);
2009DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2010 PCI_DEVICE_ID_NX2_5708S,
2011 quirk_brcm_570x_limit_vpd);
2012DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2013 PCI_DEVICE_ID_NX2_5709,
2014 quirk_brcm_570x_limit_vpd);
2015DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2016 PCI_DEVICE_ID_NX2_5709S,
2017 quirk_brcm_570x_limit_vpd);
Benjamin Li99cb233d2008-07-02 10:59:04 -07002018
Brice Goglin3f79e102006-08-31 01:54:56 -04002019#ifdef CONFIG_PCI_MSI
Tejun Heoebdf7d32007-05-31 00:40:48 -07002020/* Some chipsets do not support MSI. We cannot easily rely on setting
2021 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
2022 * some other busses controlled by the chipset even if Linux is not
2023 * aware of it. Instead of setting the flag on all busses in the
2024 * machine, simply disable MSI globally.
Brice Goglin3f79e102006-08-31 01:54:56 -04002025 */
Tejun Heoebdf7d32007-05-31 00:40:48 -07002026static void __init quirk_disable_all_msi(struct pci_dev *dev)
Brice Goglin3f79e102006-08-31 01:54:56 -04002027{
Michael Ellerman88187df2007-01-25 19:34:07 +11002028 pci_no_msi();
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07002029 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
Brice Goglin3f79e102006-08-31 01:54:56 -04002030}
Tejun Heoebdf7d32007-05-31 00:40:48 -07002031DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2032DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2033DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
Tejun Heo66d715c2008-07-04 09:59:32 -07002034DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
Jay Cliburn184b8122007-05-26 17:01:04 -05002035DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
Thomas Renninger162dedd2009-04-03 06:34:00 -07002036DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
Brice Goglin3f79e102006-08-31 01:54:56 -04002037
2038/* Disable MSI on chipsets that are known to not support it */
2039static void __devinit quirk_disable_msi(struct pci_dev *dev)
2040{
2041 if (dev->subordinate) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07002042 dev_warn(&dev->dev, "MSI quirk detected; "
2043 "subordinate MSI disabled\n");
Brice Goglin3f79e102006-08-31 01:54:56 -04002044 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2045 }
2046}
2047DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
Brice Goglin6397c752006-08-31 01:55:32 -04002048
2049/* Go through the list of Hypertransport capabilities and
2050 * return 1 if a HT MSI capability is found and enabled */
2051static int __devinit msi_ht_cap_enabled(struct pci_dev *dev)
2052{
Michael Ellerman7a380502006-11-22 18:26:21 +11002053 int pos, ttl = 48;
2054
2055 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2056 while (pos && ttl--) {
2057 u8 flags;
2058
2059 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2060 &flags) == 0)
2061 {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07002062 dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
Michael Ellerman7a380502006-11-22 18:26:21 +11002063 flags & HT_MSI_FLAGS_ENABLE ?
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07002064 "enabled" : "disabled");
Michael Ellerman7a380502006-11-22 18:26:21 +11002065 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
Brice Goglin6397c752006-08-31 01:55:32 -04002066 }
Michael Ellerman7a380502006-11-22 18:26:21 +11002067
2068 pos = pci_find_next_ht_capability(dev, pos,
2069 HT_CAPTYPE_MSI_MAPPING);
Brice Goglin6397c752006-08-31 01:55:32 -04002070 }
2071 return 0;
2072}
2073
2074/* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
2075static void __devinit quirk_msi_ht_cap(struct pci_dev *dev)
2076{
2077 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07002078 dev_warn(&dev->dev, "MSI quirk detected; "
2079 "subordinate MSI disabled\n");
Brice Goglin6397c752006-08-31 01:55:32 -04002080 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2081 }
2082}
2083DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2084 quirk_msi_ht_cap);
Sebastien Dugue6bae1d92007-12-13 16:09:25 -08002085
Brice Goglin6397c752006-08-31 01:55:32 -04002086/* The nVidia CK804 chipset may have 2 HT MSI mappings.
2087 * MSI are supported if the MSI capability set in any of these mappings.
2088 */
2089static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2090{
2091 struct pci_dev *pdev;
2092
2093 if (!dev->subordinate)
2094 return;
2095
2096 /* check HT MSI cap on this chipset and the root one.
2097 * a single one having MSI is enough to be sure that MSI are supported.
2098 */
Alan Cox11f242f2006-10-10 14:39:00 -07002099 pdev = pci_get_slot(dev->bus, 0);
Jesper Juhl9ac0ce82006-12-04 15:14:48 -08002100 if (!pdev)
2101 return;
David Rientjes0c875c22006-12-03 11:55:34 -08002102 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07002103 dev_warn(&dev->dev, "MSI quirk detected; "
2104 "subordinate MSI disabled\n");
Brice Goglin6397c752006-08-31 01:55:32 -04002105 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2106 }
Alan Cox11f242f2006-10-10 14:39:00 -07002107 pci_dev_put(pdev);
Brice Goglin6397c752006-08-31 01:55:32 -04002108}
2109DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2110 quirk_nvidia_ck804_msi_ht_cap);
David Millerba698ad2007-10-25 01:16:30 -07002111
Bjorn Helgaas415b6d02008-02-29 16:04:39 -07002112/* Force enable MSI mapping capability on HT bridges */
2113static void __devinit ht_enable_msi_mapping(struct pci_dev *dev)
Peer Chen9dc625e2008-02-04 23:50:13 -08002114{
2115 int pos, ttl = 48;
2116
2117 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2118 while (pos && ttl--) {
2119 u8 flags;
2120
2121 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2122 &flags) == 0) {
2123 dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
2124
2125 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2126 flags | HT_MSI_FLAGS_ENABLE);
2127 }
2128 pos = pci_find_next_ht_capability(dev, pos,
2129 HT_CAPTYPE_MSI_MAPPING);
2130 }
2131}
Bjorn Helgaas415b6d02008-02-29 16:04:39 -07002132DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2133 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2134 ht_enable_msi_mapping);
Peer Chen9dc625e2008-02-04 23:50:13 -08002135
Yinghai Lue0ae4f52009-02-17 20:40:09 -08002136DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2137 ht_enable_msi_mapping);
2138
Andreas Petlund75e07fc2008-11-20 20:42:25 -08002139/* The P5N32-SLI Premium motherboard from Asus has a problem with msi
2140 * for the MCP55 NIC. It is not yet determined whether the msi problem
2141 * also affects other devices. As for now, turn off msi for this device.
2142 */
2143static void __devinit nvenet_msi_disable(struct pci_dev *dev)
2144{
2145 if (dmi_name_in_vendors("P5N32-SLI PREMIUM")) {
2146 dev_info(&dev->dev,
2147 "Disabling msi for MCP55 NIC on P5N32-SLI Premium\n");
2148 dev->no_msi = 1;
2149 }
2150}
2151DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2152 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2153 nvenet_msi_disable);
2154
Yinghai Lude745302009-03-20 19:29:41 -07002155static int __devinit ht_check_msi_mapping(struct pci_dev *dev)
2156{
2157 int pos, ttl = 48;
2158 int found = 0;
2159
2160 /* check if there is HT MSI cap or enabled on this device */
2161 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2162 while (pos && ttl--) {
2163 u8 flags;
2164
2165 if (found < 1)
2166 found = 1;
2167 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2168 &flags) == 0) {
2169 if (flags & HT_MSI_FLAGS_ENABLE) {
2170 if (found < 2) {
2171 found = 2;
2172 break;
2173 }
2174 }
2175 }
2176 pos = pci_find_next_ht_capability(dev, pos,
2177 HT_CAPTYPE_MSI_MAPPING);
2178 }
2179
2180 return found;
2181}
2182
2183static int __devinit host_bridge_with_leaf(struct pci_dev *host_bridge)
2184{
2185 struct pci_dev *dev;
2186 int pos;
2187 int i, dev_no;
2188 int found = 0;
2189
2190 dev_no = host_bridge->devfn >> 3;
2191 for (i = dev_no + 1; i < 0x20; i++) {
2192 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2193 if (!dev)
2194 continue;
2195
2196 /* found next host bridge ?*/
2197 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2198 if (pos != 0) {
2199 pci_dev_put(dev);
2200 break;
2201 }
2202
2203 if (ht_check_msi_mapping(dev)) {
2204 found = 1;
2205 pci_dev_put(dev);
2206 break;
2207 }
2208 pci_dev_put(dev);
2209 }
2210
2211 return found;
2212}
2213
Yinghai Lueeafda72009-03-29 12:30:05 -07002214#define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2215#define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2216
2217static int __devinit is_end_of_ht_chain(struct pci_dev *dev)
2218{
2219 int pos, ctrl_off;
2220 int end = 0;
2221 u16 flags, ctrl;
2222
2223 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2224
2225 if (!pos)
2226 goto out;
2227
2228 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2229
2230 ctrl_off = ((flags >> 10) & 1) ?
2231 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2232 pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2233
2234 if (ctrl & (1 << 6))
2235 end = 1;
2236
2237out:
2238 return end;
2239}
2240
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002241static void __devinit nv_ht_enable_msi_mapping(struct pci_dev *dev)
2242{
2243 struct pci_dev *host_bridge;
2244 int pos;
2245 int i, dev_no;
2246 int found = 0;
2247
2248 dev_no = dev->devfn >> 3;
2249 for (i = dev_no; i >= 0; i--) {
2250 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2251 if (!host_bridge)
2252 continue;
2253
2254 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2255 if (pos != 0) {
2256 found = 1;
2257 break;
2258 }
2259 pci_dev_put(host_bridge);
2260 }
2261
2262 if (!found)
2263 return;
2264
Yinghai Lueeafda72009-03-29 12:30:05 -07002265 /* don't enable end_device/host_bridge with leaf directly here */
2266 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2267 host_bridge_with_leaf(host_bridge))
Yinghai Lude745302009-03-20 19:29:41 -07002268 goto out;
2269
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002270 /* root did that ! */
2271 if (msi_ht_cap_enabled(host_bridge))
2272 goto out;
2273
2274 ht_enable_msi_mapping(dev);
2275
2276out:
2277 pci_dev_put(host_bridge);
2278}
2279
2280static void __devinit ht_disable_msi_mapping(struct pci_dev *dev)
2281{
2282 int pos, ttl = 48;
2283
2284 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2285 while (pos && ttl--) {
2286 u8 flags;
2287
2288 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2289 &flags) == 0) {
Prakash Punnoor6a958d52009-03-06 10:10:35 +01002290 dev_info(&dev->dev, "Disabling HT MSI Mapping\n");
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002291
2292 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2293 flags & ~HT_MSI_FLAGS_ENABLE);
2294 }
2295 pos = pci_find_next_ht_capability(dev, pos,
2296 HT_CAPTYPE_MSI_MAPPING);
2297 }
2298}
2299
Yinghai Lude745302009-03-20 19:29:41 -07002300static void __devinit __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
Peer Chen9dc625e2008-02-04 23:50:13 -08002301{
2302 struct pci_dev *host_bridge;
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002303 int pos;
2304 int found;
2305
2306 /* check if there is HT MSI cap or enabled on this device */
2307 found = ht_check_msi_mapping(dev);
2308
2309 /* no HT MSI CAP */
2310 if (found == 0)
2311 return;
Peer Chen9dc625e2008-02-04 23:50:13 -08002312
2313 /*
2314 * HT MSI mapping should be disabled on devices that are below
2315 * a non-Hypertransport host bridge. Locate the host bridge...
2316 */
2317 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
2318 if (host_bridge == NULL) {
2319 dev_warn(&dev->dev,
2320 "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2321 return;
2322 }
2323
2324 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2325 if (pos != 0) {
2326 /* Host bridge is to HT */
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002327 if (found == 1) {
2328 /* it is not enabled, try to enable it */
Yinghai Lude745302009-03-20 19:29:41 -07002329 if (all)
2330 ht_enable_msi_mapping(dev);
2331 else
2332 nv_ht_enable_msi_mapping(dev);
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002333 }
Peer Chen9dc625e2008-02-04 23:50:13 -08002334 return;
2335 }
2336
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002337 /* HT MSI is not enabled */
2338 if (found == 1)
2339 return;
Peer Chen9dc625e2008-02-04 23:50:13 -08002340
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002341 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2342 ht_disable_msi_mapping(dev);
Peer Chen9dc625e2008-02-04 23:50:13 -08002343}
Yinghai Lude745302009-03-20 19:29:41 -07002344
2345static void __devinit nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2346{
2347 return __nv_msi_ht_cap_quirk(dev, 1);
2348}
2349
2350static void __devinit nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2351{
2352 return __nv_msi_ht_cap_quirk(dev, 0);
2353}
2354
2355DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2356
2357DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
Peer Chen9dc625e2008-02-04 23:50:13 -08002358
David Millerba698ad2007-10-25 01:16:30 -07002359static void __devinit quirk_msi_intx_disable_bug(struct pci_dev *dev)
2360{
2361 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2362}
Shane Huang4600c9d2008-01-25 15:46:24 +09002363static void __devinit quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2364{
2365 struct pci_dev *p;
2366
2367 /* SB700 MSI issue will be fixed at HW level from revision A21,
2368 * we need check PCI REVISION ID of SMBus controller to get SB700
2369 * revision.
2370 */
2371 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2372 NULL);
2373 if (!p)
2374 return;
2375
2376 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2377 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2378 pci_dev_put(p);
2379}
David Millerba698ad2007-10-25 01:16:30 -07002380DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2381 PCI_DEVICE_ID_TIGON3_5780,
2382 quirk_msi_intx_disable_bug);
2383DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2384 PCI_DEVICE_ID_TIGON3_5780S,
2385 quirk_msi_intx_disable_bug);
2386DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2387 PCI_DEVICE_ID_TIGON3_5714,
2388 quirk_msi_intx_disable_bug);
2389DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2390 PCI_DEVICE_ID_TIGON3_5714S,
2391 quirk_msi_intx_disable_bug);
2392DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2393 PCI_DEVICE_ID_TIGON3_5715,
2394 quirk_msi_intx_disable_bug);
2395DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2396 PCI_DEVICE_ID_TIGON3_5715S,
2397 quirk_msi_intx_disable_bug);
2398
David Millerbc38b412007-10-25 01:16:52 -07002399DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
Shane Huang4600c9d2008-01-25 15:46:24 +09002400 quirk_msi_intx_disable_ati_bug);
David Millerbc38b412007-10-25 01:16:52 -07002401DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
Shane Huang4600c9d2008-01-25 15:46:24 +09002402 quirk_msi_intx_disable_ati_bug);
David Millerbc38b412007-10-25 01:16:52 -07002403DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
Shane Huang4600c9d2008-01-25 15:46:24 +09002404 quirk_msi_intx_disable_ati_bug);
David Millerbc38b412007-10-25 01:16:52 -07002405DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
Shane Huang4600c9d2008-01-25 15:46:24 +09002406 quirk_msi_intx_disable_ati_bug);
David Millerbc38b412007-10-25 01:16:52 -07002407DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
Shane Huang4600c9d2008-01-25 15:46:24 +09002408 quirk_msi_intx_disable_ati_bug);
David Millerbc38b412007-10-25 01:16:52 -07002409
2410DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2411 quirk_msi_intx_disable_bug);
2412DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2413 quirk_msi_intx_disable_bug);
2414DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2415 quirk_msi_intx_disable_bug);
2416
Brice Goglin3f79e102006-08-31 01:54:56 -04002417#endif /* CONFIG_PCI_MSI */
Thomas Petazzoni3d137312008-08-19 10:28:24 +02002418
Yu Zhao7eb93b12009-04-03 15:18:11 +08002419#ifdef CONFIG_PCI_IOV
2420
2421/*
2422 * For Intel 82576 SR-IOV NIC, if BIOS doesn't allocate resources for the
2423 * SR-IOV BARs, zero the Flash BAR and program the SR-IOV BARs to use the
2424 * old Flash Memory Space.
2425 */
2426static void __devinit quirk_i82576_sriov(struct pci_dev *dev)
2427{
2428 int pos, flags;
2429 u32 bar, start, size;
2430
2431 if (PAGE_SIZE > 0x10000)
2432 return;
2433
2434 flags = pci_resource_flags(dev, 0);
2435 if ((flags & PCI_BASE_ADDRESS_SPACE) !=
2436 PCI_BASE_ADDRESS_SPACE_MEMORY ||
2437 (flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK) !=
2438 PCI_BASE_ADDRESS_MEM_TYPE_32)
2439 return;
2440
2441 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV);
2442 if (!pos)
2443 return;
2444
2445 pci_read_config_dword(dev, pos + PCI_SRIOV_BAR, &bar);
2446 if (bar & PCI_BASE_ADDRESS_MEM_MASK)
2447 return;
2448
2449 start = pci_resource_start(dev, 1);
2450 size = pci_resource_len(dev, 1);
2451 if (!start || size != 0x400000 || start & (size - 1))
2452 return;
2453
2454 pci_resource_flags(dev, 1) = 0;
2455 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0);
2456 pci_write_config_dword(dev, pos + PCI_SRIOV_BAR, start);
2457 pci_write_config_dword(dev, pos + PCI_SRIOV_BAR + 12, start + size / 2);
2458
2459 dev_info(&dev->dev, "use Flash Memory Space for SR-IOV BARs\n");
2460}
2461DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10c9, quirk_i82576_sriov);
2462DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e6, quirk_i82576_sriov);
2463DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e7, quirk_i82576_sriov);
2464
2465#endif /* CONFIG_PCI_IOV */
2466
Jesse Barnesbfb0f332008-10-27 17:50:21 -07002467static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
2468 struct pci_fixup *end)
Thomas Petazzoni3d137312008-08-19 10:28:24 +02002469{
2470 while (f < end) {
2471 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
Jesse Barnesbfb0f332008-10-27 17:50:21 -07002472 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
Yinghai Luc9bbb4a2008-09-24 19:04:33 -07002473 dev_dbg(&dev->dev, "calling %pF\n", f->hook);
Thomas Petazzoni3d137312008-08-19 10:28:24 +02002474 f->hook(dev);
2475 }
2476 f++;
2477 }
2478}
2479
2480extern struct pci_fixup __start_pci_fixups_early[];
2481extern struct pci_fixup __end_pci_fixups_early[];
2482extern struct pci_fixup __start_pci_fixups_header[];
2483extern struct pci_fixup __end_pci_fixups_header[];
2484extern struct pci_fixup __start_pci_fixups_final[];
2485extern struct pci_fixup __end_pci_fixups_final[];
2486extern struct pci_fixup __start_pci_fixups_enable[];
2487extern struct pci_fixup __end_pci_fixups_enable[];
2488extern struct pci_fixup __start_pci_fixups_resume[];
2489extern struct pci_fixup __end_pci_fixups_resume[];
2490extern struct pci_fixup __start_pci_fixups_resume_early[];
2491extern struct pci_fixup __end_pci_fixups_resume_early[];
2492extern struct pci_fixup __start_pci_fixups_suspend[];
2493extern struct pci_fixup __end_pci_fixups_suspend[];
2494
2495
2496void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
2497{
2498 struct pci_fixup *start, *end;
2499
2500 switch(pass) {
2501 case pci_fixup_early:
2502 start = __start_pci_fixups_early;
2503 end = __end_pci_fixups_early;
2504 break;
2505
2506 case pci_fixup_header:
2507 start = __start_pci_fixups_header;
2508 end = __end_pci_fixups_header;
2509 break;
2510
2511 case pci_fixup_final:
2512 start = __start_pci_fixups_final;
2513 end = __end_pci_fixups_final;
2514 break;
2515
2516 case pci_fixup_enable:
2517 start = __start_pci_fixups_enable;
2518 end = __end_pci_fixups_enable;
2519 break;
2520
2521 case pci_fixup_resume:
2522 start = __start_pci_fixups_resume;
2523 end = __end_pci_fixups_resume;
2524 break;
2525
2526 case pci_fixup_resume_early:
2527 start = __start_pci_fixups_resume_early;
2528 end = __end_pci_fixups_resume_early;
2529 break;
2530
2531 case pci_fixup_suspend:
2532 start = __start_pci_fixups_suspend;
2533 end = __end_pci_fixups_suspend;
2534 break;
2535
2536 default:
2537 /* stupid compiler warning, you would think with an enum... */
2538 return;
2539 }
2540 pci_do_fixups(dev, start, end);
2541}
2542#else
2543void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) {}
2544#endif
2545EXPORT_SYMBOL(pci_fixup_device);