Michael Hennerich | 9d2e173 | 2011-05-19 00:59:32 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Analog Devices ADP5589 I/O Expander and QWERTY Keypad Controller |
| 3 | * |
| 4 | * Copyright 2010-2011 Analog Devices Inc. |
| 5 | * |
| 6 | * Licensed under the GPL-2. |
| 7 | */ |
| 8 | |
| 9 | #ifndef _ADP5589_H |
| 10 | #define _ADP5589_H |
| 11 | |
| 12 | #define ADP5589_ID 0x00 |
| 13 | #define ADP5589_INT_STATUS 0x01 |
| 14 | #define ADP5589_STATUS 0x02 |
| 15 | #define ADP5589_FIFO_1 0x03 |
| 16 | #define ADP5589_FIFO_2 0x04 |
| 17 | #define ADP5589_FIFO_3 0x05 |
| 18 | #define ADP5589_FIFO_4 0x06 |
| 19 | #define ADP5589_FIFO_5 0x07 |
| 20 | #define ADP5589_FIFO_6 0x08 |
| 21 | #define ADP5589_FIFO_7 0x09 |
| 22 | #define ADP5589_FIFO_8 0x0A |
| 23 | #define ADP5589_FIFO_9 0x0B |
| 24 | #define ADP5589_FIFO_10 0x0C |
| 25 | #define ADP5589_FIFO_11 0x0D |
| 26 | #define ADP5589_FIFO_12 0x0E |
| 27 | #define ADP5589_FIFO_13 0x0F |
| 28 | #define ADP5589_FIFO_14 0x10 |
| 29 | #define ADP5589_FIFO_15 0x11 |
| 30 | #define ADP5589_FIFO_16 0x12 |
| 31 | #define ADP5589_GPI_INT_STAT_A 0x13 |
| 32 | #define ADP5589_GPI_INT_STAT_B 0x14 |
| 33 | #define ADP5589_GPI_INT_STAT_C 0x15 |
| 34 | #define ADP5589_GPI_STATUS_A 0x16 |
| 35 | #define ADP5589_GPI_STATUS_B 0x17 |
| 36 | #define ADP5589_GPI_STATUS_C 0x18 |
| 37 | #define ADP5589_RPULL_CONFIG_A 0x19 |
| 38 | #define ADP5589_RPULL_CONFIG_B 0x1A |
| 39 | #define ADP5589_RPULL_CONFIG_C 0x1B |
| 40 | #define ADP5589_RPULL_CONFIG_D 0x1C |
| 41 | #define ADP5589_RPULL_CONFIG_E 0x1D |
| 42 | #define ADP5589_GPI_INT_LEVEL_A 0x1E |
| 43 | #define ADP5589_GPI_INT_LEVEL_B 0x1F |
| 44 | #define ADP5589_GPI_INT_LEVEL_C 0x20 |
| 45 | #define ADP5589_GPI_EVENT_EN_A 0x21 |
| 46 | #define ADP5589_GPI_EVENT_EN_B 0x22 |
| 47 | #define ADP5589_GPI_EVENT_EN_C 0x23 |
| 48 | #define ADP5589_GPI_INTERRUPT_EN_A 0x24 |
| 49 | #define ADP5589_GPI_INTERRUPT_EN_B 0x25 |
| 50 | #define ADP5589_GPI_INTERRUPT_EN_C 0x26 |
| 51 | #define ADP5589_DEBOUNCE_DIS_A 0x27 |
| 52 | #define ADP5589_DEBOUNCE_DIS_B 0x28 |
| 53 | #define ADP5589_DEBOUNCE_DIS_C 0x29 |
| 54 | #define ADP5589_GPO_DATA_OUT_A 0x2A |
| 55 | #define ADP5589_GPO_DATA_OUT_B 0x2B |
| 56 | #define ADP5589_GPO_DATA_OUT_C 0x2C |
| 57 | #define ADP5589_GPO_OUT_MODE_A 0x2D |
| 58 | #define ADP5589_GPO_OUT_MODE_B 0x2E |
| 59 | #define ADP5589_GPO_OUT_MODE_C 0x2F |
| 60 | #define ADP5589_GPIO_DIRECTION_A 0x30 |
| 61 | #define ADP5589_GPIO_DIRECTION_B 0x31 |
| 62 | #define ADP5589_GPIO_DIRECTION_C 0x32 |
| 63 | #define ADP5589_UNLOCK1 0x33 |
| 64 | #define ADP5589_UNLOCK2 0x34 |
| 65 | #define ADP5589_EXT_LOCK_EVENT 0x35 |
| 66 | #define ADP5589_UNLOCK_TIMERS 0x36 |
| 67 | #define ADP5589_LOCK_CFG 0x37 |
| 68 | #define ADP5589_RESET1_EVENT_A 0x38 |
| 69 | #define ADP5589_RESET1_EVENT_B 0x39 |
| 70 | #define ADP5589_RESET1_EVENT_C 0x3A |
| 71 | #define ADP5589_RESET2_EVENT_A 0x3B |
| 72 | #define ADP5589_RESET2_EVENT_B 0x3C |
| 73 | #define ADP5589_RESET_CFG 0x3D |
| 74 | #define ADP5589_PWM_OFFT_LOW 0x3E |
| 75 | #define ADP5589_PWM_OFFT_HIGH 0x3F |
| 76 | #define ADP5589_PWM_ONT_LOW 0x40 |
| 77 | #define ADP5589_PWM_ONT_HIGH 0x41 |
| 78 | #define ADP5589_PWM_CFG 0x42 |
| 79 | #define ADP5589_CLOCK_DIV_CFG 0x43 |
| 80 | #define ADP5589_LOGIC_1_CFG 0x44 |
| 81 | #define ADP5589_LOGIC_2_CFG 0x45 |
| 82 | #define ADP5589_LOGIC_FF_CFG 0x46 |
| 83 | #define ADP5589_LOGIC_INT_EVENT_EN 0x47 |
| 84 | #define ADP5589_POLL_PTIME_CFG 0x48 |
| 85 | #define ADP5589_PIN_CONFIG_A 0x49 |
| 86 | #define ADP5589_PIN_CONFIG_B 0x4A |
| 87 | #define ADP5589_PIN_CONFIG_C 0x4B |
| 88 | #define ADP5589_PIN_CONFIG_D 0x4C |
| 89 | #define ADP5589_GENERAL_CFG 0x4D |
| 90 | #define ADP5589_INT_EN 0x4E |
| 91 | |
| 92 | #define ADP5589_DEVICE_ID_MASK 0xF |
| 93 | |
| 94 | /* Put one of these structures in i2c_board_info platform_data */ |
| 95 | |
| 96 | #define ADP5589_KEYMAPSIZE 88 |
| 97 | |
| 98 | #define ADP5589_GPI_PIN_ROW0 97 |
| 99 | #define ADP5589_GPI_PIN_ROW1 98 |
| 100 | #define ADP5589_GPI_PIN_ROW2 99 |
| 101 | #define ADP5589_GPI_PIN_ROW3 100 |
| 102 | #define ADP5589_GPI_PIN_ROW4 101 |
| 103 | #define ADP5589_GPI_PIN_ROW5 102 |
| 104 | #define ADP5589_GPI_PIN_ROW6 103 |
| 105 | #define ADP5589_GPI_PIN_ROW7 104 |
| 106 | #define ADP5589_GPI_PIN_COL0 105 |
| 107 | #define ADP5589_GPI_PIN_COL1 106 |
| 108 | #define ADP5589_GPI_PIN_COL2 107 |
| 109 | #define ADP5589_GPI_PIN_COL3 108 |
| 110 | #define ADP5589_GPI_PIN_COL4 109 |
| 111 | #define ADP5589_GPI_PIN_COL5 110 |
| 112 | #define ADP5589_GPI_PIN_COL6 111 |
| 113 | #define ADP5589_GPI_PIN_COL7 112 |
| 114 | #define ADP5589_GPI_PIN_COL8 113 |
| 115 | #define ADP5589_GPI_PIN_COL9 114 |
| 116 | #define ADP5589_GPI_PIN_COL10 115 |
| 117 | #define GPI_LOGIC1 116 |
| 118 | #define GPI_LOGIC2 117 |
| 119 | |
| 120 | #define ADP5589_GPI_PIN_ROW_BASE ADP5589_GPI_PIN_ROW0 |
| 121 | #define ADP5589_GPI_PIN_ROW_END ADP5589_GPI_PIN_ROW7 |
| 122 | #define ADP5589_GPI_PIN_COL_BASE ADP5589_GPI_PIN_COL0 |
| 123 | #define ADP5589_GPI_PIN_COL_END ADP5589_GPI_PIN_COL10 |
| 124 | |
| 125 | #define ADP5589_GPI_PIN_BASE ADP5589_GPI_PIN_ROW_BASE |
| 126 | #define ADP5589_GPI_PIN_END ADP5589_GPI_PIN_COL_END |
| 127 | |
| 128 | #define ADP5589_GPIMAPSIZE_MAX (ADP5589_GPI_PIN_END - ADP5589_GPI_PIN_BASE + 1) |
| 129 | |
| 130 | struct adp5589_gpi_map { |
| 131 | unsigned short pin; |
| 132 | unsigned short sw_evt; |
| 133 | }; |
| 134 | |
| 135 | /* scan_cycle_time */ |
| 136 | #define ADP5589_SCAN_CYCLE_10ms 0 |
| 137 | #define ADP5589_SCAN_CYCLE_20ms 1 |
| 138 | #define ADP5589_SCAN_CYCLE_30ms 2 |
| 139 | #define ADP5589_SCAN_CYCLE_40ms 3 |
| 140 | |
| 141 | /* RESET_CFG */ |
| 142 | #define RESET_PULSE_WIDTH_500us 0 |
| 143 | #define RESET_PULSE_WIDTH_1ms 1 |
| 144 | #define RESET_PULSE_WIDTH_2ms 2 |
| 145 | #define RESET_PULSE_WIDTH_10ms 3 |
| 146 | |
| 147 | #define RESET_TRIG_TIME_0ms (0 << 2) |
| 148 | #define RESET_TRIG_TIME_1000ms (1 << 2) |
| 149 | #define RESET_TRIG_TIME_1500ms (2 << 2) |
| 150 | #define RESET_TRIG_TIME_2000ms (3 << 2) |
| 151 | #define RESET_TRIG_TIME_2500ms (4 << 2) |
| 152 | #define RESET_TRIG_TIME_3000ms (5 << 2) |
| 153 | #define RESET_TRIG_TIME_3500ms (6 << 2) |
| 154 | #define RESET_TRIG_TIME_4000ms (7 << 2) |
| 155 | |
| 156 | #define RESET_PASSTHRU_EN (1 << 5) |
| 157 | #define RESET1_POL_HIGH (1 << 6) |
| 158 | #define RESET1_POL_LOW (0 << 6) |
| 159 | #define RESET2_POL_HIGH (1 << 7) |
| 160 | #define RESET2_POL_LOW (0 << 7) |
| 161 | |
| 162 | /* Mask Bits: |
| 163 | * C C C C C C C C C C C | R R R R R R R R |
| 164 | * 1 9 8 7 6 5 4 3 2 1 0 | 7 6 5 4 3 2 1 0 |
| 165 | * 0 |
| 166 | * ---------------- BIT ------------------ |
| 167 | * 1 1 1 1 1 1 1 1 1 0 0 | 0 0 0 0 0 0 0 0 |
| 168 | * 8 7 6 5 4 3 2 1 0 9 8 | 7 6 5 4 3 2 1 0 |
| 169 | */ |
| 170 | |
| 171 | #define ADP_ROW(x) (1 << (x)) |
| 172 | #define ADP_COL(x) (1 << (x + 8)) |
| 173 | |
| 174 | struct adp5589_kpad_platform_data { |
| 175 | unsigned keypad_en_mask; /* Keypad (Rows/Columns) enable mask */ |
| 176 | const unsigned short *keymap; /* Pointer to keymap */ |
| 177 | unsigned short keymapsize; /* Keymap size */ |
| 178 | bool repeat; /* Enable key repeat */ |
| 179 | bool en_keylock; /* Enable key lock feature */ |
| 180 | unsigned char unlock_key1; /* Unlock Key 1 */ |
| 181 | unsigned char unlock_key2; /* Unlock Key 2 */ |
| 182 | unsigned char unlock_timer; /* Time in seconds [0..7] between the two unlock keys 0=disable */ |
| 183 | unsigned char scan_cycle_time; /* Time between consecutive scan cycles */ |
| 184 | unsigned char reset_cfg; /* Reset config */ |
| 185 | unsigned short reset1_key_1; /* Reset Key 1 */ |
| 186 | unsigned short reset1_key_2; /* Reset Key 2 */ |
| 187 | unsigned short reset1_key_3; /* Reset Key 3 */ |
| 188 | unsigned short reset2_key_1; /* Reset Key 1 */ |
| 189 | unsigned short reset2_key_2; /* Reset Key 2 */ |
| 190 | unsigned debounce_dis_mask; /* Disable debounce mask */ |
| 191 | unsigned pull_dis_mask; /* Disable all pull resistors mask */ |
| 192 | unsigned pullup_en_100k; /* Pull-Up 100k Enable Mask */ |
| 193 | unsigned pullup_en_300k; /* Pull-Up 300k Enable Mask */ |
| 194 | unsigned pulldown_en_300k; /* Pull-Down 300k Enable Mask */ |
| 195 | const struct adp5589_gpi_map *gpimap; |
| 196 | unsigned short gpimapsize; |
| 197 | const struct adp5589_gpio_platform_data *gpio_data; |
| 198 | }; |
| 199 | |
| 200 | struct i2c_client; /* forward declaration */ |
| 201 | |
| 202 | struct adp5589_gpio_platform_data { |
| 203 | int gpio_start; /* GPIO Chip base # */ |
| 204 | int (*setup)(struct i2c_client *client, |
| 205 | int gpio, unsigned ngpio, |
| 206 | void *context); |
| 207 | int (*teardown)(struct i2c_client *client, |
| 208 | int gpio, unsigned ngpio, |
| 209 | void *context); |
| 210 | void *context; |
| 211 | }; |
| 212 | |
| 213 | #endif |