blob: a7c08d7027faff2e4ae863ecdd1550b3e46f01ba [file] [log] [blame]
Eugeni Dodonov45244b82012-05-09 15:37:20 -03001/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28#include "i915_drv.h"
29#include "intel_drv.h"
30
Jani Nikula10122052014-08-27 16:27:30 +030031struct ddi_buf_trans {
32 u32 trans1; /* balance leg enable, de-emph level */
33 u32 trans2; /* vref sel, vswing */
David Weinehallf8896f52015-06-25 11:11:03 +030034 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
Jani Nikula10122052014-08-27 16:27:30 +030035};
36
Ville Syrjälä97eeb872017-02-23 19:35:06 +020037static const u8 index_to_dp_signal_levels[] = {
38 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
39 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
40 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
41 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
42 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
43 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
44 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
45 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
46 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
47 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
48};
49
Eugeni Dodonov45244b82012-05-09 15:37:20 -030050/* HDMI/DVI modes ignore everything but the last 2 items. So we share
51 * them for both DP and FDI transports, allowing those ports to
52 * automatically adapt to HDMI connections as well
53 */
Jani Nikula10122052014-08-27 16:27:30 +030054static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
David Weinehallf8896f52015-06-25 11:11:03 +030055 { 0x00FFFFFF, 0x0006000E, 0x0 },
56 { 0x00D75FFF, 0x0005000A, 0x0 },
57 { 0x00C30FFF, 0x00040006, 0x0 },
58 { 0x80AAAFFF, 0x000B0000, 0x0 },
59 { 0x00FFFFFF, 0x0005000A, 0x0 },
60 { 0x00D75FFF, 0x000C0004, 0x0 },
61 { 0x80C30FFF, 0x000B0000, 0x0 },
62 { 0x00FFFFFF, 0x00040006, 0x0 },
63 { 0x80D75FFF, 0x000B0000, 0x0 },
Eugeni Dodonov45244b82012-05-09 15:37:20 -030064};
65
Jani Nikula10122052014-08-27 16:27:30 +030066static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
David Weinehallf8896f52015-06-25 11:11:03 +030067 { 0x00FFFFFF, 0x0007000E, 0x0 },
68 { 0x00D75FFF, 0x000F000A, 0x0 },
69 { 0x00C30FFF, 0x00060006, 0x0 },
70 { 0x00AAAFFF, 0x001E0000, 0x0 },
71 { 0x00FFFFFF, 0x000F000A, 0x0 },
72 { 0x00D75FFF, 0x00160004, 0x0 },
73 { 0x00C30FFF, 0x001E0000, 0x0 },
74 { 0x00FFFFFF, 0x00060006, 0x0 },
75 { 0x00D75FFF, 0x001E0000, 0x0 },
Paulo Zanoni6acab152013-09-12 17:06:24 -030076};
77
Jani Nikula10122052014-08-27 16:27:30 +030078static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
79 /* Idx NT mV d T mV d db */
David Weinehallf8896f52015-06-25 11:11:03 +030080 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
81 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
82 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
83 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
84 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
85 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
86 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
87 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
88 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
89 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
90 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
91 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
Eugeni Dodonov45244b82012-05-09 15:37:20 -030092};
93
Jani Nikula10122052014-08-27 16:27:30 +030094static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
David Weinehallf8896f52015-06-25 11:11:03 +030095 { 0x00FFFFFF, 0x00000012, 0x0 },
96 { 0x00EBAFFF, 0x00020011, 0x0 },
97 { 0x00C71FFF, 0x0006000F, 0x0 },
98 { 0x00AAAFFF, 0x000E000A, 0x0 },
99 { 0x00FFFFFF, 0x00020011, 0x0 },
100 { 0x00DB6FFF, 0x0005000F, 0x0 },
101 { 0x00BEEFFF, 0x000A000C, 0x0 },
102 { 0x00FFFFFF, 0x0005000F, 0x0 },
103 { 0x00DB6FFF, 0x000A000C, 0x0 },
Paulo Zanoni300644c2013-11-02 21:07:42 -0700104};
105
Jani Nikula10122052014-08-27 16:27:30 +0300106static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
David Weinehallf8896f52015-06-25 11:11:03 +0300107 { 0x00FFFFFF, 0x0007000E, 0x0 },
108 { 0x00D75FFF, 0x000E000A, 0x0 },
109 { 0x00BEFFFF, 0x00140006, 0x0 },
110 { 0x80B2CFFF, 0x001B0002, 0x0 },
111 { 0x00FFFFFF, 0x000E000A, 0x0 },
112 { 0x00DB6FFF, 0x00160005, 0x0 },
113 { 0x80C71FFF, 0x001A0002, 0x0 },
114 { 0x00F7DFFF, 0x00180004, 0x0 },
115 { 0x80D75FFF, 0x001B0002, 0x0 },
Art Runyane58623c2013-11-02 21:07:41 -0700116};
117
Jani Nikula10122052014-08-27 16:27:30 +0300118static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
David Weinehallf8896f52015-06-25 11:11:03 +0300119 { 0x00FFFFFF, 0x0001000E, 0x0 },
120 { 0x00D75FFF, 0x0004000A, 0x0 },
121 { 0x00C30FFF, 0x00070006, 0x0 },
122 { 0x00AAAFFF, 0x000C0000, 0x0 },
123 { 0x00FFFFFF, 0x0004000A, 0x0 },
124 { 0x00D75FFF, 0x00090004, 0x0 },
125 { 0x00C30FFF, 0x000C0000, 0x0 },
126 { 0x00FFFFFF, 0x00070006, 0x0 },
127 { 0x00D75FFF, 0x000C0000, 0x0 },
Art Runyane58623c2013-11-02 21:07:41 -0700128};
129
Jani Nikula10122052014-08-27 16:27:30 +0300130static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
131 /* Idx NT mV d T mV df db */
David Weinehallf8896f52015-06-25 11:11:03 +0300132 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
133 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
134 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
135 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
136 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
137 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
138 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
139 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
140 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
141 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
Damien Lespiaua26aa8b2014-08-01 11:07:55 +0100142};
143
Rodrigo Vivi5f8b2532015-08-24 16:48:44 -0700144/* Skylake H and S */
Damien Lespiau7f88e3a2013-12-03 13:56:25 +0000145static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
David Weinehallf8896f52015-06-25 11:11:03 +0300146 { 0x00002016, 0x000000A0, 0x0 },
147 { 0x00005012, 0x0000009B, 0x0 },
148 { 0x00007011, 0x00000088, 0x0 },
Rodrigo Vivid7097cf2016-01-05 11:18:55 -0800149 { 0x80009010, 0x000000C0, 0x1 },
David Weinehallf8896f52015-06-25 11:11:03 +0300150 { 0x00002016, 0x0000009B, 0x0 },
151 { 0x00005012, 0x00000088, 0x0 },
Rodrigo Vivid7097cf2016-01-05 11:18:55 -0800152 { 0x80007011, 0x000000C0, 0x1 },
David Weinehallf8896f52015-06-25 11:11:03 +0300153 { 0x00002016, 0x000000DF, 0x0 },
Rodrigo Vivid7097cf2016-01-05 11:18:55 -0800154 { 0x80005012, 0x000000C0, 0x1 },
Damien Lespiau7f88e3a2013-12-03 13:56:25 +0000155};
156
David Weinehallf8896f52015-06-25 11:11:03 +0300157/* Skylake U */
158static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
Rodrigo Vivi5f8b2532015-08-24 16:48:44 -0700159 { 0x0000201B, 0x000000A2, 0x0 },
David Weinehallf8896f52015-06-25 11:11:03 +0300160 { 0x00005012, 0x00000088, 0x0 },
Ville Syrjälä5ac90562016-08-02 15:21:57 +0300161 { 0x80007011, 0x000000CD, 0x1 },
Rodrigo Vivid7097cf2016-01-05 11:18:55 -0800162 { 0x80009010, 0x000000C0, 0x1 },
Rodrigo Vivi5f8b2532015-08-24 16:48:44 -0700163 { 0x0000201B, 0x0000009D, 0x0 },
Rodrigo Vivid7097cf2016-01-05 11:18:55 -0800164 { 0x80005012, 0x000000C0, 0x1 },
165 { 0x80007011, 0x000000C0, 0x1 },
David Weinehallf8896f52015-06-25 11:11:03 +0300166 { 0x00002016, 0x00000088, 0x0 },
Rodrigo Vivid7097cf2016-01-05 11:18:55 -0800167 { 0x80005012, 0x000000C0, 0x1 },
David Weinehallf8896f52015-06-25 11:11:03 +0300168};
169
Rodrigo Vivi5f8b2532015-08-24 16:48:44 -0700170/* Skylake Y */
171static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
David Weinehallf8896f52015-06-25 11:11:03 +0300172 { 0x00000018, 0x000000A2, 0x0 },
173 { 0x00005012, 0x00000088, 0x0 },
Ville Syrjälä5ac90562016-08-02 15:21:57 +0300174 { 0x80007011, 0x000000CD, 0x3 },
Rodrigo Vivid7097cf2016-01-05 11:18:55 -0800175 { 0x80009010, 0x000000C0, 0x3 },
David Weinehallf8896f52015-06-25 11:11:03 +0300176 { 0x00000018, 0x0000009D, 0x0 },
Rodrigo Vivid7097cf2016-01-05 11:18:55 -0800177 { 0x80005012, 0x000000C0, 0x3 },
178 { 0x80007011, 0x000000C0, 0x3 },
David Weinehallf8896f52015-06-25 11:11:03 +0300179 { 0x00000018, 0x00000088, 0x0 },
Rodrigo Vivid7097cf2016-01-05 11:18:55 -0800180 { 0x80005012, 0x000000C0, 0x3 },
David Weinehallf8896f52015-06-25 11:11:03 +0300181};
182
Rodrigo Vivi0fdd4912016-10-18 08:57:36 -0700183/* Kabylake H and S */
184static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
185 { 0x00002016, 0x000000A0, 0x0 },
186 { 0x00005012, 0x0000009B, 0x0 },
187 { 0x00007011, 0x00000088, 0x0 },
188 { 0x80009010, 0x000000C0, 0x1 },
189 { 0x00002016, 0x0000009B, 0x0 },
190 { 0x00005012, 0x00000088, 0x0 },
191 { 0x80007011, 0x000000C0, 0x1 },
192 { 0x00002016, 0x00000097, 0x0 },
193 { 0x80005012, 0x000000C0, 0x1 },
194};
195
196/* Kabylake U */
197static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
198 { 0x0000201B, 0x000000A1, 0x0 },
199 { 0x00005012, 0x00000088, 0x0 },
200 { 0x80007011, 0x000000CD, 0x3 },
201 { 0x80009010, 0x000000C0, 0x3 },
202 { 0x0000201B, 0x0000009D, 0x0 },
203 { 0x80005012, 0x000000C0, 0x3 },
204 { 0x80007011, 0x000000C0, 0x3 },
205 { 0x00002016, 0x0000004F, 0x0 },
206 { 0x80005012, 0x000000C0, 0x3 },
207};
208
209/* Kabylake Y */
210static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
211 { 0x00001017, 0x000000A1, 0x0 },
212 { 0x00005012, 0x00000088, 0x0 },
213 { 0x80007011, 0x000000CD, 0x3 },
214 { 0x8000800F, 0x000000C0, 0x3 },
215 { 0x00001017, 0x0000009D, 0x0 },
216 { 0x80005012, 0x000000C0, 0x3 },
217 { 0x80007011, 0x000000C0, 0x3 },
218 { 0x00001017, 0x0000004C, 0x0 },
219 { 0x80005012, 0x000000C0, 0x3 },
220};
221
David Weinehallf8896f52015-06-25 11:11:03 +0300222/*
Rodrigo Vivi0fdd4912016-10-18 08:57:36 -0700223 * Skylake/Kabylake H and S
David Weinehallf8896f52015-06-25 11:11:03 +0300224 * eDP 1.4 low vswing translation parameters
225 */
Sonika Jindal7ad14a22015-02-25 10:29:12 +0530226static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
David Weinehallf8896f52015-06-25 11:11:03 +0300227 { 0x00000018, 0x000000A8, 0x0 },
228 { 0x00004013, 0x000000A9, 0x0 },
229 { 0x00007011, 0x000000A2, 0x0 },
230 { 0x00009010, 0x0000009C, 0x0 },
231 { 0x00000018, 0x000000A9, 0x0 },
232 { 0x00006013, 0x000000A2, 0x0 },
233 { 0x00007011, 0x000000A6, 0x0 },
234 { 0x00000018, 0x000000AB, 0x0 },
235 { 0x00007013, 0x0000009F, 0x0 },
236 { 0x00000018, 0x000000DF, 0x0 },
Sonika Jindal7ad14a22015-02-25 10:29:12 +0530237};
238
David Weinehallf8896f52015-06-25 11:11:03 +0300239/*
Rodrigo Vivi0fdd4912016-10-18 08:57:36 -0700240 * Skylake/Kabylake U
David Weinehallf8896f52015-06-25 11:11:03 +0300241 * eDP 1.4 low vswing translation parameters
242 */
243static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
244 { 0x00000018, 0x000000A8, 0x0 },
245 { 0x00004013, 0x000000A9, 0x0 },
246 { 0x00007011, 0x000000A2, 0x0 },
247 { 0x00009010, 0x0000009C, 0x0 },
248 { 0x00000018, 0x000000A9, 0x0 },
249 { 0x00006013, 0x000000A2, 0x0 },
250 { 0x00007011, 0x000000A6, 0x0 },
251 { 0x00002016, 0x000000AB, 0x0 },
252 { 0x00005013, 0x0000009F, 0x0 },
253 { 0x00000018, 0x000000DF, 0x0 },
254};
Sonika Jindal7ad14a22015-02-25 10:29:12 +0530255
David Weinehallf8896f52015-06-25 11:11:03 +0300256/*
Rodrigo Vivi0fdd4912016-10-18 08:57:36 -0700257 * Skylake/Kabylake Y
David Weinehallf8896f52015-06-25 11:11:03 +0300258 * eDP 1.4 low vswing translation parameters
259 */
Rodrigo Vivi5f8b2532015-08-24 16:48:44 -0700260static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
David Weinehallf8896f52015-06-25 11:11:03 +0300261 { 0x00000018, 0x000000A8, 0x0 },
262 { 0x00004013, 0x000000AB, 0x0 },
263 { 0x00007011, 0x000000A4, 0x0 },
264 { 0x00009010, 0x000000DF, 0x0 },
265 { 0x00000018, 0x000000AA, 0x0 },
266 { 0x00006013, 0x000000A4, 0x0 },
267 { 0x00007011, 0x0000009D, 0x0 },
268 { 0x00000018, 0x000000A0, 0x0 },
269 { 0x00006012, 0x000000DF, 0x0 },
270 { 0x00000018, 0x0000008A, 0x0 },
271};
272
Rodrigo Vivi0fdd4912016-10-18 08:57:36 -0700273/* Skylake/Kabylake U, H and S */
Damien Lespiau7f88e3a2013-12-03 13:56:25 +0000274static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
David Weinehallf8896f52015-06-25 11:11:03 +0300275 { 0x00000018, 0x000000AC, 0x0 },
276 { 0x00005012, 0x0000009D, 0x0 },
277 { 0x00007011, 0x00000088, 0x0 },
278 { 0x00000018, 0x000000A1, 0x0 },
279 { 0x00000018, 0x00000098, 0x0 },
280 { 0x00004013, 0x00000088, 0x0 },
Rodrigo Vivi2e784162016-01-05 11:11:27 -0800281 { 0x80006012, 0x000000CD, 0x1 },
David Weinehallf8896f52015-06-25 11:11:03 +0300282 { 0x00000018, 0x000000DF, 0x0 },
Rodrigo Vivi2e784162016-01-05 11:11:27 -0800283 { 0x80003015, 0x000000CD, 0x1 }, /* Default */
284 { 0x80003015, 0x000000C0, 0x1 },
285 { 0x80000018, 0x000000C0, 0x1 },
David Weinehallf8896f52015-06-25 11:11:03 +0300286};
287
Rodrigo Vivi0fdd4912016-10-18 08:57:36 -0700288/* Skylake/Kabylake Y */
Rodrigo Vivi5f8b2532015-08-24 16:48:44 -0700289static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
David Weinehallf8896f52015-06-25 11:11:03 +0300290 { 0x00000018, 0x000000A1, 0x0 },
291 { 0x00005012, 0x000000DF, 0x0 },
Rodrigo Vivi2e784162016-01-05 11:11:27 -0800292 { 0x80007011, 0x000000CB, 0x3 },
David Weinehallf8896f52015-06-25 11:11:03 +0300293 { 0x00000018, 0x000000A4, 0x0 },
294 { 0x00000018, 0x0000009D, 0x0 },
295 { 0x00004013, 0x00000080, 0x0 },
Rodrigo Vivi2e784162016-01-05 11:11:27 -0800296 { 0x80006013, 0x000000C0, 0x3 },
David Weinehallf8896f52015-06-25 11:11:03 +0300297 { 0x00000018, 0x0000008A, 0x0 },
Rodrigo Vivi2e784162016-01-05 11:11:27 -0800298 { 0x80003015, 0x000000C0, 0x3 }, /* Default */
299 { 0x80003015, 0x000000C0, 0x3 },
300 { 0x80000018, 0x000000C0, 0x3 },
Damien Lespiau7f88e3a2013-12-03 13:56:25 +0000301};
302
Vandana Kannan96fb9f92014-11-18 15:45:27 +0530303struct bxt_ddi_buf_trans {
304 u32 margin; /* swing value */
305 u32 scale; /* scale value */
306 u32 enable; /* scale enable */
307 u32 deemphasis;
308 bool default_index; /* true if the entry represents default value */
309};
310
Vandana Kannan96fb9f92014-11-18 15:45:27 +0530311static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
312 /* Idx NT mV diff db */
Imre Deakfe4c63c2015-06-04 18:01:35 +0300313 { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */
314 { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
315 { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */
316 { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
317 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
318 { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
319 { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */
320 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
321 { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
David Weinehallf8896f52015-06-25 11:11:03 +0300322 { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */
Vandana Kannan96fb9f92014-11-18 15:45:27 +0530323};
324
Sonika Jindald9d70002015-09-24 10:24:56 +0530325static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
326 /* Idx NT mV diff db */
327 { 26, 0, 0, 128, false }, /* 0: 200 0 */
328 { 38, 0, 0, 112, false }, /* 1: 200 1.5 */
329 { 48, 0, 0, 96, false }, /* 2: 200 4 */
330 { 54, 0, 0, 69, false }, /* 3: 200 6 */
331 { 32, 0, 0, 128, false }, /* 4: 250 0 */
332 { 48, 0, 0, 104, false }, /* 5: 250 1.5 */
333 { 54, 0, 0, 85, false }, /* 6: 250 4 */
334 { 43, 0, 0, 128, false }, /* 7: 300 0 */
335 { 54, 0, 0, 101, false }, /* 8: 300 1.5 */
336 { 48, 0, 0, 128, false }, /* 9: 300 0 */
337};
338
Vandana Kannan96fb9f92014-11-18 15:45:27 +0530339/* BSpec has 2 recommended values - entries 0 and 8.
340 * Using the entry with higher vswing.
341 */
342static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
343 /* Idx NT mV diff db */
Imre Deakfe4c63c2015-06-04 18:01:35 +0300344 { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */
345 { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
346 { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */
347 { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
348 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
349 { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
350 { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */
351 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
352 { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
Vandana Kannan96fb9f92014-11-18 15:45:27 +0530353 { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */
354};
355
Ville Syrjälä5a5d24d2016-07-12 15:59:35 +0300356enum port intel_ddi_get_encoder_port(struct intel_encoder *encoder)
Paulo Zanonifc914632012-10-05 12:05:54 -0300357{
Ville Syrjälä5a5d24d2016-07-12 15:59:35 +0300358 switch (encoder->type) {
Jani Nikula8cd21b72015-09-29 10:24:26 +0300359 case INTEL_OUTPUT_DP_MST:
Ville Syrjälä5a5d24d2016-07-12 15:59:35 +0300360 return enc_to_mst(&encoder->base)->primary->port;
Ville Syrjäläcca05022016-06-22 21:57:06 +0300361 case INTEL_OUTPUT_DP:
Jani Nikula8cd21b72015-09-29 10:24:26 +0300362 case INTEL_OUTPUT_EDP:
363 case INTEL_OUTPUT_HDMI:
364 case INTEL_OUTPUT_UNKNOWN:
Ville Syrjälä5a5d24d2016-07-12 15:59:35 +0300365 return enc_to_dig_port(&encoder->base)->port;
Jani Nikula8cd21b72015-09-29 10:24:26 +0300366 case INTEL_OUTPUT_ANALOG:
Ville Syrjälä5a5d24d2016-07-12 15:59:35 +0300367 return PORT_E;
368 default:
369 MISSING_CASE(encoder->type);
370 return PORT_A;
Paulo Zanonifc914632012-10-05 12:05:54 -0300371 }
372}
373
Ville Syrjäläacee2992015-12-08 19:59:39 +0200374static const struct ddi_buf_trans *
Ville Syrjäläa930acd2016-07-12 15:59:36 +0300375bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
376{
377 if (dev_priv->vbt.edp.low_vswing) {
378 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
379 return bdw_ddi_translations_edp;
380 } else {
381 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
382 return bdw_ddi_translations_dp;
383 }
384}
385
386static const struct ddi_buf_trans *
Ville Syrjälä78ab0ba2015-12-08 19:59:41 +0200387skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
David Weinehallf8896f52015-06-25 11:11:03 +0300388{
Rodrigo Vivi0fdd4912016-10-18 08:57:36 -0700389 if (IS_SKL_ULX(dev_priv)) {
Rodrigo Vivi5f8b2532015-08-24 16:48:44 -0700390 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
Ville Syrjäläacee2992015-12-08 19:59:39 +0200391 return skl_y_ddi_translations_dp;
Rodrigo Vivi0fdd4912016-10-18 08:57:36 -0700392 } else if (IS_SKL_ULT(dev_priv)) {
David Weinehallf8896f52015-06-25 11:11:03 +0300393 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
Ville Syrjäläacee2992015-12-08 19:59:39 +0200394 return skl_u_ddi_translations_dp;
David Weinehallf8896f52015-06-25 11:11:03 +0300395 } else {
David Weinehallf8896f52015-06-25 11:11:03 +0300396 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
Ville Syrjäläacee2992015-12-08 19:59:39 +0200397 return skl_ddi_translations_dp;
David Weinehallf8896f52015-06-25 11:11:03 +0300398 }
David Weinehallf8896f52015-06-25 11:11:03 +0300399}
400
401static const struct ddi_buf_trans *
Rodrigo Vivi0fdd4912016-10-18 08:57:36 -0700402kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
403{
404 if (IS_KBL_ULX(dev_priv)) {
405 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
406 return kbl_y_ddi_translations_dp;
407 } else if (IS_KBL_ULT(dev_priv)) {
408 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
409 return kbl_u_ddi_translations_dp;
410 } else {
411 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
412 return kbl_ddi_translations_dp;
413 }
414}
415
416static const struct ddi_buf_trans *
Ville Syrjälä78ab0ba2015-12-08 19:59:41 +0200417skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
David Weinehallf8896f52015-06-25 11:11:03 +0300418{
Jani Nikula06411f02016-03-24 17:50:21 +0200419 if (dev_priv->vbt.edp.low_vswing) {
Ville Syrjälä78ab0ba2015-12-08 19:59:41 +0200420 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
Ville Syrjäläacee2992015-12-08 19:59:39 +0200421 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
422 return skl_y_ddi_translations_edp;
Ville Syrjälä78ab0ba2015-12-08 19:59:41 +0200423 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)) {
Ville Syrjäläacee2992015-12-08 19:59:39 +0200424 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
425 return skl_u_ddi_translations_edp;
426 } else {
Ville Syrjäläacee2992015-12-08 19:59:39 +0200427 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
428 return skl_ddi_translations_edp;
Ville Syrjäläacee2992015-12-08 19:59:39 +0200429 }
David Weinehallf8896f52015-06-25 11:11:03 +0300430 }
Ville Syrjäläcd1101c2015-12-08 19:59:40 +0200431
Rodrigo Vivi0fdd4912016-10-18 08:57:36 -0700432 if (IS_KABYLAKE(dev_priv))
433 return kbl_get_buf_trans_dp(dev_priv, n_entries);
434 else
435 return skl_get_buf_trans_dp(dev_priv, n_entries);
Ville Syrjäläacee2992015-12-08 19:59:39 +0200436}
David Weinehallf8896f52015-06-25 11:11:03 +0300437
Ville Syrjäläacee2992015-12-08 19:59:39 +0200438static const struct ddi_buf_trans *
Ville Syrjälä78ab0ba2015-12-08 19:59:41 +0200439skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
Ville Syrjäläacee2992015-12-08 19:59:39 +0200440{
Ville Syrjälä78ab0ba2015-12-08 19:59:41 +0200441 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
Ville Syrjäläacee2992015-12-08 19:59:39 +0200442 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
443 return skl_y_ddi_translations_hdmi;
444 } else {
445 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
446 return skl_ddi_translations_hdmi;
447 }
David Weinehallf8896f52015-06-25 11:11:03 +0300448}
449
Ville Syrjälä8d8bb852016-07-12 15:59:30 +0300450static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
451{
452 int n_hdmi_entries;
453 int hdmi_level;
454 int hdmi_default_entry;
455
456 hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
457
Ander Conselvan de Oliveiracc3f90f2016-12-02 10:23:49 +0200458 if (IS_GEN9_LP(dev_priv))
Ville Syrjälä8d8bb852016-07-12 15:59:30 +0300459 return hdmi_level;
460
Rodrigo Vivib976dc52017-01-23 10:32:37 -0800461 if (IS_GEN9_BC(dev_priv)) {
Ville Syrjälä8d8bb852016-07-12 15:59:30 +0300462 skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
463 hdmi_default_entry = 8;
464 } else if (IS_BROADWELL(dev_priv)) {
465 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
466 hdmi_default_entry = 7;
467 } else if (IS_HASWELL(dev_priv)) {
468 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
469 hdmi_default_entry = 6;
470 } else {
471 WARN(1, "ddi translation table missing\n");
472 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
473 hdmi_default_entry = 7;
474 }
475
476 /* Choose a good default if VBT is badly populated */
477 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
478 hdmi_level >= n_hdmi_entries)
479 hdmi_level = hdmi_default_entry;
480
481 return hdmi_level;
482}
483
Ville Syrjälä7d1c42e2017-02-23 19:35:05 +0200484static const struct ddi_buf_trans *
485intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
486 int *n_entries)
487{
488 if (IS_KABYLAKE(dev_priv)) {
489 return kbl_get_buf_trans_dp(dev_priv, n_entries);
490 } else if (IS_SKYLAKE(dev_priv)) {
491 return skl_get_buf_trans_dp(dev_priv, n_entries);
492 } else if (IS_BROADWELL(dev_priv)) {
493 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
494 return bdw_ddi_translations_dp;
495 } else if (IS_HASWELL(dev_priv)) {
496 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
497 return hsw_ddi_translations_dp;
498 }
499
500 *n_entries = 0;
501 return NULL;
502}
503
504static const struct ddi_buf_trans *
505intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
506 int *n_entries)
507{
508 if (IS_KABYLAKE(dev_priv) || IS_SKYLAKE(dev_priv)) {
509 return skl_get_buf_trans_edp(dev_priv, n_entries);
510 } else if (IS_BROADWELL(dev_priv)) {
511 return bdw_get_buf_trans_edp(dev_priv, n_entries);
512 } else if (IS_HASWELL(dev_priv)) {
513 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
514 return hsw_ddi_translations_dp;
515 }
516
517 *n_entries = 0;
518 return NULL;
519}
520
521static const struct ddi_buf_trans *
522intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
523 int *n_entries)
524{
525 if (IS_BROADWELL(dev_priv)) {
526 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
527 return hsw_ddi_translations_fdi;
528 } else if (IS_HASWELL(dev_priv)) {
529 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
530 return hsw_ddi_translations_fdi;
531 }
532
533 *n_entries = 0;
534 return NULL;
535}
536
Art Runyane58623c2013-11-02 21:07:41 -0700537/*
538 * Starting with Haswell, DDI port buffers must be programmed with correct
Ville Syrjälä32bdc402016-07-12 15:59:33 +0300539 * values in advance. This function programs the correct values for
540 * DP/eDP/FDI use cases.
Eugeni Dodonov45244b82012-05-09 15:37:20 -0300541 */
Ville Syrjälä32bdc402016-07-12 15:59:33 +0300542void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder)
Eugeni Dodonov45244b82012-05-09 15:37:20 -0300543{
Ville Syrjälä6a7e4f92015-12-08 19:59:44 +0200544 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
Antti Koskipaa75067dd2015-07-10 14:10:55 +0300545 u32 iboost_bit = 0;
Ville Syrjälä7d1c42e2017-02-23 19:35:05 +0200546 int i, n_entries;
Ville Syrjälä32bdc402016-07-12 15:59:33 +0300547 enum port port = intel_ddi_get_encoder_port(encoder);
Jani Nikula10122052014-08-27 16:27:30 +0300548 const struct ddi_buf_trans *ddi_translations;
Art Runyane58623c2013-11-02 21:07:41 -0700549
Ander Conselvan de Oliveiracc3f90f2016-12-02 10:23:49 +0200550 if (IS_GEN9_LP(dev_priv))
Vandana Kannan96fb9f92014-11-18 15:45:27 +0530551 return;
Ville Syrjälä6a7e4f92015-12-08 19:59:44 +0200552
Ville Syrjälä7d1c42e2017-02-23 19:35:05 +0200553 switch (encoder->type) {
554 case INTEL_OUTPUT_EDP:
555 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv,
556 &n_entries);
557 break;
558 case INTEL_OUTPUT_DP:
559 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv,
560 &n_entries);
561 break;
562 case INTEL_OUTPUT_ANALOG:
563 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
564 &n_entries);
565 break;
566 default:
567 MISSING_CASE(encoder->type);
568 return;
Art Runyane58623c2013-11-02 21:07:41 -0700569 }
570
Rodrigo Vivib976dc52017-01-23 10:32:37 -0800571 if (IS_GEN9_BC(dev_priv)) {
Rodrigo Vivi0a918772016-09-30 11:05:56 -0700572 /* If we're boosting the current, set bit 31 of trans1 */
573 if (dev_priv->vbt.ddi_port_info[port].dp_boost_level)
574 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
575
576 if (WARN_ON(encoder->type == INTEL_OUTPUT_EDP &&
577 port != PORT_A && port != PORT_E &&
Ville Syrjälä7d1c42e2017-02-23 19:35:05 +0200578 n_entries > 9))
579 n_entries = 9;
Rodrigo Vivi0a918772016-09-30 11:05:56 -0700580 }
581
Ville Syrjälä7d1c42e2017-02-23 19:35:05 +0200582 for (i = 0; i < n_entries; i++) {
Ville Syrjälä9712e682015-09-18 20:03:22 +0300583 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
584 ddi_translations[i].trans1 | iboost_bit);
585 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
586 ddi_translations[i].trans2);
Eugeni Dodonov45244b82012-05-09 15:37:20 -0300587 }
Ville Syrjälä32bdc402016-07-12 15:59:33 +0300588}
Damien Lespiauce4dd492014-08-01 11:07:54 +0100589
Ville Syrjälä32bdc402016-07-12 15:59:33 +0300590/*
591 * Starting with Haswell, DDI port buffers must be programmed with correct
592 * values in advance. This function programs the correct values for
593 * HDMI/DVI use cases.
594 */
595static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder)
596{
597 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
598 u32 iboost_bit = 0;
599 int n_hdmi_entries, hdmi_level;
600 enum port port = intel_ddi_get_encoder_port(encoder);
601 const struct ddi_buf_trans *ddi_translations_hdmi;
602
Ander Conselvan de Oliveiracc3f90f2016-12-02 10:23:49 +0200603 if (IS_GEN9_LP(dev_priv))
Damien Lespiauce3b7e92014-08-04 15:04:43 +0100604 return;
605
Ville Syrjälä32bdc402016-07-12 15:59:33 +0300606 hdmi_level = intel_ddi_hdmi_level(dev_priv, port);
607
Rodrigo Vivib976dc52017-01-23 10:32:37 -0800608 if (IS_GEN9_BC(dev_priv)) {
Ville Syrjälä32bdc402016-07-12 15:59:33 +0300609 ddi_translations_hdmi = skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
Ville Syrjälä1edaaa22016-07-12 15:59:34 +0300610
Ville Syrjälä32bdc402016-07-12 15:59:33 +0300611 /* If we're boosting the current, set bit 31 of trans1 */
Ville Syrjälä1edaaa22016-07-12 15:59:34 +0300612 if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
Ville Syrjälä32bdc402016-07-12 15:59:33 +0300613 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
614 } else if (IS_BROADWELL(dev_priv)) {
615 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
616 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
617 } else if (IS_HASWELL(dev_priv)) {
618 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
619 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
620 } else {
621 WARN(1, "ddi translation table missing\n");
622 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
623 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
624 }
625
Paulo Zanoni6acab152013-09-12 17:06:24 -0300626 /* Entry 9 is for HDMI: */
Ville Syrjäläed9c77d2016-07-12 15:59:32 +0300627 I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
Ville Syrjälä9712e682015-09-18 20:03:22 +0300628 ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit);
Ville Syrjäläed9c77d2016-07-12 15:59:32 +0300629 I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
Ville Syrjälä9712e682015-09-18 20:03:22 +0300630 ddi_translations_hdmi[hdmi_level].trans2);
Eugeni Dodonov45244b82012-05-09 15:37:20 -0300631}
632
Paulo Zanoni248138b2012-11-29 11:29:31 -0200633static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
634 enum port port)
635{
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200636 i915_reg_t reg = DDI_BUF_CTL(port);
Paulo Zanoni248138b2012-11-29 11:29:31 -0200637 int i;
638
Vandana Kannan3449ca82015-03-27 14:19:09 +0200639 for (i = 0; i < 16; i++) {
Paulo Zanoni248138b2012-11-29 11:29:31 -0200640 udelay(1);
641 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
642 return;
643 }
644 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
645}
Eugeni Dodonovc82e4d22012-05-09 15:37:21 -0300646
Ander Conselvan de Oliveirac8560522016-09-01 15:08:07 -0700647static uint32_t hsw_pll_to_ddi_pll_sel(struct intel_shared_dpll *pll)
648{
649 switch (pll->id) {
650 case DPLL_ID_WRPLL1:
651 return PORT_CLK_SEL_WRPLL1;
652 case DPLL_ID_WRPLL2:
653 return PORT_CLK_SEL_WRPLL2;
654 case DPLL_ID_SPLL:
655 return PORT_CLK_SEL_SPLL;
656 case DPLL_ID_LCPLL_810:
657 return PORT_CLK_SEL_LCPLL_810;
658 case DPLL_ID_LCPLL_1350:
659 return PORT_CLK_SEL_LCPLL_1350;
660 case DPLL_ID_LCPLL_2700:
661 return PORT_CLK_SEL_LCPLL_2700;
662 default:
663 MISSING_CASE(pll->id);
664 return PORT_CLK_SEL_NONE;
665 }
666}
667
Eugeni Dodonovc82e4d22012-05-09 15:37:21 -0300668/* Starting with Haswell, different DDI ports can work in FDI mode for
669 * connection to the PCH-located connectors. For this, it is necessary to train
670 * both the DDI port and PCH receiver for the desired DDI buffer settings.
671 *
672 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
673 * please note that when FDI mode is active on DDI E, it shares 2 lines with
674 * DDI A (which is used for eDP)
675 */
676
677void hsw_fdi_link_train(struct drm_crtc *crtc)
678{
679 struct drm_device *dev = crtc->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +0100680 struct drm_i915_private *dev_priv = to_i915(dev);
Eugeni Dodonovc82e4d22012-05-09 15:37:21 -0300681 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Ville Syrjälä6a7e4f92015-12-08 19:59:44 +0200682 struct intel_encoder *encoder;
Ander Conselvan de Oliveirac8560522016-09-01 15:08:07 -0700683 u32 temp, i, rx_ctl_val, ddi_pll_sel;
Eugeni Dodonovc82e4d22012-05-09 15:37:21 -0300684
Ville Syrjälä6a7e4f92015-12-08 19:59:44 +0200685 for_each_encoder_on_crtc(dev, crtc, encoder) {
686 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
Ville Syrjälä32bdc402016-07-12 15:59:33 +0300687 intel_prepare_dp_ddi_buffers(encoder);
Ville Syrjälä6a7e4f92015-12-08 19:59:44 +0200688 }
689
Paulo Zanoni04945642012-11-01 21:00:59 -0200690 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
691 * mode set "sequence for CRT port" document:
692 * - TP1 to TP2 time with the default value
693 * - FDI delay to 90h
Damien Lespiau8693a822013-05-03 18:48:11 +0100694 *
695 * WaFDIAutoLinkSetTimingOverrride:hsw
Paulo Zanoni04945642012-11-01 21:00:59 -0200696 */
Ville Syrjäläeede3b52015-09-18 20:03:30 +0300697 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
Paulo Zanoni04945642012-11-01 21:00:59 -0200698 FDI_RX_PWRDN_LANE0_VAL(2) |
699 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
700
701 /* Enable the PCH Receiver FDI PLL */
Damien Lespiau3e683202012-12-11 18:48:29 +0000702 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
Daniel Vetter33d29b12013-02-13 18:04:45 +0100703 FDI_RX_PLL_ENABLE |
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +0200704 FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
Ville Syrjäläeede3b52015-09-18 20:03:30 +0300705 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
706 POSTING_READ(FDI_RX_CTL(PIPE_A));
Paulo Zanoni04945642012-11-01 21:00:59 -0200707 udelay(220);
708
709 /* Switch from Rawclk to PCDclk */
710 rx_ctl_val |= FDI_PCDCLK;
Ville Syrjäläeede3b52015-09-18 20:03:30 +0300711 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
Paulo Zanoni04945642012-11-01 21:00:59 -0200712
713 /* Configure Port Clock Select */
Ander Conselvan de Oliveirac8560522016-09-01 15:08:07 -0700714 ddi_pll_sel = hsw_pll_to_ddi_pll_sel(intel_crtc->config->shared_dpll);
715 I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
716 WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
Paulo Zanoni04945642012-11-01 21:00:59 -0200717
718 /* Start the training iterating through available voltages and emphasis,
719 * testing each value twice. */
Jani Nikula10122052014-08-27 16:27:30 +0300720 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
Eugeni Dodonovc82e4d22012-05-09 15:37:21 -0300721 /* Configure DP_TP_CTL with auto-training */
722 I915_WRITE(DP_TP_CTL(PORT_E),
723 DP_TP_CTL_FDI_AUTOTRAIN |
724 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
725 DP_TP_CTL_LINK_TRAIN_PAT1 |
726 DP_TP_CTL_ENABLE);
727
Damien Lespiau876a8cd2012-12-11 18:48:30 +0000728 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
729 * DDI E does not support port reversal, the functionality is
730 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
731 * port reversal bit */
Eugeni Dodonovc82e4d22012-05-09 15:37:21 -0300732 I915_WRITE(DDI_BUF_CTL(PORT_E),
Paulo Zanoni04945642012-11-01 21:00:59 -0200733 DDI_BUF_CTL_ENABLE |
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +0200734 ((intel_crtc->config->fdi_lanes - 1) << 1) |
Sonika Jindalc5fe6a02014-08-11 08:57:36 +0530735 DDI_BUF_TRANS_SELECT(i / 2));
Paulo Zanoni04945642012-11-01 21:00:59 -0200736 POSTING_READ(DDI_BUF_CTL(PORT_E));
Eugeni Dodonovc82e4d22012-05-09 15:37:21 -0300737
738 udelay(600);
739
Paulo Zanoni04945642012-11-01 21:00:59 -0200740 /* Program PCH FDI Receiver TU */
Ville Syrjäläeede3b52015-09-18 20:03:30 +0300741 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
Eugeni Dodonov4acf5182012-07-04 20:15:16 -0300742
Paulo Zanoni04945642012-11-01 21:00:59 -0200743 /* Enable PCH FDI Receiver with auto-training */
744 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
Ville Syrjäläeede3b52015-09-18 20:03:30 +0300745 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
746 POSTING_READ(FDI_RX_CTL(PIPE_A));
Paulo Zanoni04945642012-11-01 21:00:59 -0200747
748 /* Wait for FDI receiver lane calibration */
749 udelay(30);
750
751 /* Unset FDI_RX_MISC pwrdn lanes */
Ville Syrjäläeede3b52015-09-18 20:03:30 +0300752 temp = I915_READ(FDI_RX_MISC(PIPE_A));
Paulo Zanoni04945642012-11-01 21:00:59 -0200753 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
Ville Syrjäläeede3b52015-09-18 20:03:30 +0300754 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
755 POSTING_READ(FDI_RX_MISC(PIPE_A));
Paulo Zanoni04945642012-11-01 21:00:59 -0200756
757 /* Wait for FDI auto training time */
758 udelay(5);
Eugeni Dodonovc82e4d22012-05-09 15:37:21 -0300759
760 temp = I915_READ(DP_TP_STATUS(PORT_E));
761 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
Paulo Zanoni04945642012-11-01 21:00:59 -0200762 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
Ville Syrjäläa308ccb2015-12-04 22:22:50 +0200763 break;
764 }
Eugeni Dodonovc82e4d22012-05-09 15:37:21 -0300765
Ville Syrjäläa308ccb2015-12-04 22:22:50 +0200766 /*
767 * Leave things enabled even if we failed to train FDI.
768 * Results in less fireworks from the state checker.
769 */
770 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
771 DRM_ERROR("FDI link training failed!\n");
772 break;
Eugeni Dodonovc82e4d22012-05-09 15:37:21 -0300773 }
Paulo Zanoni04945642012-11-01 21:00:59 -0200774
Ville Syrjälä5b421c52016-03-01 16:16:23 +0200775 rx_ctl_val &= ~FDI_RX_ENABLE;
776 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
777 POSTING_READ(FDI_RX_CTL(PIPE_A));
778
Paulo Zanoni248138b2012-11-29 11:29:31 -0200779 temp = I915_READ(DDI_BUF_CTL(PORT_E));
780 temp &= ~DDI_BUF_CTL_ENABLE;
781 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
782 POSTING_READ(DDI_BUF_CTL(PORT_E));
783
Paulo Zanoni04945642012-11-01 21:00:59 -0200784 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
Paulo Zanoni248138b2012-11-29 11:29:31 -0200785 temp = I915_READ(DP_TP_CTL(PORT_E));
786 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
787 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
788 I915_WRITE(DP_TP_CTL(PORT_E), temp);
789 POSTING_READ(DP_TP_CTL(PORT_E));
790
791 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
Paulo Zanoni04945642012-11-01 21:00:59 -0200792
Paulo Zanoni04945642012-11-01 21:00:59 -0200793 /* Reset FDI_RX_MISC pwrdn lanes */
Ville Syrjäläeede3b52015-09-18 20:03:30 +0300794 temp = I915_READ(FDI_RX_MISC(PIPE_A));
Paulo Zanoni04945642012-11-01 21:00:59 -0200795 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
796 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
Ville Syrjäläeede3b52015-09-18 20:03:30 +0300797 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
798 POSTING_READ(FDI_RX_MISC(PIPE_A));
Eugeni Dodonovc82e4d22012-05-09 15:37:21 -0300799 }
800
Ville Syrjäläa308ccb2015-12-04 22:22:50 +0200801 /* Enable normal pixel sending for FDI */
802 I915_WRITE(DP_TP_CTL(PORT_E),
803 DP_TP_CTL_FDI_AUTOTRAIN |
804 DP_TP_CTL_LINK_TRAIN_NORMAL |
805 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
806 DP_TP_CTL_ENABLE);
Eugeni Dodonovc82e4d22012-05-09 15:37:21 -0300807}
Eugeni Dodonov0e72a5b2012-05-09 15:37:27 -0300808
Dave Airlie44905a272014-05-02 13:36:43 +1000809void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
810{
811 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
812 struct intel_digital_port *intel_dig_port =
813 enc_to_dig_port(&encoder->base);
814
815 intel_dp->DP = intel_dig_port->saved_port_bits |
Sonika Jindalc5fe6a02014-08-11 08:57:36 +0530816 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
Ville Syrjälä901c2da2015-08-17 18:05:12 +0300817 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
Dave Airlie44905a272014-05-02 13:36:43 +1000818}
819
Paulo Zanoni8d9ddbc2012-10-05 12:05:53 -0300820static struct intel_encoder *
821intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
822{
823 struct drm_device *dev = crtc->dev;
824 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
825 struct intel_encoder *intel_encoder, *ret = NULL;
826 int num_encoders = 0;
827
828 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
829 ret = intel_encoder;
830 num_encoders++;
831 }
832
833 if (num_encoders != 1)
Ville Syrjälä84f44ce2013-04-17 17:48:49 +0300834 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
835 pipe_name(intel_crtc->pipe));
Paulo Zanoni8d9ddbc2012-10-05 12:05:53 -0300836
837 BUG_ON(ret == NULL);
838 return ret;
839}
840
Satheeshakrishna Mbcddf612014-08-22 09:49:10 +0530841struct intel_encoder *
Ander Conselvan de Oliveira3165c072015-03-20 16:18:12 +0200842intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200843{
Ander Conselvan de Oliveira3165c072015-03-20 16:18:12 +0200844 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
845 struct intel_encoder *ret = NULL;
846 struct drm_atomic_state *state;
Ander Conselvan de Oliveirada3ced22015-04-21 17:12:59 +0300847 struct drm_connector *connector;
848 struct drm_connector_state *connector_state;
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200849 int num_encoders = 0;
Ander Conselvan de Oliveira3165c072015-03-20 16:18:12 +0200850 int i;
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200851
Ander Conselvan de Oliveira3165c072015-03-20 16:18:12 +0200852 state = crtc_state->base.state;
853
Ander Conselvan de Oliveirada3ced22015-04-21 17:12:59 +0300854 for_each_connector_in_state(state, connector, connector_state, i) {
855 if (connector_state->crtc != crtc_state->base.crtc)
Ander Conselvan de Oliveira3165c072015-03-20 16:18:12 +0200856 continue;
857
Ander Conselvan de Oliveirada3ced22015-04-21 17:12:59 +0300858 ret = to_intel_encoder(connector_state->best_encoder);
Ander Conselvan de Oliveira3165c072015-03-20 16:18:12 +0200859 num_encoders++;
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200860 }
861
862 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
863 pipe_name(crtc->pipe));
864
865 BUG_ON(ret == NULL);
866 return ret;
867}
868
Damien Lespiau1c0b85c2013-05-10 14:01:51 +0100869#define LC_FREQ 2700
Damien Lespiau1c0b85c2013-05-10 14:01:51 +0100870
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200871static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
872 i915_reg_t reg)
Jesse Barnes11578552014-01-21 12:42:10 -0800873{
874 int refclk = LC_FREQ;
875 int n, p, r;
876 u32 wrpll;
877
878 wrpll = I915_READ(reg);
Daniel Vetter114fe482014-06-25 22:01:48 +0300879 switch (wrpll & WRPLL_PLL_REF_MASK) {
880 case WRPLL_PLL_SSC:
881 case WRPLL_PLL_NON_SSC:
Jesse Barnes11578552014-01-21 12:42:10 -0800882 /*
883 * We could calculate spread here, but our checking
884 * code only cares about 5% accuracy, and spread is a max of
885 * 0.5% downspread.
886 */
887 refclk = 135;
888 break;
Daniel Vetter114fe482014-06-25 22:01:48 +0300889 case WRPLL_PLL_LCPLL:
Jesse Barnes11578552014-01-21 12:42:10 -0800890 refclk = LC_FREQ;
891 break;
892 default:
893 WARN(1, "bad wrpll refclk\n");
894 return 0;
895 }
896
897 r = wrpll & WRPLL_DIVIDER_REF_MASK;
898 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
899 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
900
Jesse Barnes20f0ec12014-01-22 12:58:04 -0800901 /* Convert to KHz, p & r have a fixed point portion */
902 return (refclk * n * 100) / (p * r);
Jesse Barnes11578552014-01-21 12:42:10 -0800903}
904
Satheeshakrishna M540e7322014-11-13 14:55:16 +0000905static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
906 uint32_t dpll)
907{
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200908 i915_reg_t cfgcr1_reg, cfgcr2_reg;
Satheeshakrishna M540e7322014-11-13 14:55:16 +0000909 uint32_t cfgcr1_val, cfgcr2_val;
910 uint32_t p0, p1, p2, dco_freq;
911
Ville Syrjälä923c12412015-09-30 17:06:43 +0300912 cfgcr1_reg = DPLL_CFGCR1(dpll);
913 cfgcr2_reg = DPLL_CFGCR2(dpll);
Satheeshakrishna M540e7322014-11-13 14:55:16 +0000914
915 cfgcr1_val = I915_READ(cfgcr1_reg);
916 cfgcr2_val = I915_READ(cfgcr2_reg);
917
918 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
919 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
920
921 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
922 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
923 else
924 p1 = 1;
925
926
927 switch (p0) {
928 case DPLL_CFGCR2_PDIV_1:
929 p0 = 1;
930 break;
931 case DPLL_CFGCR2_PDIV_2:
932 p0 = 2;
933 break;
934 case DPLL_CFGCR2_PDIV_3:
935 p0 = 3;
936 break;
937 case DPLL_CFGCR2_PDIV_7:
938 p0 = 7;
939 break;
940 }
941
942 switch (p2) {
943 case DPLL_CFGCR2_KDIV_5:
944 p2 = 5;
945 break;
946 case DPLL_CFGCR2_KDIV_2:
947 p2 = 2;
948 break;
949 case DPLL_CFGCR2_KDIV_3:
950 p2 = 3;
951 break;
952 case DPLL_CFGCR2_KDIV_1:
953 p2 = 1;
954 break;
955 }
956
957 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
958
959 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
960 1000) / 0x8000;
961
962 return dco_freq / (p0 * p1 * p2 * 5);
963}
964
Ville Syrjälä398a0172015-06-30 15:33:51 +0300965static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
966{
967 int dotclock;
968
969 if (pipe_config->has_pch_encoder)
970 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
971 &pipe_config->fdi_m_n);
Ville Syrjälä37a56502016-06-22 21:57:04 +0300972 else if (intel_crtc_has_dp_encoder(pipe_config))
Ville Syrjälä398a0172015-06-30 15:33:51 +0300973 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
974 &pipe_config->dp_m_n);
975 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
976 dotclock = pipe_config->port_clock * 2 / 3;
977 else
978 dotclock = pipe_config->port_clock;
979
980 if (pipe_config->pixel_multiplier)
981 dotclock /= pipe_config->pixel_multiplier;
982
983 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
984}
Satheeshakrishna M540e7322014-11-13 14:55:16 +0000985
986static void skl_ddi_clock_get(struct intel_encoder *encoder,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +0200987 struct intel_crtc_state *pipe_config)
Satheeshakrishna M540e7322014-11-13 14:55:16 +0000988{
Chris Wilsonfac5e232016-07-04 11:34:36 +0100989 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
Satheeshakrishna M540e7322014-11-13 14:55:16 +0000990 int link_clock = 0;
991 uint32_t dpll_ctl1, dpll;
992
Ander Conselvan de Oliveirac8560522016-09-01 15:08:07 -0700993 dpll = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
Satheeshakrishna M540e7322014-11-13 14:55:16 +0000994
995 dpll_ctl1 = I915_READ(DPLL_CTRL1);
996
997 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
998 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
999 } else {
Damien Lespiau71cd8422015-04-30 16:39:17 +01001000 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
1001 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
Satheeshakrishna M540e7322014-11-13 14:55:16 +00001002
1003 switch (link_clock) {
Damien Lespiau71cd8422015-04-30 16:39:17 +01001004 case DPLL_CTRL1_LINK_RATE_810:
Satheeshakrishna M540e7322014-11-13 14:55:16 +00001005 link_clock = 81000;
1006 break;
Damien Lespiau71cd8422015-04-30 16:39:17 +01001007 case DPLL_CTRL1_LINK_RATE_1080:
Sonika Jindala8f3ef62015-03-05 10:02:30 +05301008 link_clock = 108000;
1009 break;
Damien Lespiau71cd8422015-04-30 16:39:17 +01001010 case DPLL_CTRL1_LINK_RATE_1350:
Satheeshakrishna M540e7322014-11-13 14:55:16 +00001011 link_clock = 135000;
1012 break;
Damien Lespiau71cd8422015-04-30 16:39:17 +01001013 case DPLL_CTRL1_LINK_RATE_1620:
Sonika Jindala8f3ef62015-03-05 10:02:30 +05301014 link_clock = 162000;
1015 break;
Damien Lespiau71cd8422015-04-30 16:39:17 +01001016 case DPLL_CTRL1_LINK_RATE_2160:
Sonika Jindala8f3ef62015-03-05 10:02:30 +05301017 link_clock = 216000;
1018 break;
Damien Lespiau71cd8422015-04-30 16:39:17 +01001019 case DPLL_CTRL1_LINK_RATE_2700:
Satheeshakrishna M540e7322014-11-13 14:55:16 +00001020 link_clock = 270000;
1021 break;
1022 default:
1023 WARN(1, "Unsupported link rate\n");
1024 break;
1025 }
1026 link_clock *= 2;
1027 }
1028
1029 pipe_config->port_clock = link_clock;
1030
Ville Syrjälä398a0172015-06-30 15:33:51 +03001031 ddi_dotclock_get(pipe_config);
Satheeshakrishna M540e7322014-11-13 14:55:16 +00001032}
1033
Daniel Vetter3d51278a2014-07-29 20:57:08 +02001034static void hsw_ddi_clock_get(struct intel_encoder *encoder,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02001035 struct intel_crtc_state *pipe_config)
Jesse Barnes11578552014-01-21 12:42:10 -08001036{
Chris Wilsonfac5e232016-07-04 11:34:36 +01001037 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
Jesse Barnes11578552014-01-21 12:42:10 -08001038 int link_clock = 0;
1039 u32 val, pll;
1040
Ander Conselvan de Oliveirac8560522016-09-01 15:08:07 -07001041 val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
Jesse Barnes11578552014-01-21 12:42:10 -08001042 switch (val & PORT_CLK_SEL_MASK) {
1043 case PORT_CLK_SEL_LCPLL_810:
1044 link_clock = 81000;
1045 break;
1046 case PORT_CLK_SEL_LCPLL_1350:
1047 link_clock = 135000;
1048 break;
1049 case PORT_CLK_SEL_LCPLL_2700:
1050 link_clock = 270000;
1051 break;
1052 case PORT_CLK_SEL_WRPLL1:
Ville Syrjälä01403de2015-09-18 20:03:33 +03001053 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
Jesse Barnes11578552014-01-21 12:42:10 -08001054 break;
1055 case PORT_CLK_SEL_WRPLL2:
Ville Syrjälä01403de2015-09-18 20:03:33 +03001056 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
Jesse Barnes11578552014-01-21 12:42:10 -08001057 break;
1058 case PORT_CLK_SEL_SPLL:
1059 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1060 if (pll == SPLL_PLL_FREQ_810MHz)
1061 link_clock = 81000;
1062 else if (pll == SPLL_PLL_FREQ_1350MHz)
1063 link_clock = 135000;
1064 else if (pll == SPLL_PLL_FREQ_2700MHz)
1065 link_clock = 270000;
1066 else {
1067 WARN(1, "bad spll freq\n");
1068 return;
1069 }
1070 break;
1071 default:
1072 WARN(1, "bad port clock sel\n");
1073 return;
1074 }
1075
1076 pipe_config->port_clock = link_clock * 2;
1077
Ville Syrjälä398a0172015-06-30 15:33:51 +03001078 ddi_dotclock_get(pipe_config);
Jesse Barnes11578552014-01-21 12:42:10 -08001079}
1080
Satheeshakrishna M977bb382014-08-22 09:49:12 +05301081static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
1082 enum intel_dpll_id dpll)
1083{
Imre Deakaa610dc2015-06-22 23:35:52 +03001084 struct intel_shared_dpll *pll;
1085 struct intel_dpll_hw_state *state;
Ander Conselvan de Oliveira9e2c8472016-05-04 12:11:57 +03001086 struct dpll clock;
Imre Deakaa610dc2015-06-22 23:35:52 +03001087
1088 /* For DDI ports we always use a shared PLL. */
1089 if (WARN_ON(dpll == DPLL_ID_PRIVATE))
1090 return 0;
1091
1092 pll = &dev_priv->shared_dplls[dpll];
Ander Conselvan de Oliveira2c42e532016-12-29 17:22:09 +02001093 state = &pll->state.hw_state;
Imre Deakaa610dc2015-06-22 23:35:52 +03001094
1095 clock.m1 = 2;
1096 clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
1097 if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1098 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
1099 clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1100 clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1101 clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1102
1103 return chv_calc_dpll_params(100000, &clock);
Satheeshakrishna M977bb382014-08-22 09:49:12 +05301104}
1105
1106static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1107 struct intel_crtc_state *pipe_config)
1108{
Chris Wilsonfac5e232016-07-04 11:34:36 +01001109 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
Satheeshakrishna M977bb382014-08-22 09:49:12 +05301110 enum port port = intel_ddi_get_encoder_port(encoder);
1111 uint32_t dpll = port;
1112
Ville Syrjälä398a0172015-06-30 15:33:51 +03001113 pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll);
Satheeshakrishna M977bb382014-08-22 09:49:12 +05301114
Ville Syrjälä398a0172015-06-30 15:33:51 +03001115 ddi_dotclock_get(pipe_config);
Satheeshakrishna M977bb382014-08-22 09:49:12 +05301116}
1117
Daniel Vetter3d51278a2014-07-29 20:57:08 +02001118void intel_ddi_clock_get(struct intel_encoder *encoder,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02001119 struct intel_crtc_state *pipe_config)
Daniel Vetter3d51278a2014-07-29 20:57:08 +02001120{
Tvrtko Ursulin08537232016-10-13 11:03:02 +01001121 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
Damien Lespiau22606a12014-12-12 14:26:57 +00001122
Tvrtko Ursulin08537232016-10-13 11:03:02 +01001123 if (INTEL_GEN(dev_priv) <= 8)
Damien Lespiau22606a12014-12-12 14:26:57 +00001124 hsw_ddi_clock_get(encoder, pipe_config);
Rodrigo Vivib976dc52017-01-23 10:32:37 -08001125 else if (IS_GEN9_BC(dev_priv))
Damien Lespiau22606a12014-12-12 14:26:57 +00001126 skl_ddi_clock_get(encoder, pipe_config);
Ander Conselvan de Oliveiracc3f90f2016-12-02 10:23:49 +02001127 else if (IS_GEN9_LP(dev_priv))
Satheeshakrishna M977bb382014-08-22 09:49:12 +05301128 bxt_ddi_clock_get(encoder, pipe_config);
Daniel Vetter3d51278a2014-07-29 20:57:08 +02001129}
1130
Damien Lespiau0220ab62014-07-29 18:06:22 +01001131static bool
Damien Lespiaud664c0c2014-07-29 18:06:23 +01001132hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02001133 struct intel_crtc_state *crtc_state,
Ville Syrjälä96f3f1f2015-07-06 15:10:02 +03001134 struct intel_encoder *intel_encoder)
Paulo Zanoni6441ab52012-10-05 12:05:58 -03001135{
Ander Conselvan de Oliveiradaedf202016-03-08 17:46:23 +02001136 struct intel_shared_dpll *pll;
Ville Syrjälä96f3f1f2015-07-06 15:10:02 +03001137
Ander Conselvan de Oliveira9d16da62016-03-08 17:46:26 +02001138 pll = intel_get_shared_dpll(intel_crtc, crtc_state,
1139 intel_encoder);
1140 if (!pll)
1141 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1142 pipe_name(intel_crtc->pipe));
1143
1144 return pll;
Paulo Zanoni6441ab52012-10-05 12:05:58 -03001145}
1146
Satheeshakrishna M82d35432014-11-13 14:55:20 +00001147static bool
1148skl_ddi_pll_select(struct intel_crtc *intel_crtc,
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02001149 struct intel_crtc_state *crtc_state,
Ville Syrjälä96f3f1f2015-07-06 15:10:02 +03001150 struct intel_encoder *intel_encoder)
Satheeshakrishna M82d35432014-11-13 14:55:20 +00001151{
1152 struct intel_shared_dpll *pll;
Satheeshakrishna M82d35432014-11-13 14:55:20 +00001153
Ander Conselvan de Oliveiradaedf202016-03-08 17:46:23 +02001154 pll = intel_get_shared_dpll(intel_crtc, crtc_state, intel_encoder);
Satheeshakrishna M82d35432014-11-13 14:55:20 +00001155 if (pll == NULL) {
1156 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1157 pipe_name(intel_crtc->pipe));
1158 return false;
1159 }
1160
Satheeshakrishna M82d35432014-11-13 14:55:20 +00001161 return true;
1162}
Damien Lespiau0220ab62014-07-29 18:06:22 +01001163
Satheeshakrishna Md683f3b2014-08-22 09:49:08 +05301164static bool
1165bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
1166 struct intel_crtc_state *crtc_state,
Ville Syrjälä96f3f1f2015-07-06 15:10:02 +03001167 struct intel_encoder *intel_encoder)
Satheeshakrishna Md683f3b2014-08-22 09:49:08 +05301168{
Ander Conselvan de Oliveira34177c22016-03-08 17:46:25 +02001169 return !!intel_get_shared_dpll(intel_crtc, crtc_state, intel_encoder);
Satheeshakrishna Md683f3b2014-08-22 09:49:08 +05301170}
1171
Damien Lespiau0220ab62014-07-29 18:06:22 +01001172/*
1173 * Tries to find a *shared* PLL for the CRTC and store it in
1174 * intel_crtc->ddi_pll_sel.
1175 *
1176 * For private DPLLs, compute_config() should do the selection for us. This
1177 * function should be folded into compute_config() eventually.
1178 */
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02001179bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
1180 struct intel_crtc_state *crtc_state)
Damien Lespiau0220ab62014-07-29 18:06:22 +01001181{
Tvrtko Ursulin08537232016-10-13 11:03:02 +01001182 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02001183 struct intel_encoder *intel_encoder =
Ander Conselvan de Oliveira3165c072015-03-20 16:18:12 +02001184 intel_ddi_get_crtc_new_encoder(crtc_state);
Damien Lespiau0220ab62014-07-29 18:06:22 +01001185
Rodrigo Vivib976dc52017-01-23 10:32:37 -08001186 if (IS_GEN9_BC(dev_priv))
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02001187 return skl_ddi_pll_select(intel_crtc, crtc_state,
Ville Syrjälä96f3f1f2015-07-06 15:10:02 +03001188 intel_encoder);
Ander Conselvan de Oliveiracc3f90f2016-12-02 10:23:49 +02001189 else if (IS_GEN9_LP(dev_priv))
Satheeshakrishna Md683f3b2014-08-22 09:49:08 +05301190 return bxt_ddi_pll_select(intel_crtc, crtc_state,
Ville Syrjälä96f3f1f2015-07-06 15:10:02 +03001191 intel_encoder);
Satheeshakrishna M82d35432014-11-13 14:55:20 +00001192 else
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02001193 return hsw_ddi_pll_select(intel_crtc, crtc_state,
Ville Syrjälä96f3f1f2015-07-06 15:10:02 +03001194 intel_encoder);
Damien Lespiau0220ab62014-07-29 18:06:22 +01001195}
1196
Paulo Zanonidae84792012-10-15 15:51:30 -03001197void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
1198{
Chris Wilsonfac5e232016-07-04 11:34:36 +01001199 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
Paulo Zanonidae84792012-10-15 15:51:30 -03001200 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1201 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001202 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
Paulo Zanonidae84792012-10-15 15:51:30 -03001203 int type = intel_encoder->type;
1204 uint32_t temp;
1205
Ville Syrjäläcca05022016-06-22 21:57:06 +03001206 if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
Jani Nikula4d1de972016-03-18 17:05:42 +02001207 WARN_ON(transcoder_is_dsi(cpu_transcoder));
1208
Paulo Zanonic9809792012-10-23 18:30:00 -02001209 temp = TRANS_MSA_SYNC_CLK;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001210 switch (intel_crtc->config->pipe_bpp) {
Paulo Zanonidae84792012-10-15 15:51:30 -03001211 case 18:
Paulo Zanonic9809792012-10-23 18:30:00 -02001212 temp |= TRANS_MSA_6_BPC;
Paulo Zanonidae84792012-10-15 15:51:30 -03001213 break;
1214 case 24:
Paulo Zanonic9809792012-10-23 18:30:00 -02001215 temp |= TRANS_MSA_8_BPC;
Paulo Zanonidae84792012-10-15 15:51:30 -03001216 break;
1217 case 30:
Paulo Zanonic9809792012-10-23 18:30:00 -02001218 temp |= TRANS_MSA_10_BPC;
Paulo Zanonidae84792012-10-15 15:51:30 -03001219 break;
1220 case 36:
Paulo Zanonic9809792012-10-23 18:30:00 -02001221 temp |= TRANS_MSA_12_BPC;
Paulo Zanonidae84792012-10-15 15:51:30 -03001222 break;
1223 default:
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01001224 BUG();
Paulo Zanonidae84792012-10-15 15:51:30 -03001225 }
Paulo Zanonic9809792012-10-23 18:30:00 -02001226 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
Paulo Zanonidae84792012-10-15 15:51:30 -03001227 }
1228}
1229
Dave Airlie0e32b392014-05-02 14:02:48 +10001230void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
1231{
1232 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1233 struct drm_device *dev = crtc->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01001234 struct drm_i915_private *dev_priv = to_i915(dev);
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001235 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
Dave Airlie0e32b392014-05-02 14:02:48 +10001236 uint32_t temp;
1237 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1238 if (state == true)
1239 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1240 else
1241 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1242 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1243}
1244
Damien Lespiau8228c252013-03-07 15:30:27 +00001245void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
Paulo Zanoni8d9ddbc2012-10-05 12:05:53 -03001246{
1247 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1248 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
Paulo Zanonic7670b12013-11-02 21:07:37 -07001249 struct drm_device *dev = crtc->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01001250 struct drm_i915_private *dev_priv = to_i915(dev);
Paulo Zanoni8d9ddbc2012-10-05 12:05:53 -03001251 enum pipe pipe = intel_crtc->pipe;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001252 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
Paulo Zanoni174edf12012-10-26 19:05:50 -02001253 enum port port = intel_ddi_get_encoder_port(intel_encoder);
Paulo Zanoni7739c332012-10-15 15:51:29 -03001254 int type = intel_encoder->type;
Paulo Zanoni8d9ddbc2012-10-05 12:05:53 -03001255 uint32_t temp;
1256
Paulo Zanoniad80a812012-10-24 16:06:19 -02001257 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1258 temp = TRANS_DDI_FUNC_ENABLE;
Paulo Zanoni174edf12012-10-26 19:05:50 -02001259 temp |= TRANS_DDI_SELECT_PORT(port);
Paulo Zanonidfcef252012-08-08 14:15:29 -03001260
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001261 switch (intel_crtc->config->pipe_bpp) {
Paulo Zanonidfcef252012-08-08 14:15:29 -03001262 case 18:
Paulo Zanoniad80a812012-10-24 16:06:19 -02001263 temp |= TRANS_DDI_BPC_6;
Paulo Zanonidfcef252012-08-08 14:15:29 -03001264 break;
1265 case 24:
Paulo Zanoniad80a812012-10-24 16:06:19 -02001266 temp |= TRANS_DDI_BPC_8;
Paulo Zanonidfcef252012-08-08 14:15:29 -03001267 break;
1268 case 30:
Paulo Zanoniad80a812012-10-24 16:06:19 -02001269 temp |= TRANS_DDI_BPC_10;
Paulo Zanonidfcef252012-08-08 14:15:29 -03001270 break;
1271 case 36:
Paulo Zanoniad80a812012-10-24 16:06:19 -02001272 temp |= TRANS_DDI_BPC_12;
Paulo Zanonidfcef252012-08-08 14:15:29 -03001273 break;
1274 default:
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01001275 BUG();
Paulo Zanonidfcef252012-08-08 14:15:29 -03001276 }
Eugeni Dodonov72662e12012-05-09 15:37:31 -03001277
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001278 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
Paulo Zanoniad80a812012-10-24 16:06:19 -02001279 temp |= TRANS_DDI_PVSYNC;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001280 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
Paulo Zanoniad80a812012-10-24 16:06:19 -02001281 temp |= TRANS_DDI_PHSYNC;
Paulo Zanonif63eb7c42012-08-08 14:15:28 -03001282
Paulo Zanonie6f0bfc2012-10-23 18:30:04 -02001283 if (cpu_transcoder == TRANSCODER_EDP) {
1284 switch (pipe) {
1285 case PIPE_A:
Paulo Zanonic7670b12013-11-02 21:07:37 -07001286 /* On Haswell, can only use the always-on power well for
1287 * eDP when not using the panel fitter, and when not
1288 * using motion blur mitigation (which we don't
1289 * support). */
Tvrtko Ursulin772c2a52016-10-13 11:03:01 +01001290 if (IS_HASWELL(dev_priv) &&
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001291 (intel_crtc->config->pch_pfit.enabled ||
1292 intel_crtc->config->pch_pfit.force_thru))
Daniel Vetterd6dd9eb2013-01-29 16:35:20 -02001293 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1294 else
1295 temp |= TRANS_DDI_EDP_INPUT_A_ON;
Paulo Zanonie6f0bfc2012-10-23 18:30:04 -02001296 break;
1297 case PIPE_B:
1298 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1299 break;
1300 case PIPE_C:
1301 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1302 break;
1303 default:
1304 BUG();
1305 break;
1306 }
1307 }
1308
Paulo Zanoni7739c332012-10-15 15:51:29 -03001309 if (type == INTEL_OUTPUT_HDMI) {
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001310 if (intel_crtc->config->has_hdmi_sink)
Paulo Zanoniad80a812012-10-24 16:06:19 -02001311 temp |= TRANS_DDI_MODE_SELECT_HDMI;
Paulo Zanoni8d9ddbc2012-10-05 12:05:53 -03001312 else
Paulo Zanoniad80a812012-10-24 16:06:19 -02001313 temp |= TRANS_DDI_MODE_SELECT_DVI;
Paulo Zanoni7739c332012-10-15 15:51:29 -03001314 } else if (type == INTEL_OUTPUT_ANALOG) {
Paulo Zanoniad80a812012-10-24 16:06:19 -02001315 temp |= TRANS_DDI_MODE_SELECT_FDI;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001316 temp |= (intel_crtc->config->fdi_lanes - 1) << 1;
Ville Syrjäläcca05022016-06-22 21:57:06 +03001317 } else if (type == INTEL_OUTPUT_DP ||
Paulo Zanoni7739c332012-10-15 15:51:29 -03001318 type == INTEL_OUTPUT_EDP) {
Ville Syrjälä64ee2fd2016-07-28 17:50:39 +03001319 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
Ville Syrjälä90a6b7b2015-07-06 16:39:15 +03001320 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
Dave Airlie0e32b392014-05-02 14:02:48 +10001321 } else if (type == INTEL_OUTPUT_DP_MST) {
Ville Syrjälä64ee2fd2016-07-28 17:50:39 +03001322 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
Ville Syrjälä90a6b7b2015-07-06 16:39:15 +03001323 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
Paulo Zanoni8d9ddbc2012-10-05 12:05:53 -03001324 } else {
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03001325 WARN(1, "Invalid encoder type %d for pipe %c\n",
1326 intel_encoder->type, pipe_name(pipe));
Paulo Zanoni8d9ddbc2012-10-05 12:05:53 -03001327 }
1328
Paulo Zanoniad80a812012-10-24 16:06:19 -02001329 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
Paulo Zanoni8d9ddbc2012-10-05 12:05:53 -03001330}
1331
Paulo Zanoniad80a812012-10-24 16:06:19 -02001332void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1333 enum transcoder cpu_transcoder)
Paulo Zanoni8d9ddbc2012-10-05 12:05:53 -03001334{
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001335 i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
Paulo Zanoni8d9ddbc2012-10-05 12:05:53 -03001336 uint32_t val = I915_READ(reg);
1337
Dave Airlie0e32b392014-05-02 14:02:48 +10001338 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
Paulo Zanoniad80a812012-10-24 16:06:19 -02001339 val |= TRANS_DDI_PORT_NONE;
Paulo Zanoni8d9ddbc2012-10-05 12:05:53 -03001340 I915_WRITE(reg, val);
Eugeni Dodonov72662e12012-05-09 15:37:31 -03001341}
1342
Paulo Zanonibcbc8892012-10-26 19:05:51 -02001343bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1344{
1345 struct drm_device *dev = intel_connector->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01001346 struct drm_i915_private *dev_priv = to_i915(dev);
Paulo Zanonibcbc8892012-10-26 19:05:51 -02001347 struct intel_encoder *intel_encoder = intel_connector->encoder;
1348 int type = intel_connector->base.connector_type;
1349 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1350 enum pipe pipe = 0;
1351 enum transcoder cpu_transcoder;
1352 uint32_t tmp;
Imre Deake27daab2016-02-12 18:55:16 +02001353 bool ret;
Paulo Zanonibcbc8892012-10-26 19:05:51 -02001354
Ander Conselvan de Oliveira79f255a2017-02-22 08:34:27 +02001355 if (!intel_display_power_get_if_enabled(dev_priv,
1356 intel_encoder->power_domain))
Paulo Zanoni882244a2014-04-01 14:55:12 -03001357 return false;
1358
Imre Deake27daab2016-02-12 18:55:16 +02001359 if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) {
1360 ret = false;
1361 goto out;
1362 }
Paulo Zanonibcbc8892012-10-26 19:05:51 -02001363
1364 if (port == PORT_A)
1365 cpu_transcoder = TRANSCODER_EDP;
1366 else
Daniel Vetter1a240d42012-11-29 22:18:51 +01001367 cpu_transcoder = (enum transcoder) pipe;
Paulo Zanonibcbc8892012-10-26 19:05:51 -02001368
1369 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1370
1371 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1372 case TRANS_DDI_MODE_SELECT_HDMI:
1373 case TRANS_DDI_MODE_SELECT_DVI:
Imre Deake27daab2016-02-12 18:55:16 +02001374 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1375 break;
Paulo Zanonibcbc8892012-10-26 19:05:51 -02001376
1377 case TRANS_DDI_MODE_SELECT_DP_SST:
Imre Deake27daab2016-02-12 18:55:16 +02001378 ret = type == DRM_MODE_CONNECTOR_eDP ||
1379 type == DRM_MODE_CONNECTOR_DisplayPort;
1380 break;
1381
Dave Airlie0e32b392014-05-02 14:02:48 +10001382 case TRANS_DDI_MODE_SELECT_DP_MST:
1383 /* if the transcoder is in MST state then
1384 * connector isn't connected */
Imre Deake27daab2016-02-12 18:55:16 +02001385 ret = false;
1386 break;
Paulo Zanonibcbc8892012-10-26 19:05:51 -02001387
1388 case TRANS_DDI_MODE_SELECT_FDI:
Imre Deake27daab2016-02-12 18:55:16 +02001389 ret = type == DRM_MODE_CONNECTOR_VGA;
1390 break;
Paulo Zanonibcbc8892012-10-26 19:05:51 -02001391
1392 default:
Imre Deake27daab2016-02-12 18:55:16 +02001393 ret = false;
1394 break;
Paulo Zanonibcbc8892012-10-26 19:05:51 -02001395 }
Imre Deake27daab2016-02-12 18:55:16 +02001396
1397out:
Ander Conselvan de Oliveira79f255a2017-02-22 08:34:27 +02001398 intel_display_power_put(dev_priv, intel_encoder->power_domain);
Imre Deake27daab2016-02-12 18:55:16 +02001399
1400 return ret;
Paulo Zanonibcbc8892012-10-26 19:05:51 -02001401}
1402
Daniel Vetter85234cd2012-07-02 13:27:29 +02001403bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1404 enum pipe *pipe)
1405{
1406 struct drm_device *dev = encoder->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01001407 struct drm_i915_private *dev_priv = to_i915(dev);
Paulo Zanonife43d3f2012-10-15 15:51:39 -03001408 enum port port = intel_ddi_get_encoder_port(encoder);
Daniel Vetter85234cd2012-07-02 13:27:29 +02001409 u32 tmp;
1410 int i;
Imre Deake27daab2016-02-12 18:55:16 +02001411 bool ret;
Daniel Vetter85234cd2012-07-02 13:27:29 +02001412
Ander Conselvan de Oliveira79f255a2017-02-22 08:34:27 +02001413 if (!intel_display_power_get_if_enabled(dev_priv,
1414 encoder->power_domain))
Imre Deak6d129be2014-03-05 16:20:54 +02001415 return false;
1416
Imre Deake27daab2016-02-12 18:55:16 +02001417 ret = false;
1418
Paulo Zanonife43d3f2012-10-15 15:51:39 -03001419 tmp = I915_READ(DDI_BUF_CTL(port));
Daniel Vetter85234cd2012-07-02 13:27:29 +02001420
1421 if (!(tmp & DDI_BUF_CTL_ENABLE))
Imre Deake27daab2016-02-12 18:55:16 +02001422 goto out;
Daniel Vetter85234cd2012-07-02 13:27:29 +02001423
Paulo Zanoniad80a812012-10-24 16:06:19 -02001424 if (port == PORT_A) {
1425 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
Daniel Vetter85234cd2012-07-02 13:27:29 +02001426
Paulo Zanoniad80a812012-10-24 16:06:19 -02001427 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1428 case TRANS_DDI_EDP_INPUT_A_ON:
1429 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1430 *pipe = PIPE_A;
1431 break;
1432 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1433 *pipe = PIPE_B;
1434 break;
1435 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1436 *pipe = PIPE_C;
1437 break;
1438 }
1439
Imre Deake27daab2016-02-12 18:55:16 +02001440 ret = true;
Paulo Zanoniad80a812012-10-24 16:06:19 -02001441
Imre Deake27daab2016-02-12 18:55:16 +02001442 goto out;
1443 }
Dave Airlie0e32b392014-05-02 14:02:48 +10001444
Imre Deake27daab2016-02-12 18:55:16 +02001445 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1446 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1447
1448 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) {
1449 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
1450 TRANS_DDI_MODE_SELECT_DP_MST)
1451 goto out;
1452
1453 *pipe = i;
1454 ret = true;
1455
1456 goto out;
Daniel Vetter85234cd2012-07-02 13:27:29 +02001457 }
1458 }
1459
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03001460 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
Daniel Vetter85234cd2012-07-02 13:27:29 +02001461
Imre Deake27daab2016-02-12 18:55:16 +02001462out:
Ander Conselvan de Oliveiracc3f90f2016-12-02 10:23:49 +02001463 if (ret && IS_GEN9_LP(dev_priv)) {
Imre Deake93da0a2016-06-13 16:44:37 +03001464 tmp = I915_READ(BXT_PHY_CTL(port));
1465 if ((tmp & (BXT_PHY_LANE_POWERDOWN_ACK |
1466 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
1467 DRM_ERROR("Port %c enabled but PHY powered down? "
1468 "(PHY_CTL %08x)\n", port_name(port), tmp);
1469 }
1470
Ander Conselvan de Oliveira79f255a2017-02-22 08:34:27 +02001471 intel_display_power_put(dev_priv, encoder->power_domain);
Imre Deake27daab2016-02-12 18:55:16 +02001472
1473 return ret;
Daniel Vetter85234cd2012-07-02 13:27:29 +02001474}
1475
Ander Conselvan de Oliveira62b69562017-02-24 16:19:59 +02001476static u64 intel_ddi_get_power_domains(struct intel_encoder *encoder)
1477{
1478 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
1479 enum pipe pipe;
1480
1481 if (intel_ddi_get_hw_state(encoder, &pipe))
1482 return BIT_ULL(dig_port->ddi_io_power_domain);
1483
1484 return 0;
1485}
1486
Paulo Zanonifc914632012-10-05 12:05:54 -03001487void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1488{
1489 struct drm_crtc *crtc = &intel_crtc->base;
Shashank Sharma7d4aefd2015-10-01 22:23:49 +05301490 struct drm_device *dev = crtc->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01001491 struct drm_i915_private *dev_priv = to_i915(dev);
Paulo Zanonifc914632012-10-05 12:05:54 -03001492 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1493 enum port port = intel_ddi_get_encoder_port(intel_encoder);
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001494 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
Paulo Zanonifc914632012-10-05 12:05:54 -03001495
Paulo Zanonibb523fc2012-10-23 18:29:56 -02001496 if (cpu_transcoder != TRANSCODER_EDP)
1497 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1498 TRANS_CLK_SEL_PORT(port));
Paulo Zanonifc914632012-10-05 12:05:54 -03001499}
1500
1501void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1502{
Chris Wilsonfac5e232016-07-04 11:34:36 +01001503 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001504 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
Paulo Zanonifc914632012-10-05 12:05:54 -03001505
Paulo Zanonibb523fc2012-10-23 18:29:56 -02001506 if (cpu_transcoder != TRANSCODER_EDP)
1507 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1508 TRANS_CLK_SEL_DISABLED);
Paulo Zanonifc914632012-10-05 12:05:54 -03001509}
1510
Ville Syrjäläa7d8dbc2016-07-12 15:59:28 +03001511static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
1512 enum port port, uint8_t iboost)
David Weinehallf8896f52015-06-25 11:11:03 +03001513{
Ville Syrjäläa7d8dbc2016-07-12 15:59:28 +03001514 u32 tmp;
1515
1516 tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
1517 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
1518 if (iboost)
1519 tmp |= iboost << BALANCE_LEG_SHIFT(port);
1520 else
1521 tmp |= BALANCE_LEG_DISABLE(port);
1522 I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
1523}
1524
1525static void skl_ddi_set_iboost(struct intel_encoder *encoder, u32 level)
1526{
1527 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
1528 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
1529 enum port port = intel_dig_port->port;
1530 int type = encoder->type;
David Weinehallf8896f52015-06-25 11:11:03 +03001531 const struct ddi_buf_trans *ddi_translations;
1532 uint8_t iboost;
Antti Koskipaa75067dd2015-07-10 14:10:55 +03001533 uint8_t dp_iboost, hdmi_iboost;
David Weinehallf8896f52015-06-25 11:11:03 +03001534 int n_entries;
David Weinehallf8896f52015-06-25 11:11:03 +03001535
Antti Koskipaa75067dd2015-07-10 14:10:55 +03001536 /* VBT may override standard boost values */
1537 dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
1538 hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
1539
Ville Syrjäläcca05022016-06-22 21:57:06 +03001540 if (type == INTEL_OUTPUT_DP) {
Antti Koskipaa75067dd2015-07-10 14:10:55 +03001541 if (dp_iboost) {
1542 iboost = dp_iboost;
1543 } else {
Rodrigo Vivi0fdd4912016-10-18 08:57:36 -07001544 if (IS_KABYLAKE(dev_priv))
1545 ddi_translations = kbl_get_buf_trans_dp(dev_priv,
1546 &n_entries);
1547 else
1548 ddi_translations = skl_get_buf_trans_dp(dev_priv,
1549 &n_entries);
Ander Conselvan de Oliveirae4d4c052015-11-11 15:15:54 +02001550 iboost = ddi_translations[level].i_boost;
Antti Koskipaa75067dd2015-07-10 14:10:55 +03001551 }
David Weinehallf8896f52015-06-25 11:11:03 +03001552 } else if (type == INTEL_OUTPUT_EDP) {
Antti Koskipaa75067dd2015-07-10 14:10:55 +03001553 if (dp_iboost) {
1554 iboost = dp_iboost;
1555 } else {
Ville Syrjälä78ab0ba2015-12-08 19:59:41 +02001556 ddi_translations = skl_get_buf_trans_edp(dev_priv, &n_entries);
Ville Syrjälä10afa0b2015-12-08 19:59:43 +02001557
1558 if (WARN_ON(port != PORT_A &&
1559 port != PORT_E && n_entries > 9))
1560 n_entries = 9;
1561
Ander Conselvan de Oliveirae4d4c052015-11-11 15:15:54 +02001562 iboost = ddi_translations[level].i_boost;
Antti Koskipaa75067dd2015-07-10 14:10:55 +03001563 }
David Weinehallf8896f52015-06-25 11:11:03 +03001564 } else if (type == INTEL_OUTPUT_HDMI) {
Antti Koskipaa75067dd2015-07-10 14:10:55 +03001565 if (hdmi_iboost) {
1566 iboost = hdmi_iboost;
1567 } else {
Ville Syrjälä78ab0ba2015-12-08 19:59:41 +02001568 ddi_translations = skl_get_buf_trans_hdmi(dev_priv, &n_entries);
Ander Conselvan de Oliveirae4d4c052015-11-11 15:15:54 +02001569 iboost = ddi_translations[level].i_boost;
Antti Koskipaa75067dd2015-07-10 14:10:55 +03001570 }
David Weinehallf8896f52015-06-25 11:11:03 +03001571 } else {
1572 return;
1573 }
1574
1575 /* Make sure that the requested I_boost is valid */
1576 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
1577 DRM_ERROR("Invalid I_boost value %u\n", iboost);
1578 return;
1579 }
1580
Ville Syrjäläa7d8dbc2016-07-12 15:59:28 +03001581 _skl_ddi_set_iboost(dev_priv, port, iboost);
David Weinehallf8896f52015-06-25 11:11:03 +03001582
Ville Syrjäläa7d8dbc2016-07-12 15:59:28 +03001583 if (port == PORT_A && intel_dig_port->max_lanes == 4)
1584 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
David Weinehallf8896f52015-06-25 11:11:03 +03001585}
1586
Ville Syrjälä78ab0ba2015-12-08 19:59:41 +02001587static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
1588 u32 level, enum port port, int type)
Vandana Kannan96fb9f92014-11-18 15:45:27 +05301589{
Vandana Kannan96fb9f92014-11-18 15:45:27 +05301590 const struct bxt_ddi_buf_trans *ddi_translations;
1591 u32 n_entries, i;
Vandana Kannan96fb9f92014-11-18 15:45:27 +05301592
Jani Nikula06411f02016-03-24 17:50:21 +02001593 if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
Sonika Jindald9d70002015-09-24 10:24:56 +05301594 n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
1595 ddi_translations = bxt_ddi_translations_edp;
Ville Syrjäläcca05022016-06-22 21:57:06 +03001596 } else if (type == INTEL_OUTPUT_DP
Sonika Jindald9d70002015-09-24 10:24:56 +05301597 || type == INTEL_OUTPUT_EDP) {
Vandana Kannan96fb9f92014-11-18 15:45:27 +05301598 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
1599 ddi_translations = bxt_ddi_translations_dp;
1600 } else if (type == INTEL_OUTPUT_HDMI) {
1601 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
1602 ddi_translations = bxt_ddi_translations_hdmi;
1603 } else {
1604 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
1605 type);
1606 return;
1607 }
1608
1609 /* Check if default value has to be used */
1610 if (level >= n_entries ||
1611 (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
1612 for (i = 0; i < n_entries; i++) {
1613 if (ddi_translations[i].default_index) {
1614 level = i;
1615 break;
1616 }
1617 }
1618 }
1619
Ander Conselvan de Oliveirab6e08202016-10-06 19:22:19 +03001620 bxt_ddi_phy_set_signal_level(dev_priv, port,
1621 ddi_translations[level].margin,
1622 ddi_translations[level].scale,
1623 ddi_translations[level].enable,
1624 ddi_translations[level].deemphasis);
Vandana Kannan96fb9f92014-11-18 15:45:27 +05301625}
1626
Ville Syrjäläffe51112017-02-23 19:49:01 +02001627u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
1628{
1629 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1630 int n_entries;
1631
1632 if (encoder->type == INTEL_OUTPUT_EDP)
1633 intel_ddi_get_buf_trans_edp(dev_priv, &n_entries);
1634 else
1635 intel_ddi_get_buf_trans_dp(dev_priv, &n_entries);
1636
1637 if (WARN_ON(n_entries < 1))
1638 n_entries = 1;
1639 if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
1640 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
1641
1642 return index_to_dp_signal_levels[n_entries - 1] &
1643 DP_TRAIN_VOLTAGE_SWING_MASK;
1644}
1645
David Weinehallf8896f52015-06-25 11:11:03 +03001646static uint32_t translate_signal_level(int signal_levels)
1647{
Ville Syrjälä97eeb872017-02-23 19:35:06 +02001648 int i;
David Weinehallf8896f52015-06-25 11:11:03 +03001649
Ville Syrjälä97eeb872017-02-23 19:35:06 +02001650 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
1651 if (index_to_dp_signal_levels[i] == signal_levels)
1652 return i;
David Weinehallf8896f52015-06-25 11:11:03 +03001653 }
1654
Ville Syrjälä97eeb872017-02-23 19:35:06 +02001655 WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
1656 signal_levels);
1657
1658 return 0;
David Weinehallf8896f52015-06-25 11:11:03 +03001659}
1660
1661uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
1662{
1663 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
Ville Syrjälä78ab0ba2015-12-08 19:59:41 +02001664 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
David Weinehallf8896f52015-06-25 11:11:03 +03001665 struct intel_encoder *encoder = &dport->base;
1666 uint8_t train_set = intel_dp->train_set[0];
1667 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1668 DP_TRAIN_PRE_EMPHASIS_MASK);
1669 enum port port = dport->port;
1670 uint32_t level;
1671
1672 level = translate_signal_level(signal_levels);
1673
Rodrigo Vivib976dc52017-01-23 10:32:37 -08001674 if (IS_GEN9_BC(dev_priv))
Ville Syrjäläa7d8dbc2016-07-12 15:59:28 +03001675 skl_ddi_set_iboost(encoder, level);
Ander Conselvan de Oliveiracc3f90f2016-12-02 10:23:49 +02001676 else if (IS_GEN9_LP(dev_priv))
Ville Syrjälä78ab0ba2015-12-08 19:59:41 +02001677 bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
David Weinehallf8896f52015-06-25 11:11:03 +03001678
1679 return DDI_BUF_TRANS_SELECT(level);
1680}
1681
Ville Syrjäläe404ba8d2015-08-17 18:46:20 +03001682void intel_ddi_clk_select(struct intel_encoder *encoder,
Ander Conselvan de Oliveirac8560522016-09-01 15:08:07 -07001683 struct intel_shared_dpll *pll)
Paulo Zanoni6441ab52012-10-05 12:05:58 -03001684{
Ville Syrjäläe404ba8d2015-08-17 18:46:20 +03001685 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1686 enum port port = intel_ddi_get_encoder_port(encoder);
Paulo Zanoni82a4d9c2012-10-23 18:30:07 -02001687
Ander Conselvan de Oliveirac8560522016-09-01 15:08:07 -07001688 if (WARN_ON(!pll))
1689 return;
1690
Rodrigo Vivib976dc52017-01-23 10:32:37 -08001691 if (IS_GEN9_BC(dev_priv)) {
Satheeshakrishna Mefa80ad2014-11-13 14:55:19 +00001692 uint32_t val;
1693
Damien Lespiau5416d872014-11-14 17:24:33 +00001694 /* DDI -> PLL mapping */
Satheeshakrishna Mefa80ad2014-11-13 14:55:19 +00001695 val = I915_READ(DPLL_CTRL2);
1696
1697 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
1698 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
Ander Conselvan de Oliveirac8560522016-09-01 15:08:07 -07001699 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->id, port) |
Satheeshakrishna Mefa80ad2014-11-13 14:55:19 +00001700 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
1701
1702 I915_WRITE(DPLL_CTRL2, val);
Damien Lespiau5416d872014-11-14 17:24:33 +00001703
Ville Syrjäläe404ba8d2015-08-17 18:46:20 +03001704 } else if (INTEL_INFO(dev_priv)->gen < 9) {
Ander Conselvan de Oliveirac8560522016-09-01 15:08:07 -07001705 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
Satheeshakrishna Mefa80ad2014-11-13 14:55:19 +00001706 }
Ville Syrjäläe404ba8d2015-08-17 18:46:20 +03001707}
1708
Manasi Navareba88d152016-09-01 15:08:08 -07001709static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
1710 int link_rate, uint32_t lane_count,
1711 struct intel_shared_dpll *pll,
1712 bool link_mst)
1713{
1714 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1715 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1716 enum port port = intel_ddi_get_encoder_port(encoder);
Ander Conselvan de Oliveira62b69562017-02-24 16:19:59 +02001717 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
Manasi Navareba88d152016-09-01 15:08:08 -07001718
1719 intel_dp_set_link_params(intel_dp, link_rate, lane_count,
1720 link_mst);
1721 if (encoder->type == INTEL_OUTPUT_EDP)
1722 intel_edp_panel_on(intel_dp);
1723
1724 intel_ddi_clk_select(encoder, pll);
Ander Conselvan de Oliveira62b69562017-02-24 16:19:59 +02001725
1726 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
1727
Manasi Navareba88d152016-09-01 15:08:08 -07001728 intel_prepare_dp_ddi_buffers(encoder);
1729 intel_ddi_init_dp_buf_reg(encoder);
1730 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1731 intel_dp_start_link_train(intel_dp);
1732 if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
1733 intel_dp_stop_link_train(intel_dp);
1734}
1735
1736static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
1737 bool has_hdmi_sink,
Maarten Lankhorstac240282016-11-23 15:57:00 +01001738 const struct intel_crtc_state *crtc_state,
1739 const struct drm_connector_state *conn_state,
Manasi Navareba88d152016-09-01 15:08:08 -07001740 struct intel_shared_dpll *pll)
1741{
1742 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1743 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1744 struct drm_encoder *drm_encoder = &encoder->base;
1745 enum port port = intel_ddi_get_encoder_port(encoder);
1746 int level = intel_ddi_hdmi_level(dev_priv, port);
Ander Conselvan de Oliveira62b69562017-02-24 16:19:59 +02001747 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
Manasi Navareba88d152016-09-01 15:08:08 -07001748
1749 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
1750 intel_ddi_clk_select(encoder, pll);
Ander Conselvan de Oliveira62b69562017-02-24 16:19:59 +02001751
1752 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
1753
Manasi Navareba88d152016-09-01 15:08:08 -07001754 intel_prepare_hdmi_ddi_buffers(encoder);
Rodrigo Vivib976dc52017-01-23 10:32:37 -08001755 if (IS_GEN9_BC(dev_priv))
Manasi Navareba88d152016-09-01 15:08:08 -07001756 skl_ddi_set_iboost(encoder, level);
Ander Conselvan de Oliveiracc3f90f2016-12-02 10:23:49 +02001757 else if (IS_GEN9_LP(dev_priv))
Manasi Navareba88d152016-09-01 15:08:08 -07001758 bxt_ddi_vswing_sequence(dev_priv, level, port,
1759 INTEL_OUTPUT_HDMI);
1760
1761 intel_hdmi->set_infoframes(drm_encoder,
1762 has_hdmi_sink,
Maarten Lankhorstac240282016-11-23 15:57:00 +01001763 crtc_state, conn_state);
Manasi Navareba88d152016-09-01 15:08:08 -07001764}
1765
Maarten Lankhorstfd6bbda2016-08-09 17:04:04 +02001766static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder,
1767 struct intel_crtc_state *pipe_config,
1768 struct drm_connector_state *conn_state)
Ville Syrjäläe404ba8d2015-08-17 18:46:20 +03001769{
1770 struct drm_encoder *encoder = &intel_encoder->base;
Ville Syrjäläe404ba8d2015-08-17 18:46:20 +03001771 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
Ville Syrjäläe404ba8d2015-08-17 18:46:20 +03001772 int type = intel_encoder->type;
Ville Syrjälä6a7e4f92015-12-08 19:59:44 +02001773
Ville Syrjäläcca05022016-06-22 21:57:06 +03001774 if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
Manasi Navareba88d152016-09-01 15:08:08 -07001775 intel_ddi_pre_enable_dp(intel_encoder,
1776 crtc->config->port_clock,
1777 crtc->config->lane_count,
1778 crtc->config->shared_dpll,
1779 intel_crtc_has_type(crtc->config,
1780 INTEL_OUTPUT_DP_MST));
1781 }
1782 if (type == INTEL_OUTPUT_HDMI) {
1783 intel_ddi_pre_enable_hdmi(intel_encoder,
Maarten Lankhorstac240282016-11-23 15:57:00 +01001784 pipe_config->has_hdmi_sink,
1785 pipe_config, conn_state,
Manasi Navareba88d152016-09-01 15:08:08 -07001786 crtc->config->shared_dpll);
Paulo Zanonic19b0662012-10-15 15:51:41 -03001787 }
Paulo Zanoni6441ab52012-10-05 12:05:58 -03001788}
1789
Maarten Lankhorstfd6bbda2016-08-09 17:04:04 +02001790static void intel_ddi_post_disable(struct intel_encoder *intel_encoder,
1791 struct intel_crtc_state *old_crtc_state,
1792 struct drm_connector_state *old_conn_state)
Paulo Zanoni6441ab52012-10-05 12:05:58 -03001793{
1794 struct drm_encoder *encoder = &intel_encoder->base;
Tvrtko Ursulin66478472016-11-16 08:55:40 +00001795 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
Paulo Zanoni6441ab52012-10-05 12:05:58 -03001796 enum port port = intel_ddi_get_encoder_port(intel_encoder);
Ander Conselvan de Oliveira62b69562017-02-24 16:19:59 +02001797 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
Paulo Zanoni82a4d9c2012-10-23 18:30:07 -02001798 int type = intel_encoder->type;
Paulo Zanoni2886e932012-10-05 12:06:00 -03001799 uint32_t val;
Paulo Zanonia836bdf2012-10-15 15:51:32 -03001800 bool wait = false;
Paulo Zanoni2886e932012-10-05 12:06:00 -03001801
Maarten Lankhorstfd6bbda2016-08-09 17:04:04 +02001802 /* old_crtc_state and old_conn_state are NULL when called from DP_MST */
1803
Paulo Zanoni2886e932012-10-05 12:06:00 -03001804 val = I915_READ(DDI_BUF_CTL(port));
1805 if (val & DDI_BUF_CTL_ENABLE) {
1806 val &= ~DDI_BUF_CTL_ENABLE;
1807 I915_WRITE(DDI_BUF_CTL(port), val);
Paulo Zanonia836bdf2012-10-15 15:51:32 -03001808 wait = true;
Paulo Zanoni2886e932012-10-05 12:06:00 -03001809 }
Paulo Zanoni6441ab52012-10-05 12:05:58 -03001810
Paulo Zanonia836bdf2012-10-15 15:51:32 -03001811 val = I915_READ(DP_TP_CTL(port));
1812 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1813 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1814 I915_WRITE(DP_TP_CTL(port), val);
1815
1816 if (wait)
1817 intel_wait_ddi_buf_idle(dev_priv, port);
1818
Ville Syrjäläcca05022016-06-22 21:57:06 +03001819 if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
Paulo Zanoni82a4d9c2012-10-23 18:30:07 -02001820 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
Jani Nikula76bb80e2013-11-15 15:29:57 +02001821 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
Jani Nikula24f3e092014-03-17 16:43:36 +02001822 intel_edp_panel_vdd_on(intel_dp);
Daniel Vetter4be73782014-01-17 14:39:48 +01001823 intel_edp_panel_off(intel_dp);
Paulo Zanoni82a4d9c2012-10-23 18:30:07 -02001824 }
1825
Ander Conselvan de Oliveira62b69562017-02-24 16:19:59 +02001826 if (dig_port)
1827 intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
1828
Rodrigo Vivib976dc52017-01-23 10:32:37 -08001829 if (IS_GEN9_BC(dev_priv))
Satheeshakrishna Mefa80ad2014-11-13 14:55:19 +00001830 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
1831 DPLL_CTRL2_DDI_CLK_OFF(port)));
Tvrtko Ursulin66478472016-11-16 08:55:40 +00001832 else if (INTEL_GEN(dev_priv) < 9)
Satheeshakrishna Mefa80ad2014-11-13 14:55:19 +00001833 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
Ville Syrjäläb2ccb822016-05-02 22:08:24 +03001834
1835 if (type == INTEL_OUTPUT_HDMI) {
1836 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1837
1838 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
1839 }
Paulo Zanoni6441ab52012-10-05 12:05:58 -03001840}
1841
Maarten Lankhorstb7076542016-08-23 16:18:08 +02001842void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1843 struct intel_crtc_state *old_crtc_state,
1844 struct drm_connector_state *old_conn_state)
1845{
1846 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
1847 uint32_t val;
1848
1849 /*
1850 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
1851 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
1852 * step 13 is the correct place for it. Step 18 is where it was
1853 * originally before the BUN.
1854 */
1855 val = I915_READ(FDI_RX_CTL(PIPE_A));
1856 val &= ~FDI_RX_ENABLE;
1857 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
1858
1859 intel_ddi_post_disable(intel_encoder, old_crtc_state, old_conn_state);
1860
1861 val = I915_READ(FDI_RX_MISC(PIPE_A));
1862 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1863 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1864 I915_WRITE(FDI_RX_MISC(PIPE_A), val);
1865
1866 val = I915_READ(FDI_RX_CTL(PIPE_A));
1867 val &= ~FDI_PCDCLK;
1868 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
1869
1870 val = I915_READ(FDI_RX_CTL(PIPE_A));
1871 val &= ~FDI_RX_PLL_ENABLE;
1872 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
1873}
1874
Maarten Lankhorstfd6bbda2016-08-09 17:04:04 +02001875static void intel_enable_ddi(struct intel_encoder *intel_encoder,
1876 struct intel_crtc_state *pipe_config,
1877 struct drm_connector_state *conn_state)
Eugeni Dodonov72662e12012-05-09 15:37:31 -03001878{
Paulo Zanoni6547fef2012-10-15 15:51:40 -03001879 struct drm_encoder *encoder = &intel_encoder->base;
Tvrtko Ursulin66478472016-11-16 08:55:40 +00001880 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
Paulo Zanoni6547fef2012-10-15 15:51:40 -03001881 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1882 int type = intel_encoder->type;
Eugeni Dodonov72662e12012-05-09 15:37:31 -03001883
Paulo Zanoni6547fef2012-10-15 15:51:40 -03001884 if (type == INTEL_OUTPUT_HDMI) {
Damien Lespiau876a8cd2012-12-11 18:48:30 +00001885 struct intel_digital_port *intel_dig_port =
1886 enc_to_dig_port(encoder);
1887
Paulo Zanoni6547fef2012-10-15 15:51:40 -03001888 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1889 * are ignored so nothing special needs to be done besides
1890 * enabling the port.
1891 */
Damien Lespiau876a8cd2012-12-11 18:48:30 +00001892 I915_WRITE(DDI_BUF_CTL(port),
Stéphane Marchesinbcf53de2013-07-12 13:54:41 -07001893 intel_dig_port->saved_port_bits |
1894 DDI_BUF_CTL_ENABLE);
Paulo Zanonid6c50ff2012-10-23 18:30:06 -02001895 } else if (type == INTEL_OUTPUT_EDP) {
1896 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1897
Tvrtko Ursulin66478472016-11-16 08:55:40 +00001898 if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
Imre Deak3ab9c632013-05-03 12:57:41 +03001899 intel_dp_stop_link_train(intel_dp);
1900
Daniel Vetter4be73782014-01-17 14:39:48 +01001901 intel_edp_backlight_on(intel_dp);
Rodrigo Vivi0bc12bc2014-11-14 08:52:28 -08001902 intel_psr_enable(intel_dp);
Maarten Lankhorst85cb48a2016-08-09 17:04:13 +02001903 intel_edp_drrs_enable(intel_dp, pipe_config);
Paulo Zanoni6547fef2012-10-15 15:51:40 -03001904 }
Wang Xingchao7b9f35a2013-01-22 23:25:25 +08001905
Maarten Lankhorst37255d82016-12-15 15:29:43 +01001906 if (pipe_config->has_audio)
Maarten Lankhorstbbf35e92016-11-08 13:55:38 +01001907 intel_audio_codec_enable(intel_encoder, pipe_config, conn_state);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02001908}
1909
Maarten Lankhorstfd6bbda2016-08-09 17:04:04 +02001910static void intel_disable_ddi(struct intel_encoder *intel_encoder,
1911 struct intel_crtc_state *old_crtc_state,
1912 struct drm_connector_state *old_conn_state)
Daniel Vetter5ab432e2012-06-30 08:59:56 +02001913{
Paulo Zanonid6c50ff2012-10-23 18:30:06 -02001914 struct drm_encoder *encoder = &intel_encoder->base;
1915 int type = intel_encoder->type;
1916
Maarten Lankhorst37255d82016-12-15 15:29:43 +01001917 if (old_crtc_state->has_audio)
Jani Nikula69bfe1a2014-10-27 16:26:50 +02001918 intel_audio_codec_disable(intel_encoder);
Paulo Zanoni2831d8422013-03-06 20:03:09 -03001919
Paulo Zanonid6c50ff2012-10-23 18:30:06 -02001920 if (type == INTEL_OUTPUT_EDP) {
1921 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1922
Maarten Lankhorst85cb48a2016-08-09 17:04:13 +02001923 intel_edp_drrs_disable(intel_dp, old_crtc_state);
Rodrigo Vivi0bc12bc2014-11-14 08:52:28 -08001924 intel_psr_disable(intel_dp);
Daniel Vetter4be73782014-01-17 14:39:48 +01001925 intel_edp_backlight_off(intel_dp);
Paulo Zanonid6c50ff2012-10-23 18:30:06 -02001926 }
Eugeni Dodonov72662e12012-05-09 15:37:31 -03001927}
Paulo Zanoni79f689a2012-10-05 12:05:52 -03001928
Maarten Lankhorstfd6bbda2016-08-09 17:04:04 +02001929static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder,
1930 struct intel_crtc_state *pipe_config,
1931 struct drm_connector_state *conn_state)
Imre Deak95a7a2a2016-06-13 16:44:35 +03001932{
Imre Deak95a7a2a2016-06-13 16:44:35 +03001933 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
Ander Conselvan de Oliveira47a6bc62016-10-06 19:22:17 +03001934 uint8_t mask = intel_crtc->config->lane_lat_optim_mask;
Imre Deak95a7a2a2016-06-13 16:44:35 +03001935
Ander Conselvan de Oliveira47a6bc62016-10-06 19:22:17 +03001936 bxt_ddi_phy_set_lane_optim_mask(encoder, mask);
Imre Deak95a7a2a2016-06-13 16:44:35 +03001937}
1938
Ander Conselvan de Oliveiraad642172015-10-23 13:01:49 +03001939void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
Paulo Zanonic19b0662012-10-15 15:51:41 -03001940{
Ander Conselvan de Oliveiraad642172015-10-23 13:01:49 +03001941 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1942 struct drm_i915_private *dev_priv =
1943 to_i915(intel_dig_port->base.base.dev);
Paulo Zanoni174edf12012-10-26 19:05:50 -02001944 enum port port = intel_dig_port->port;
Paulo Zanonic19b0662012-10-15 15:51:41 -03001945 uint32_t val;
Syam Sidhardhanf3e227d2013-02-25 04:05:38 +05301946 bool wait = false;
Paulo Zanonic19b0662012-10-15 15:51:41 -03001947
1948 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
1949 val = I915_READ(DDI_BUF_CTL(port));
1950 if (val & DDI_BUF_CTL_ENABLE) {
1951 val &= ~DDI_BUF_CTL_ENABLE;
1952 I915_WRITE(DDI_BUF_CTL(port), val);
1953 wait = true;
1954 }
1955
1956 val = I915_READ(DP_TP_CTL(port));
1957 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1958 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1959 I915_WRITE(DP_TP_CTL(port), val);
1960 POSTING_READ(DP_TP_CTL(port));
1961
1962 if (wait)
1963 intel_wait_ddi_buf_idle(dev_priv, port);
1964 }
1965
Dave Airlie0e32b392014-05-02 14:02:48 +10001966 val = DP_TP_CTL_ENABLE |
Paulo Zanonic19b0662012-10-15 15:51:41 -03001967 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
Ville Syrjälä64ee2fd2016-07-28 17:50:39 +03001968 if (intel_dp->link_mst)
Dave Airlie0e32b392014-05-02 14:02:48 +10001969 val |= DP_TP_CTL_MODE_MST;
1970 else {
1971 val |= DP_TP_CTL_MODE_SST;
1972 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1973 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
1974 }
Paulo Zanonic19b0662012-10-15 15:51:41 -03001975 I915_WRITE(DP_TP_CTL(port), val);
1976 POSTING_READ(DP_TP_CTL(port));
1977
1978 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
1979 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
1980 POSTING_READ(DDI_BUF_CTL(port));
1981
1982 udelay(600);
1983}
Paulo Zanoni00c09d72012-10-26 19:05:52 -02001984
Libin Yang9935f7f2016-11-28 20:07:06 +08001985bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
1986 struct intel_crtc *intel_crtc)
1987{
1988 u32 temp;
1989
1990 if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
1991 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1992 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
1993 return true;
1994 }
1995 return false;
1996}
1997
Ville Syrjälä6801c182013-09-24 14:24:05 +03001998void intel_ddi_get_config(struct intel_encoder *encoder,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02001999 struct intel_crtc_state *pipe_config)
Jesse Barnes045ac3b2013-05-14 17:08:26 -07002000{
Chris Wilsonfac5e232016-07-04 11:34:36 +01002001 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
Jesse Barnes045ac3b2013-05-14 17:08:26 -07002002 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
Ander Conselvan de Oliveira0cb09a92015-01-30 12:17:23 +02002003 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
Daniel Vetterbbd440f2014-11-20 22:33:59 +01002004 struct intel_hdmi *intel_hdmi;
Jesse Barnes045ac3b2013-05-14 17:08:26 -07002005 u32 temp, flags = 0;
2006
Jani Nikula4d1de972016-03-18 17:05:42 +02002007 /* XXX: DSI transcoder paranoia */
2008 if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
2009 return;
2010
Jesse Barnes045ac3b2013-05-14 17:08:26 -07002011 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2012 if (temp & TRANS_DDI_PHSYNC)
2013 flags |= DRM_MODE_FLAG_PHSYNC;
2014 else
2015 flags |= DRM_MODE_FLAG_NHSYNC;
2016 if (temp & TRANS_DDI_PVSYNC)
2017 flags |= DRM_MODE_FLAG_PVSYNC;
2018 else
2019 flags |= DRM_MODE_FLAG_NVSYNC;
2020
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +02002021 pipe_config->base.adjusted_mode.flags |= flags;
Ville Syrjälä42571ae2013-09-06 23:29:00 +03002022
2023 switch (temp & TRANS_DDI_BPC_MASK) {
2024 case TRANS_DDI_BPC_6:
2025 pipe_config->pipe_bpp = 18;
2026 break;
2027 case TRANS_DDI_BPC_8:
2028 pipe_config->pipe_bpp = 24;
2029 break;
2030 case TRANS_DDI_BPC_10:
2031 pipe_config->pipe_bpp = 30;
2032 break;
2033 case TRANS_DDI_BPC_12:
2034 pipe_config->pipe_bpp = 36;
2035 break;
2036 default:
2037 break;
2038 }
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03002039
2040 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
2041 case TRANS_DDI_MODE_SELECT_HDMI:
Daniel Vetter6897b4b2014-04-24 23:54:47 +02002042 pipe_config->has_hdmi_sink = true;
Daniel Vetterbbd440f2014-11-20 22:33:59 +01002043 intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2044
Ville Syrjäläcda0aaa2015-11-26 18:27:07 +02002045 if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
Daniel Vetterbbd440f2014-11-20 22:33:59 +01002046 pipe_config->has_infoframe = true;
Ander Conselvan de Oliveirad4d62792016-04-27 15:44:16 +03002047 /* fall through */
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03002048 case TRANS_DDI_MODE_SELECT_DVI:
Ander Conselvan de Oliveirad4d62792016-04-27 15:44:16 +03002049 pipe_config->lane_count = 4;
2050 break;
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03002051 case TRANS_DDI_MODE_SELECT_FDI:
2052 break;
2053 case TRANS_DDI_MODE_SELECT_DP_SST:
2054 case TRANS_DDI_MODE_SELECT_DP_MST:
Ville Syrjälä90a6b7b2015-07-06 16:39:15 +03002055 pipe_config->lane_count =
2056 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03002057 intel_dp_get_m_n(intel_crtc, pipe_config);
2058 break;
2059 default:
2060 break;
2061 }
Daniel Vetter10214422013-11-18 07:38:16 +01002062
Libin Yang9935f7f2016-11-28 20:07:06 +08002063 pipe_config->has_audio =
2064 intel_ddi_is_audio_enabled(dev_priv, intel_crtc);
Daniel Vetter9ed109a2014-04-24 23:54:52 +02002065
Jani Nikula6aa23e62016-03-24 17:50:20 +02002066 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
2067 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
Daniel Vetter10214422013-11-18 07:38:16 +01002068 /*
2069 * This is a big fat ugly hack.
2070 *
2071 * Some machines in UEFI boot mode provide us a VBT that has 18
2072 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2073 * unknown we fail to light up. Yet the same BIOS boots up with
2074 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2075 * max, not what it tells us to use.
2076 *
2077 * Note: This will still be broken if the eDP panel is not lit
2078 * up by the BIOS, and thus we can't get the mode at module
2079 * load.
2080 */
2081 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
Jani Nikula6aa23e62016-03-24 17:50:20 +02002082 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2083 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
Daniel Vetter10214422013-11-18 07:38:16 +01002084 }
Jesse Barnes11578552014-01-21 12:42:10 -08002085
Damien Lespiau22606a12014-12-12 14:26:57 +00002086 intel_ddi_clock_get(encoder, pipe_config);
Imre Deak95a7a2a2016-06-13 16:44:35 +03002087
Ander Conselvan de Oliveiracc3f90f2016-12-02 10:23:49 +02002088 if (IS_GEN9_LP(dev_priv))
Imre Deak95a7a2a2016-06-13 16:44:35 +03002089 pipe_config->lane_lat_optim_mask =
2090 bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
Jesse Barnes045ac3b2013-05-14 17:08:26 -07002091}
2092
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01002093static bool intel_ddi_compute_config(struct intel_encoder *encoder,
Maarten Lankhorst0a478c22016-08-09 17:04:05 +02002094 struct intel_crtc_state *pipe_config,
2095 struct drm_connector_state *conn_state)
Paulo Zanoni00c09d72012-10-26 19:05:52 -02002096{
Chris Wilsonfac5e232016-07-04 11:34:36 +01002097 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01002098 int type = encoder->type;
Daniel Vettereccb1402013-05-22 00:50:22 +02002099 int port = intel_ddi_get_encoder_port(encoder);
Imre Deak95a7a2a2016-06-13 16:44:35 +03002100 int ret;
Paulo Zanoni00c09d72012-10-26 19:05:52 -02002101
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01002102 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
Paulo Zanoni00c09d72012-10-26 19:05:52 -02002103
Daniel Vettereccb1402013-05-22 00:50:22 +02002104 if (port == PORT_A)
2105 pipe_config->cpu_transcoder = TRANSCODER_EDP;
2106
Paulo Zanoni00c09d72012-10-26 19:05:52 -02002107 if (type == INTEL_OUTPUT_HDMI)
Maarten Lankhorst0a478c22016-08-09 17:04:05 +02002108 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
Paulo Zanoni00c09d72012-10-26 19:05:52 -02002109 else
Maarten Lankhorst0a478c22016-08-09 17:04:05 +02002110 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
Imre Deak95a7a2a2016-06-13 16:44:35 +03002111
Ander Conselvan de Oliveiracc3f90f2016-12-02 10:23:49 +02002112 if (IS_GEN9_LP(dev_priv) && ret)
Imre Deak95a7a2a2016-06-13 16:44:35 +03002113 pipe_config->lane_lat_optim_mask =
2114 bxt_ddi_phy_calc_lane_lat_optim_mask(encoder,
Ander Conselvan de Oliveirab284eed2016-10-06 19:22:16 +03002115 pipe_config->lane_count);
Imre Deak95a7a2a2016-06-13 16:44:35 +03002116
2117 return ret;
2118
Paulo Zanoni00c09d72012-10-26 19:05:52 -02002119}
2120
2121static const struct drm_encoder_funcs intel_ddi_funcs = {
Imre Deakbf93ba62016-04-18 10:04:21 +03002122 .reset = intel_dp_encoder_reset,
2123 .destroy = intel_dp_encoder_destroy,
Paulo Zanoni00c09d72012-10-26 19:05:52 -02002124};
2125
Paulo Zanoni4a28ae52013-10-09 13:52:36 -03002126static struct intel_connector *
2127intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
2128{
2129 struct intel_connector *connector;
2130 enum port port = intel_dig_port->port;
2131
Ander Conselvan de Oliveira9bdbd0b2015-04-10 10:59:10 +03002132 connector = intel_connector_alloc();
Paulo Zanoni4a28ae52013-10-09 13:52:36 -03002133 if (!connector)
2134 return NULL;
2135
2136 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
2137 if (!intel_dp_init_connector(intel_dig_port, connector)) {
2138 kfree(connector);
2139 return NULL;
2140 }
2141
2142 return connector;
2143}
2144
2145static struct intel_connector *
2146intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
2147{
2148 struct intel_connector *connector;
2149 enum port port = intel_dig_port->port;
2150
Ander Conselvan de Oliveira9bdbd0b2015-04-10 10:59:10 +03002151 connector = intel_connector_alloc();
Paulo Zanoni4a28ae52013-10-09 13:52:36 -03002152 if (!connector)
2153 return NULL;
2154
2155 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
2156 intel_hdmi_init_connector(intel_dig_port, connector);
2157
2158 return connector;
2159}
2160
Ander Conselvan de Oliveirac39055b2016-11-23 16:21:44 +02002161void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
Paulo Zanoni00c09d72012-10-26 19:05:52 -02002162{
2163 struct intel_digital_port *intel_dig_port;
2164 struct intel_encoder *intel_encoder;
2165 struct drm_encoder *encoder;
Shashank Sharmaff662122016-10-14 19:56:51 +05302166 bool init_hdmi, init_dp, init_lspcon = false;
Ville Syrjälä10e7bec2015-12-08 19:59:37 +02002167 int max_lanes;
2168
2169 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) {
2170 switch (port) {
2171 case PORT_A:
2172 max_lanes = 4;
2173 break;
2174 case PORT_E:
2175 max_lanes = 0;
2176 break;
2177 default:
2178 max_lanes = 4;
2179 break;
2180 }
2181 } else {
2182 switch (port) {
2183 case PORT_A:
2184 max_lanes = 2;
2185 break;
2186 case PORT_E:
2187 max_lanes = 2;
2188 break;
2189 default:
2190 max_lanes = 4;
2191 break;
2192 }
2193 }
Paulo Zanoni311a2092013-09-12 17:12:18 -03002194
2195 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
2196 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
2197 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
Shashank Sharmaff662122016-10-14 19:56:51 +05302198
2199 if (intel_bios_is_lspcon_present(dev_priv, port)) {
2200 /*
2201 * Lspcon device needs to be driven with DP connector
2202 * with special detection sequence. So make sure DP
2203 * is initialized before lspcon.
2204 */
2205 init_dp = true;
2206 init_lspcon = true;
2207 init_hdmi = false;
2208 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
2209 }
2210
Paulo Zanoni311a2092013-09-12 17:12:18 -03002211 if (!init_dp && !init_hdmi) {
Rodrigo Vivi500ea702015-08-07 17:01:16 -07002212 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
Paulo Zanoni311a2092013-09-12 17:12:18 -03002213 port_name(port));
Rodrigo Vivi500ea702015-08-07 17:01:16 -07002214 return;
Paulo Zanoni311a2092013-09-12 17:12:18 -03002215 }
Paulo Zanoni00c09d72012-10-26 19:05:52 -02002216
Daniel Vetterb14c5672013-09-19 12:18:32 +02002217 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
Paulo Zanoni00c09d72012-10-26 19:05:52 -02002218 if (!intel_dig_port)
2219 return;
2220
Paulo Zanoni00c09d72012-10-26 19:05:52 -02002221 intel_encoder = &intel_dig_port->base;
2222 encoder = &intel_encoder->base;
2223
Ander Conselvan de Oliveirac39055b2016-11-23 16:21:44 +02002224 drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs,
Ville Syrjälä580d8ed2016-05-27 20:59:24 +03002225 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
Paulo Zanoni00c09d72012-10-26 19:05:52 -02002226
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01002227 intel_encoder->compute_config = intel_ddi_compute_config;
Paulo Zanoni00c09d72012-10-26 19:05:52 -02002228 intel_encoder->enable = intel_enable_ddi;
Ander Conselvan de Oliveiracc3f90f2016-12-02 10:23:49 +02002229 if (IS_GEN9_LP(dev_priv))
Imre Deak95a7a2a2016-06-13 16:44:35 +03002230 intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable;
Paulo Zanoni00c09d72012-10-26 19:05:52 -02002231 intel_encoder->pre_enable = intel_ddi_pre_enable;
2232 intel_encoder->disable = intel_disable_ddi;
2233 intel_encoder->post_disable = intel_ddi_post_disable;
2234 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
Jesse Barnes045ac3b2013-05-14 17:08:26 -07002235 intel_encoder->get_config = intel_ddi_get_config;
Imre Deakbf93ba62016-04-18 10:04:21 +03002236 intel_encoder->suspend = intel_dp_encoder_suspend;
Ander Conselvan de Oliveira62b69562017-02-24 16:19:59 +02002237 intel_encoder->get_power_domains = intel_ddi_get_power_domains;
Paulo Zanoni00c09d72012-10-26 19:05:52 -02002238
2239 intel_dig_port->port = port;
Stéphane Marchesinbcf53de2013-07-12 13:54:41 -07002240 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
2241 (DDI_BUF_PORT_REVERSAL |
2242 DDI_A_4_LANES);
Paulo Zanoni00c09d72012-10-26 19:05:52 -02002243
Ander Conselvan de Oliveira62b69562017-02-24 16:19:59 +02002244 switch (port) {
2245 case PORT_A:
2246 intel_dig_port->ddi_io_power_domain =
2247 POWER_DOMAIN_PORT_DDI_A_IO;
2248 break;
2249 case PORT_B:
2250 intel_dig_port->ddi_io_power_domain =
2251 POWER_DOMAIN_PORT_DDI_B_IO;
2252 break;
2253 case PORT_C:
2254 intel_dig_port->ddi_io_power_domain =
2255 POWER_DOMAIN_PORT_DDI_C_IO;
2256 break;
2257 case PORT_D:
2258 intel_dig_port->ddi_io_power_domain =
2259 POWER_DOMAIN_PORT_DDI_D_IO;
2260 break;
2261 case PORT_E:
2262 intel_dig_port->ddi_io_power_domain =
2263 POWER_DOMAIN_PORT_DDI_E_IO;
2264 break;
2265 default:
2266 MISSING_CASE(port);
2267 }
2268
Matt Roper6c566dc2015-11-05 14:53:32 -08002269 /*
2270 * Bspec says that DDI_A_4_LANES is the only supported configuration
2271 * for Broxton. Yet some BIOS fail to set this bit on port A if eDP
2272 * wasn't lit up at boot. Force this bit on in our internal
2273 * configuration so that we use the proper lane count for our
2274 * calculations.
2275 */
Ander Conselvan de Oliveiracc3f90f2016-12-02 10:23:49 +02002276 if (IS_GEN9_LP(dev_priv) && port == PORT_A) {
Matt Roper6c566dc2015-11-05 14:53:32 -08002277 if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
2278 DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
2279 intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
Matt Ropered8d60f2016-01-28 15:09:37 -08002280 max_lanes = 4;
Matt Roper6c566dc2015-11-05 14:53:32 -08002281 }
2282 }
2283
Matt Ropered8d60f2016-01-28 15:09:37 -08002284 intel_dig_port->max_lanes = max_lanes;
2285
Paulo Zanoni00c09d72012-10-26 19:05:52 -02002286 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
Ander Conselvan de Oliveira79f255a2017-02-22 08:34:27 +02002287 intel_encoder->power_domain = intel_port_to_power_domain(port);
Pandiyan, Dhinakaran03cdc1d2016-09-19 18:24:38 -07002288 intel_encoder->port = port;
Chris Wilsonf68d6972014-08-04 07:15:09 +01002289 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
Ville Syrjäläbc079e82014-03-03 16:15:28 +02002290 intel_encoder->cloneable = 0;
Paulo Zanoni00c09d72012-10-26 19:05:52 -02002291
Chris Wilsonf68d6972014-08-04 07:15:09 +01002292 if (init_dp) {
2293 if (!intel_ddi_init_dp_connector(intel_dig_port))
2294 goto err;
Dave Airlie13cf5502014-06-18 11:29:35 +10002295
Chris Wilsonf68d6972014-08-04 07:15:09 +01002296 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
Ander Conselvan de Oliveiraca4c3892017-02-03 16:03:13 +02002297 dev_priv->hotplug.irq_port[port] = intel_dig_port;
Chris Wilsonf68d6972014-08-04 07:15:09 +01002298 }
Daniel Vetter21a8e6a2013-04-10 23:28:35 +02002299
Paulo Zanoni311a2092013-09-12 17:12:18 -03002300 /* In theory we don't need the encoder->type check, but leave it just in
2301 * case we have some really bad VBTs... */
Chris Wilsonf68d6972014-08-04 07:15:09 +01002302 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
2303 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
2304 goto err;
Daniel Vetter21a8e6a2013-04-10 23:28:35 +02002305 }
Chris Wilsonf68d6972014-08-04 07:15:09 +01002306
Shashank Sharmaff662122016-10-14 19:56:51 +05302307 if (init_lspcon) {
2308 if (lspcon_init(intel_dig_port))
2309 /* TODO: handle hdmi info frame part */
2310 DRM_DEBUG_KMS("LSPCON init success on port %c\n",
2311 port_name(port));
2312 else
2313 /*
2314 * LSPCON init faied, but DP init was success, so
2315 * lets try to drive as DP++ port.
2316 */
2317 DRM_ERROR("LSPCON init failed on port %c\n",
2318 port_name(port));
2319 }
2320
Chris Wilsonf68d6972014-08-04 07:15:09 +01002321 return;
2322
2323err:
2324 drm_encoder_cleanup(encoder);
2325 kfree(intel_dig_port);
Paulo Zanoni00c09d72012-10-26 19:05:52 -02002326}