Ander Conselvan de Oliveira | ac7f11c | 2016-03-08 17:46:19 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2012-2016 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | */ |
| 24 | |
| 25 | #ifndef _INTEL_DPLL_MGR_H_ |
| 26 | #define _INTEL_DPLL_MGR_H_ |
| 27 | |
Ander Conselvan de Oliveira | daedf20 | 2016-03-08 17:46:23 +0200 | [diff] [blame] | 28 | /*FIXME: Move this to a more appropriate place. */ |
| 29 | #define abs_diff(a, b) ({ \ |
| 30 | typeof(a) __a = (a); \ |
| 31 | typeof(b) __b = (b); \ |
| 32 | (void) (&__a == &__b); \ |
| 33 | __a > __b ? (__a - __b) : (__b - __a); }) |
| 34 | |
Ander Conselvan de Oliveira | ac7f11c | 2016-03-08 17:46:19 +0200 | [diff] [blame] | 35 | struct drm_i915_private; |
Ander Conselvan de Oliveira | c2a9fcd | 2016-03-08 17:46:20 +0200 | [diff] [blame] | 36 | struct intel_crtc; |
| 37 | struct intel_crtc_state; |
Ander Conselvan de Oliveira | daedf20 | 2016-03-08 17:46:23 +0200 | [diff] [blame] | 38 | struct intel_encoder; |
Ander Conselvan de Oliveira | ac7f11c | 2016-03-08 17:46:19 +0200 | [diff] [blame] | 39 | |
Ander Conselvan de Oliveira | daedf20 | 2016-03-08 17:46:23 +0200 | [diff] [blame] | 40 | struct intel_shared_dpll; |
Ander Conselvan de Oliveira | f9476a6 | 2016-03-08 17:46:22 +0200 | [diff] [blame] | 41 | struct intel_dpll_mgr; |
| 42 | |
Ander Conselvan de Oliveira | 294591c | 2016-12-29 17:22:11 +0200 | [diff] [blame] | 43 | /** |
| 44 | * enum intel_dpll_id - possible DPLL ids |
| 45 | * |
| 46 | * Enumeration of possible IDs for a DPLL. Real shared dpll ids must be >= 0. |
| 47 | */ |
Ander Conselvan de Oliveira | ac7f11c | 2016-03-08 17:46:19 +0200 | [diff] [blame] | 48 | enum intel_dpll_id { |
Ander Conselvan de Oliveira | 294591c | 2016-12-29 17:22:11 +0200 | [diff] [blame] | 49 | /** |
| 50 | * @DPLL_ID_PRIVATE: non-shared dpll in use |
| 51 | */ |
| 52 | DPLL_ID_PRIVATE = -1, |
| 53 | |
| 54 | /** |
| 55 | * @DPLL_ID_PCH_PLL_A: DPLL A in ILK, SNB and IVB |
| 56 | */ |
Ander Conselvan de Oliveira | ac7f11c | 2016-03-08 17:46:19 +0200 | [diff] [blame] | 57 | DPLL_ID_PCH_PLL_A = 0, |
Ander Conselvan de Oliveira | 294591c | 2016-12-29 17:22:11 +0200 | [diff] [blame] | 58 | /** |
| 59 | * @DPLL_ID_PCH_PLL_B: DPLL B in ILK, SNB and IVB |
| 60 | */ |
Ander Conselvan de Oliveira | ac7f11c | 2016-03-08 17:46:19 +0200 | [diff] [blame] | 61 | DPLL_ID_PCH_PLL_B = 1, |
Ander Conselvan de Oliveira | 294591c | 2016-12-29 17:22:11 +0200 | [diff] [blame] | 62 | |
| 63 | |
| 64 | /** |
| 65 | * @DPLL_ID_WRPLL1: HSW and BDW WRPLL1 |
| 66 | */ |
Ander Conselvan de Oliveira | ac7f11c | 2016-03-08 17:46:19 +0200 | [diff] [blame] | 67 | DPLL_ID_WRPLL1 = 0, |
Ander Conselvan de Oliveira | 294591c | 2016-12-29 17:22:11 +0200 | [diff] [blame] | 68 | /** |
| 69 | * @DPLL_ID_WRPLL2: HSW and BDW WRPLL2 |
| 70 | */ |
Ander Conselvan de Oliveira | ac7f11c | 2016-03-08 17:46:19 +0200 | [diff] [blame] | 71 | DPLL_ID_WRPLL2 = 1, |
Ander Conselvan de Oliveira | 294591c | 2016-12-29 17:22:11 +0200 | [diff] [blame] | 72 | /** |
| 73 | * @DPLL_ID_SPLL: HSW and BDW SPLL |
| 74 | */ |
Ander Conselvan de Oliveira | ac7f11c | 2016-03-08 17:46:19 +0200 | [diff] [blame] | 75 | DPLL_ID_SPLL = 2, |
Ander Conselvan de Oliveira | 294591c | 2016-12-29 17:22:11 +0200 | [diff] [blame] | 76 | /** |
| 77 | * @DPLL_ID_LCPLL_810: HSW and BDW 0.81 GHz LCPLL |
| 78 | */ |
Ander Conselvan de Oliveira | 9d16da6 | 2016-03-08 17:46:26 +0200 | [diff] [blame] | 79 | DPLL_ID_LCPLL_810 = 3, |
Ander Conselvan de Oliveira | 294591c | 2016-12-29 17:22:11 +0200 | [diff] [blame] | 80 | /** |
| 81 | * @DPLL_ID_LCPLL_1350: HSW and BDW 1.35 GHz LCPLL |
| 82 | */ |
Ander Conselvan de Oliveira | 9d16da6 | 2016-03-08 17:46:26 +0200 | [diff] [blame] | 83 | DPLL_ID_LCPLL_1350 = 4, |
Ander Conselvan de Oliveira | 294591c | 2016-12-29 17:22:11 +0200 | [diff] [blame] | 84 | /** |
| 85 | * @DPLL_ID_LCPLL_2700: HSW and BDW 2.7 GHz LCPLL |
| 86 | */ |
Ander Conselvan de Oliveira | 9d16da6 | 2016-03-08 17:46:26 +0200 | [diff] [blame] | 87 | DPLL_ID_LCPLL_2700 = 5, |
Ander Conselvan de Oliveira | ac7f11c | 2016-03-08 17:46:19 +0200 | [diff] [blame] | 88 | |
Ander Conselvan de Oliveira | 294591c | 2016-12-29 17:22:11 +0200 | [diff] [blame] | 89 | |
| 90 | /** |
| 91 | * @DPLL_ID_SKL_DPLL0: SKL and later DPLL0 |
| 92 | */ |
Ander Conselvan de Oliveira | a3c988e | 2016-03-08 17:46:27 +0200 | [diff] [blame] | 93 | DPLL_ID_SKL_DPLL0 = 0, |
Ander Conselvan de Oliveira | 294591c | 2016-12-29 17:22:11 +0200 | [diff] [blame] | 94 | /** |
| 95 | * @DPLL_ID_SKL_DPLL1: SKL and later DPLL1 |
| 96 | */ |
Ander Conselvan de Oliveira | a3c988e | 2016-03-08 17:46:27 +0200 | [diff] [blame] | 97 | DPLL_ID_SKL_DPLL1 = 1, |
Ander Conselvan de Oliveira | 294591c | 2016-12-29 17:22:11 +0200 | [diff] [blame] | 98 | /** |
| 99 | * @DPLL_ID_SKL_DPLL2: SKL and later DPLL2 |
| 100 | */ |
Ander Conselvan de Oliveira | a3c988e | 2016-03-08 17:46:27 +0200 | [diff] [blame] | 101 | DPLL_ID_SKL_DPLL2 = 2, |
Ander Conselvan de Oliveira | 294591c | 2016-12-29 17:22:11 +0200 | [diff] [blame] | 102 | /** |
| 103 | * @DPLL_ID_SKL_DPLL3: SKL and later DPLL3 |
| 104 | */ |
Ander Conselvan de Oliveira | a3c988e | 2016-03-08 17:46:27 +0200 | [diff] [blame] | 105 | DPLL_ID_SKL_DPLL3 = 3, |
Ander Conselvan de Oliveira | ac7f11c | 2016-03-08 17:46:19 +0200 | [diff] [blame] | 106 | }; |
Ander Conselvan de Oliveira | 9d16da6 | 2016-03-08 17:46:26 +0200 | [diff] [blame] | 107 | #define I915_NUM_PLLS 6 |
| 108 | |
Ander Conselvan de Oliveira | ac7f11c | 2016-03-08 17:46:19 +0200 | [diff] [blame] | 109 | struct intel_dpll_hw_state { |
| 110 | /* i9xx, pch plls */ |
| 111 | uint32_t dpll; |
| 112 | uint32_t dpll_md; |
| 113 | uint32_t fp0; |
| 114 | uint32_t fp1; |
| 115 | |
| 116 | /* hsw, bdw */ |
| 117 | uint32_t wrpll; |
| 118 | uint32_t spll; |
| 119 | |
| 120 | /* skl */ |
| 121 | /* |
| 122 | * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in |
| 123 | * lower part of ctrl1 and they get shifted into position when writing |
| 124 | * the register. This allows us to easily compare the state to share |
| 125 | * the DPLL. |
| 126 | */ |
| 127 | uint32_t ctrl1; |
| 128 | /* HDMI only, 0 when used for DP */ |
| 129 | uint32_t cfgcr1, cfgcr2; |
| 130 | |
| 131 | /* bxt */ |
| 132 | uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, |
| 133 | pcsdw12; |
| 134 | }; |
| 135 | |
Ander Conselvan de Oliveira | 294591c | 2016-12-29 17:22:11 +0200 | [diff] [blame] | 136 | /** |
| 137 | * struct intel_shared_dpll_state - hold the DPLL atomic state |
| 138 | * |
| 139 | * This structure holds an atomic state for the DPLL, that can represent |
| 140 | * either its current state (in struct &intel_shared_dpll) or a desired |
| 141 | * future state which would be applied by an atomic mode set (stored in |
| 142 | * a struct &intel_atomic_state). |
| 143 | * |
| 144 | * See also intel_get_shared_dpll() and intel_release_shared_dpll(). |
| 145 | */ |
Ander Conselvan de Oliveira | 2c42e53 | 2016-12-29 17:22:09 +0200 | [diff] [blame] | 146 | struct intel_shared_dpll_state { |
Ander Conselvan de Oliveira | 294591c | 2016-12-29 17:22:11 +0200 | [diff] [blame] | 147 | /** |
| 148 | * @crtc_mask: mask of CRTC using this DPLL, active or not |
| 149 | */ |
| 150 | unsigned crtc_mask; |
| 151 | |
| 152 | /** |
| 153 | * @hw_state: hardware configuration for the DPLL stored in |
| 154 | * struct &intel_dpll_hw_state. |
| 155 | */ |
Ander Conselvan de Oliveira | ac7f11c | 2016-03-08 17:46:19 +0200 | [diff] [blame] | 156 | struct intel_dpll_hw_state hw_state; |
| 157 | }; |
| 158 | |
Ander Conselvan de Oliveira | 294591c | 2016-12-29 17:22:11 +0200 | [diff] [blame] | 159 | /** |
| 160 | * struct intel_shared_dpll_funcs - platform specific hooks for managing DPLLs |
| 161 | */ |
Ander Conselvan de Oliveira | 2edd644 | 2016-03-08 17:46:21 +0200 | [diff] [blame] | 162 | struct intel_shared_dpll_funcs { |
Ander Conselvan de Oliveira | 294591c | 2016-12-29 17:22:11 +0200 | [diff] [blame] | 163 | /** |
| 164 | * @prepare: |
| 165 | * |
| 166 | * Optional hook to perform operations prior to enabling the PLL. |
| 167 | * Called from intel_prepare_shared_dpll() function unless the PLL |
| 168 | * is already enabled. |
| 169 | */ |
Ander Conselvan de Oliveira | eac6176 | 2016-12-29 17:22:10 +0200 | [diff] [blame] | 170 | void (*prepare)(struct drm_i915_private *dev_priv, |
| 171 | struct intel_shared_dpll *pll); |
Ander Conselvan de Oliveira | 294591c | 2016-12-29 17:22:11 +0200 | [diff] [blame] | 172 | |
| 173 | /** |
| 174 | * @enable: |
| 175 | * |
| 176 | * Hook for enabling the pll, called from intel_enable_shared_dpll() |
| 177 | * if the pll is not already enabled. |
| 178 | */ |
Ander Conselvan de Oliveira | ac7f11c | 2016-03-08 17:46:19 +0200 | [diff] [blame] | 179 | void (*enable)(struct drm_i915_private *dev_priv, |
| 180 | struct intel_shared_dpll *pll); |
Ander Conselvan de Oliveira | 294591c | 2016-12-29 17:22:11 +0200 | [diff] [blame] | 181 | |
| 182 | /** |
| 183 | * @disable: |
| 184 | * |
| 185 | * Hook for disabling the pll, called from intel_disable_shared_dpll() |
| 186 | * only when it is safe to disable the pll, i.e., there are no more |
| 187 | * tracked users for it. |
| 188 | */ |
Ander Conselvan de Oliveira | ac7f11c | 2016-03-08 17:46:19 +0200 | [diff] [blame] | 189 | void (*disable)(struct drm_i915_private *dev_priv, |
| 190 | struct intel_shared_dpll *pll); |
Ander Conselvan de Oliveira | 294591c | 2016-12-29 17:22:11 +0200 | [diff] [blame] | 191 | |
| 192 | /** |
| 193 | * @get_hw_state: |
| 194 | * |
| 195 | * Hook for reading the values currently programmed to the DPLL |
| 196 | * registers. This is used for initial hw state readout and state |
| 197 | * verification after a mode set. |
| 198 | */ |
Ander Conselvan de Oliveira | ac7f11c | 2016-03-08 17:46:19 +0200 | [diff] [blame] | 199 | bool (*get_hw_state)(struct drm_i915_private *dev_priv, |
| 200 | struct intel_shared_dpll *pll, |
| 201 | struct intel_dpll_hw_state *hw_state); |
| 202 | }; |
| 203 | |
Ander Conselvan de Oliveira | 294591c | 2016-12-29 17:22:11 +0200 | [diff] [blame] | 204 | /** |
| 205 | * struct intel_shared_dpll - display PLL with tracked state and users |
| 206 | */ |
Ander Conselvan de Oliveira | 2edd644 | 2016-03-08 17:46:21 +0200 | [diff] [blame] | 207 | struct intel_shared_dpll { |
Ander Conselvan de Oliveira | 294591c | 2016-12-29 17:22:11 +0200 | [diff] [blame] | 208 | /** |
| 209 | * @state: |
| 210 | * |
| 211 | * Store the state for the pll, including the its hw state |
| 212 | * and CRTCs using it. |
| 213 | */ |
Ander Conselvan de Oliveira | 2c42e53 | 2016-12-29 17:22:09 +0200 | [diff] [blame] | 214 | struct intel_shared_dpll_state state; |
Ander Conselvan de Oliveira | 2edd644 | 2016-03-08 17:46:21 +0200 | [diff] [blame] | 215 | |
Ander Conselvan de Oliveira | 294591c | 2016-12-29 17:22:11 +0200 | [diff] [blame] | 216 | /** |
| 217 | * @active_mask: mask of active CRTCs (i.e. DPMS on) using this DPLL |
| 218 | */ |
| 219 | unsigned active_mask; |
| 220 | |
| 221 | /** |
| 222 | * @on: is the PLL actually active? Disabled during modeset |
| 223 | */ |
| 224 | bool on; |
| 225 | |
| 226 | /** |
| 227 | * @name: DPLL name; used for logging |
| 228 | */ |
Ander Conselvan de Oliveira | 2edd644 | 2016-03-08 17:46:21 +0200 | [diff] [blame] | 229 | const char *name; |
Ander Conselvan de Oliveira | 294591c | 2016-12-29 17:22:11 +0200 | [diff] [blame] | 230 | |
| 231 | /** |
| 232 | * @id: unique indentifier for this DPLL; should match the index in the |
| 233 | * dev_priv->shared_dplls array |
| 234 | */ |
Ander Conselvan de Oliveira | 2edd644 | 2016-03-08 17:46:21 +0200 | [diff] [blame] | 235 | enum intel_dpll_id id; |
| 236 | |
Ander Conselvan de Oliveira | 294591c | 2016-12-29 17:22:11 +0200 | [diff] [blame] | 237 | /** |
| 238 | * @funcs: platform specific hooks |
| 239 | */ |
Ander Conselvan de Oliveira | 2edd644 | 2016-03-08 17:46:21 +0200 | [diff] [blame] | 240 | struct intel_shared_dpll_funcs funcs; |
Ander Conselvan de Oliveira | 9d16da6 | 2016-03-08 17:46:26 +0200 | [diff] [blame] | 241 | |
Ander Conselvan de Oliveira | 294591c | 2016-12-29 17:22:11 +0200 | [diff] [blame] | 242 | #define INTEL_DPLL_ALWAYS_ON (1 << 0) |
| 243 | /** |
| 244 | * @flags: |
| 245 | * |
| 246 | * INTEL_DPLL_ALWAYS_ON |
| 247 | * Inform the state checker that the DPLL is kept enabled even if |
| 248 | * not in use by any CRTC. |
| 249 | */ |
Ander Conselvan de Oliveira | 9d16da6 | 2016-03-08 17:46:26 +0200 | [diff] [blame] | 250 | uint32_t flags; |
Ander Conselvan de Oliveira | 2edd644 | 2016-03-08 17:46:21 +0200 | [diff] [blame] | 251 | }; |
| 252 | |
Ander Conselvan de Oliveira | ac7f11c | 2016-03-08 17:46:19 +0200 | [diff] [blame] | 253 | #define SKL_DPLL0 0 |
| 254 | #define SKL_DPLL1 1 |
| 255 | #define SKL_DPLL2 2 |
| 256 | #define SKL_DPLL3 3 |
| 257 | |
Ander Conselvan de Oliveira | c2a9fcd | 2016-03-08 17:46:20 +0200 | [diff] [blame] | 258 | /* shared dpll functions */ |
| 259 | struct intel_shared_dpll * |
| 260 | intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv, |
| 261 | enum intel_dpll_id id); |
| 262 | enum intel_dpll_id |
| 263 | intel_get_shared_dpll_id(struct drm_i915_private *dev_priv, |
| 264 | struct intel_shared_dpll *pll); |
Ander Conselvan de Oliveira | c2a9fcd | 2016-03-08 17:46:20 +0200 | [diff] [blame] | 265 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
| 266 | struct intel_shared_dpll *pll, |
| 267 | bool state); |
| 268 | #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true) |
| 269 | #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false) |
| 270 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | daedf20 | 2016-03-08 17:46:23 +0200 | [diff] [blame] | 271 | struct intel_crtc_state *state, |
| 272 | struct intel_encoder *encoder); |
Ander Conselvan de Oliveira | a1c414e | 2016-12-29 17:22:07 +0200 | [diff] [blame] | 273 | void intel_release_shared_dpll(struct intel_shared_dpll *dpll, |
| 274 | struct intel_crtc *crtc, |
| 275 | struct drm_atomic_state *state); |
Ander Conselvan de Oliveira | c2a9fcd | 2016-03-08 17:46:20 +0200 | [diff] [blame] | 276 | void intel_prepare_shared_dpll(struct intel_crtc *crtc); |
| 277 | void intel_enable_shared_dpll(struct intel_crtc *crtc); |
| 278 | void intel_disable_shared_dpll(struct intel_crtc *crtc); |
Ander Conselvan de Oliveira | 3c0fb58 | 2016-12-29 17:22:08 +0200 | [diff] [blame] | 279 | void intel_shared_dpll_swap_state(struct drm_atomic_state *state); |
Ander Conselvan de Oliveira | c2a9fcd | 2016-03-08 17:46:20 +0200 | [diff] [blame] | 280 | void intel_shared_dpll_init(struct drm_device *dev); |
| 281 | |
Ander Conselvan de Oliveira | f50b79f | 2016-12-29 17:22:12 +0200 | [diff] [blame] | 282 | void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv, |
| 283 | struct intel_dpll_hw_state *hw_state); |
| 284 | |
Ander Conselvan de Oliveira | ac7f11c | 2016-03-08 17:46:19 +0200 | [diff] [blame] | 285 | #endif /* _INTEL_DPLL_MGR_H_ */ |