Kumar Gala | b053dc5 | 2009-06-19 08:31:05 -0500 | [diff] [blame] | 1 | SPI (Serial Peripheral Interface) busses |
| 2 | |
Geert Uytterhoeven | a8830cb | 2017-05-22 15:11:40 +0200 | [diff] [blame] | 3 | SPI busses can be described with a node for the SPI controller device |
| 4 | and a set of child nodes for each SPI slave on the bus. The system's SPI |
| 5 | controller may be described for use in SPI master mode or in SPI slave mode, |
| 6 | but not for both at the same time. |
Kumar Gala | b053dc5 | 2009-06-19 08:31:05 -0500 | [diff] [blame] | 7 | |
Geert Uytterhoeven | a8830cb | 2017-05-22 15:11:40 +0200 | [diff] [blame] | 8 | The SPI controller node requires the following properties: |
| 9 | - compatible - Name of SPI bus controller following generic names |
| 10 | recommended practice. |
| 11 | |
| 12 | In master mode, the SPI controller node requires the following additional |
| 13 | properties: |
Kumar Gala | b053dc5 | 2009-06-19 08:31:05 -0500 | [diff] [blame] | 14 | - #address-cells - number of cells required to define a chip select |
Geert Uytterhoeven | a777059 | 2016-06-22 14:48:26 +0200 | [diff] [blame] | 15 | address on the SPI bus. |
Kumar Gala | b053dc5 | 2009-06-19 08:31:05 -0500 | [diff] [blame] | 16 | - #size-cells - should be zero. |
Geert Uytterhoeven | a8830cb | 2017-05-22 15:11:40 +0200 | [diff] [blame] | 17 | |
| 18 | In slave mode, the SPI controller node requires one additional property: |
| 19 | - spi-slave - Empty property. |
| 20 | |
Kumar Gala | b053dc5 | 2009-06-19 08:31:05 -0500 | [diff] [blame] | 21 | No other properties are required in the SPI bus node. It is assumed |
| 22 | that a driver for an SPI bus device will understand that it is an SPI bus. |
| 23 | However, the binding does not attempt to define the specific method for |
| 24 | assigning chip select numbers. Since SPI chip select configuration is |
| 25 | flexible and non-standardized, it is left out of this binding with the |
| 26 | assumption that board specific platform code will be used to manage |
| 27 | chip selects. Individual drivers can define additional properties to |
| 28 | support describing the chip select layout. |
| 29 | |
Geert Uytterhoeven | a8830cb | 2017-05-22 15:11:40 +0200 | [diff] [blame] | 30 | Optional properties (master mode only): |
Geert Uytterhoeven | a777059 | 2016-06-22 14:48:26 +0200 | [diff] [blame] | 31 | - cs-gpios - gpios chip select. |
| 32 | - num-cs - total number of chipselects. |
Roland Stigge | 41962f9 | 2012-08-22 15:49:19 +0200 | [diff] [blame] | 33 | |
Geert Uytterhoeven | a777059 | 2016-06-22 14:48:26 +0200 | [diff] [blame] | 34 | If cs-gpios is used the number of chip selects will be increased automatically |
| 35 | with max(cs-gpios > hw cs). |
Jean-Christophe PLAGNIOL-VILLARD | 7431798 | 2012-11-15 20:19:57 +0100 | [diff] [blame] | 36 | |
| 37 | So if for example the controller has 2 CS lines, and the cs-gpios |
| 38 | property looks like this: |
| 39 | |
Guenther Wutz | c4dcd20 | 2016-08-03 16:11:54 +0200 | [diff] [blame] | 40 | cs-gpios = <&gpio1 0 0>, <0>, <&gpio1 1 0>, <&gpio1 2 0>; |
Jean-Christophe PLAGNIOL-VILLARD | 7431798 | 2012-11-15 20:19:57 +0100 | [diff] [blame] | 41 | |
| 42 | Then it should be configured so that num_chipselect = 4 with the |
| 43 | following mapping: |
| 44 | |
| 45 | cs0 : &gpio1 0 0 |
| 46 | cs1 : native |
| 47 | cs2 : &gpio1 1 0 |
| 48 | cs3 : &gpio1 2 0 |
| 49 | |
Geert Uytterhoeven | a8830cb | 2017-05-22 15:11:40 +0200 | [diff] [blame] | 50 | |
| 51 | SPI slave nodes must be children of the SPI controller node. |
| 52 | |
| 53 | In master mode, one or more slave nodes (up to the number of chip selects) can |
| 54 | be present. Required properties are: |
| 55 | - compatible - Name of SPI device following generic names recommended |
| 56 | practice. |
| 57 | - reg - Chip select address of device. |
| 58 | - spi-max-frequency - Maximum SPI clocking speed of device in Hz. |
| 59 | |
| 60 | In slave mode, the (single) slave node is optional. |
| 61 | If present, it must be called "slave". Required properties are: |
| 62 | - compatible - Name of SPI device following generic names recommended |
| 63 | practice. |
| 64 | |
| 65 | All slave nodes can contain the following optional properties: |
| 66 | - spi-cpol - Empty property indicating device requires inverse clock |
| 67 | polarity (CPOL) mode. |
| 68 | - spi-cpha - Empty property indicating device requires shifted clock |
| 69 | phase (CPHA) mode. |
| 70 | - spi-cs-high - Empty property indicating device requires chip select |
| 71 | active high. |
| 72 | - spi-3wire - Empty property indicating device requires 3-wire mode. |
| 73 | - spi-lsb-first - Empty property indicating device requires LSB first mode. |
| 74 | - spi-tx-bus-width - The bus width (number of data wires) that is used for MOSI. |
| 75 | Defaults to 1 if not present. |
| 76 | - spi-rx-bus-width - The bus width (number of data wires) that is used for MISO. |
| 77 | Defaults to 1 if not present. |
| 78 | - spi-rx-delay-us - Microsecond delay after a read transfer. |
| 79 | - spi-tx-delay-us - Microsecond delay after a write transfer. |
wangyuhang | a110f93 | 2013-09-01 17:36:21 +0800 | [diff] [blame] | 80 | |
| 81 | Some SPI controllers and devices support Dual and Quad SPI transfer mode. |
Geert Uytterhoeven | a777059 | 2016-06-22 14:48:26 +0200 | [diff] [blame] | 82 | It allows data in the SPI system to be transferred using 2 wires (DUAL) or 4 |
| 83 | wires (QUAD). |
wangyuhang | a110f93 | 2013-09-01 17:36:21 +0800 | [diff] [blame] | 84 | Now the value that spi-tx-bus-width and spi-rx-bus-width can receive is |
Geert Uytterhoeven | a777059 | 2016-06-22 14:48:26 +0200 | [diff] [blame] | 85 | only 1 (SINGLE), 2 (DUAL) and 4 (QUAD). |
wangyuhang | a110f93 | 2013-09-01 17:36:21 +0800 | [diff] [blame] | 86 | Dual/Quad mode is not allowed when 3-wire mode is used. |
Kumar Gala | b053dc5 | 2009-06-19 08:31:05 -0500 | [diff] [blame] | 87 | |
Jean-Christophe PLAGNIOL-VILLARD | 7431798 | 2012-11-15 20:19:57 +0100 | [diff] [blame] | 88 | If a gpio chipselect is used for the SPI slave the gpio number will be passed |
Baruch Siach | ba1271b | 2013-12-05 13:39:05 +0200 | [diff] [blame] | 89 | via the SPI master node cs-gpios property. |
Jean-Christophe PLAGNIOL-VILLARD | 7431798 | 2012-11-15 20:19:57 +0100 | [diff] [blame] | 90 | |
Kumar Gala | b053dc5 | 2009-06-19 08:31:05 -0500 | [diff] [blame] | 91 | SPI example for an MPC5200 SPI bus: |
| 92 | spi@f00 { |
| 93 | #address-cells = <1>; |
| 94 | #size-cells = <0>; |
| 95 | compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; |
| 96 | reg = <0xf00 0x20>; |
| 97 | interrupts = <2 13 0 2 14 0>; |
| 98 | interrupt-parent = <&mpc5200_pic>; |
| 99 | |
| 100 | ethernet-switch@0 { |
| 101 | compatible = "micrel,ks8995m"; |
| 102 | spi-max-frequency = <1000000>; |
| 103 | reg = <0>; |
| 104 | }; |
| 105 | |
| 106 | codec@1 { |
| 107 | compatible = "ti,tlv320aic26"; |
| 108 | spi-max-frequency = <100000>; |
| 109 | reg = <1>; |
| 110 | }; |
| 111 | }; |