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Samuel Ortizfa9ff4b2008-02-07 00:14:49 -08001/*
2 * driver/mfd/asic3.c
3 *
4 * Compaq ASIC3 support.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Copyright 2001 Compaq Computer Corporation.
11 * Copyright 2004-2005 Phil Blundell
Samuel Ortiz6f2384c2008-06-20 11:02:19 +020012 * Copyright 2007-2008 OpenedHand Ltd.
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -080013 *
14 * Authors: Phil Blundell <pb@handhelds.org>,
15 * Samuel Ortiz <sameo@openedhand.com>
16 *
17 */
18
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -080019#include <linux/kernel.h>
Philipp Zabel9461f652009-06-15 12:10:24 +020020#include <linux/delay.h>
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -080021#include <linux/irq.h>
Samuel Ortiz6f2384c2008-06-20 11:02:19 +020022#include <linux/gpio.h>
Paul Gortmaker5d4a3572011-07-10 12:41:10 -040023#include <linux/export.h>
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -080024#include <linux/io.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090025#include <linux/slab.h>
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -080026#include <linux/spinlock.h>
27#include <linux/platform_device.h>
28
29#include <linux/mfd/asic3.h>
Philipp Zabel9461f652009-06-15 12:10:24 +020030#include <linux/mfd/core.h>
31#include <linux/mfd/ds1wm.h>
Philipp Zabel09f05ce2009-06-15 12:10:25 +020032#include <linux/mfd/tmio.h>
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -080033
Philipp Zabele956a2a2009-06-05 18:31:02 +020034enum {
35 ASIC3_CLOCK_SPI,
36 ASIC3_CLOCK_OWM,
37 ASIC3_CLOCK_PWM0,
38 ASIC3_CLOCK_PWM1,
39 ASIC3_CLOCK_LED0,
40 ASIC3_CLOCK_LED1,
41 ASIC3_CLOCK_LED2,
42 ASIC3_CLOCK_SD_HOST,
43 ASIC3_CLOCK_SD_BUS,
44 ASIC3_CLOCK_SMBUS,
45 ASIC3_CLOCK_EX0,
46 ASIC3_CLOCK_EX1,
47};
48
49struct asic3_clk {
50 int enabled;
51 unsigned int cdex;
52 unsigned long rate;
53};
54
55#define INIT_CDEX(_name, _rate) \
56 [ASIC3_CLOCK_##_name] = { \
57 .cdex = CLOCK_CDEX_##_name, \
58 .rate = _rate, \
59 }
60
Mark Brown59f2ad22010-12-11 12:59:35 +000061static struct asic3_clk asic3_clk_init[] __initdata = {
Philipp Zabele956a2a2009-06-05 18:31:02 +020062 INIT_CDEX(SPI, 0),
63 INIT_CDEX(OWM, 5000000),
64 INIT_CDEX(PWM0, 0),
65 INIT_CDEX(PWM1, 0),
66 INIT_CDEX(LED0, 0),
67 INIT_CDEX(LED1, 0),
68 INIT_CDEX(LED2, 0),
69 INIT_CDEX(SD_HOST, 24576000),
70 INIT_CDEX(SD_BUS, 12288000),
71 INIT_CDEX(SMBUS, 0),
72 INIT_CDEX(EX0, 32768),
73 INIT_CDEX(EX1, 24576000),
74};
75
Samuel Ortiz6f2384c2008-06-20 11:02:19 +020076struct asic3 {
77 void __iomem *mapping;
78 unsigned int bus_shift;
79 unsigned int irq_nr;
80 unsigned int irq_base;
81 spinlock_t lock;
82 u16 irq_bothedge[4];
83 struct gpio_chip gpio;
84 struct device *dev;
Ian Molton64e88672010-01-06 13:51:48 +010085 void __iomem *tmio_cnf;
Philipp Zabele956a2a2009-06-05 18:31:02 +020086
87 struct asic3_clk clocks[ARRAY_SIZE(asic3_clk_init)];
Samuel Ortiz6f2384c2008-06-20 11:02:19 +020088};
89
90static int asic3_gpio_get(struct gpio_chip *chip, unsigned offset);
91
Paul Parsons13ca4f62011-05-13 18:53:03 +000092void asic3_write_register(struct asic3 *asic, unsigned int reg, u32 value)
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -080093{
Al Virob32661e2008-03-29 03:10:58 +000094 iowrite16(value, asic->mapping +
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -080095 (reg >> asic->bus_shift));
96}
Paul Parsons13ca4f62011-05-13 18:53:03 +000097EXPORT_SYMBOL_GPL(asic3_write_register);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -080098
Paul Parsons13ca4f62011-05-13 18:53:03 +000099u32 asic3_read_register(struct asic3 *asic, unsigned int reg)
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800100{
Al Virob32661e2008-03-29 03:10:58 +0000101 return ioread16(asic->mapping +
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800102 (reg >> asic->bus_shift));
103}
Paul Parsons13ca4f62011-05-13 18:53:03 +0000104EXPORT_SYMBOL_GPL(asic3_read_register);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800105
Mark Brown59f2ad22010-12-11 12:59:35 +0000106static void asic3_set_register(struct asic3 *asic, u32 reg, u32 bits, bool set)
Philipp Zabel6483c1b2009-06-05 18:31:01 +0200107{
108 unsigned long flags;
109 u32 val;
110
111 spin_lock_irqsave(&asic->lock, flags);
112 val = asic3_read_register(asic, reg);
113 if (set)
114 val |= bits;
115 else
116 val &= ~bits;
117 asic3_write_register(asic, reg, val);
118 spin_unlock_irqrestore(&asic->lock, flags);
119}
120
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800121/* IRQs */
122#define MAX_ASIC_ISR_LOOPS 20
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200123#define ASIC3_GPIO_BASE_INCR \
124 (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE)
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800125
126static void asic3_irq_flip_edge(struct asic3 *asic,
127 u32 base, int bit)
128{
129 u16 edge;
130 unsigned long flags;
131
132 spin_lock_irqsave(&asic->lock, flags);
133 edge = asic3_read_register(asic,
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200134 base + ASIC3_GPIO_EDGE_TRIGGER);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800135 edge ^= bit;
136 asic3_write_register(asic,
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200137 base + ASIC3_GPIO_EDGE_TRIGGER, edge);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800138 spin_unlock_irqrestore(&asic->lock, flags);
139}
140
Thomas Gleixnerbd0b9ac2015-09-14 10:42:37 +0200141static void asic3_irq_demux(struct irq_desc *desc)
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800142{
Thomas Gleixner52a7d6072011-03-25 11:12:26 +0000143 struct asic3 *asic = irq_desc_get_handler_data(desc);
144 struct irq_data *data = irq_desc_get_irq_data(desc);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800145 int iter, i;
146 unsigned long flags;
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800147
Axel Lina09aee82011-04-14 22:43:47 +0800148 data->chip->irq_ack(data);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800149
150 for (iter = 0 ; iter < MAX_ASIC_ISR_LOOPS; iter++) {
151 u32 status;
152 int bank;
153
154 spin_lock_irqsave(&asic->lock, flags);
155 status = asic3_read_register(asic,
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200156 ASIC3_OFFSET(INTR, P_INT_STAT));
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800157 spin_unlock_irqrestore(&asic->lock, flags);
158
159 /* Check all ten register bits */
160 if ((status & 0x3ff) == 0)
161 break;
162
163 /* Handle GPIO IRQs */
164 for (bank = 0; bank < ASIC3_NUM_GPIO_BANKS; bank++) {
165 if (status & (1 << bank)) {
166 unsigned long base, istat;
167
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200168 base = ASIC3_GPIO_A_BASE
169 + bank * ASIC3_GPIO_BASE_INCR;
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800170 spin_lock_irqsave(&asic->lock, flags);
171 istat = asic3_read_register(asic,
172 base +
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200173 ASIC3_GPIO_INT_STATUS);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800174 /* Clearing IntStatus */
175 asic3_write_register(asic,
176 base +
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200177 ASIC3_GPIO_INT_STATUS, 0);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800178 spin_unlock_irqrestore(&asic->lock, flags);
179
180 for (i = 0; i < ASIC3_GPIOS_PER_BANK; i++) {
181 int bit = (1 << i);
182 unsigned int irqnr;
183
184 if (!(istat & bit))
185 continue;
186
187 irqnr = asic->irq_base +
188 (ASIC3_GPIOS_PER_BANK * bank)
189 + i;
Thomas Gleixner52a7d6072011-03-25 11:12:26 +0000190 generic_handle_irq(irqnr);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800191 if (asic->irq_bothedge[bank] & bit)
192 asic3_irq_flip_edge(asic, base,
193 bit);
194 }
195 }
196 }
197
198 /* Handle remaining IRQs in the status register */
199 for (i = ASIC3_NUM_GPIOS; i < ASIC3_NR_IRQS; i++) {
200 /* They start at bit 4 and go up */
Thomas Gleixner52a7d6072011-03-25 11:12:26 +0000201 if (status & (1 << (i - ASIC3_NUM_GPIOS + 4)))
202 generic_handle_irq(asic->irq_base + i);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800203 }
204 }
205
206 if (iter >= MAX_ASIC_ISR_LOOPS)
Samuel Ortiz24f4f2e2008-06-20 11:11:19 +0200207 dev_err(asic->dev, "interrupt processing overrun\n");
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800208}
209
210static inline int asic3_irq_to_bank(struct asic3 *asic, int irq)
211{
212 int n;
213
214 n = (irq - asic->irq_base) >> 4;
215
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200216 return (n * (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE));
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800217}
218
219static inline int asic3_irq_to_index(struct asic3 *asic, int irq)
220{
221 return (irq - asic->irq_base) & 0xf;
222}
223
Mark Brown0f76aae2010-12-11 13:08:57 +0000224static void asic3_mask_gpio_irq(struct irq_data *data)
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800225{
Mark Brown0f76aae2010-12-11 13:08:57 +0000226 struct asic3 *asic = irq_data_get_irq_chip_data(data);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800227 u32 val, bank, index;
228 unsigned long flags;
229
Mark Brown0f76aae2010-12-11 13:08:57 +0000230 bank = asic3_irq_to_bank(asic, data->irq);
231 index = asic3_irq_to_index(asic, data->irq);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800232
233 spin_lock_irqsave(&asic->lock, flags);
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200234 val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800235 val |= 1 << index;
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200236 asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800237 spin_unlock_irqrestore(&asic->lock, flags);
238}
239
Mark Brown0f76aae2010-12-11 13:08:57 +0000240static void asic3_mask_irq(struct irq_data *data)
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800241{
Mark Brown0f76aae2010-12-11 13:08:57 +0000242 struct asic3 *asic = irq_data_get_irq_chip_data(data);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800243 int regval;
244 unsigned long flags;
245
246 spin_lock_irqsave(&asic->lock, flags);
247 regval = asic3_read_register(asic,
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200248 ASIC3_INTR_BASE +
249 ASIC3_INTR_INT_MASK);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800250
251 regval &= ~(ASIC3_INTMASK_MASK0 <<
Mark Brown0f76aae2010-12-11 13:08:57 +0000252 (data->irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800253
254 asic3_write_register(asic,
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200255 ASIC3_INTR_BASE +
256 ASIC3_INTR_INT_MASK,
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800257 regval);
258 spin_unlock_irqrestore(&asic->lock, flags);
259}
260
Mark Brown0f76aae2010-12-11 13:08:57 +0000261static void asic3_unmask_gpio_irq(struct irq_data *data)
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800262{
Mark Brown0f76aae2010-12-11 13:08:57 +0000263 struct asic3 *asic = irq_data_get_irq_chip_data(data);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800264 u32 val, bank, index;
265 unsigned long flags;
266
Mark Brown0f76aae2010-12-11 13:08:57 +0000267 bank = asic3_irq_to_bank(asic, data->irq);
268 index = asic3_irq_to_index(asic, data->irq);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800269
270 spin_lock_irqsave(&asic->lock, flags);
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200271 val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800272 val &= ~(1 << index);
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200273 asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800274 spin_unlock_irqrestore(&asic->lock, flags);
275}
276
Mark Brown0f76aae2010-12-11 13:08:57 +0000277static void asic3_unmask_irq(struct irq_data *data)
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800278{
Mark Brown0f76aae2010-12-11 13:08:57 +0000279 struct asic3 *asic = irq_data_get_irq_chip_data(data);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800280 int regval;
281 unsigned long flags;
282
283 spin_lock_irqsave(&asic->lock, flags);
284 regval = asic3_read_register(asic,
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200285 ASIC3_INTR_BASE +
286 ASIC3_INTR_INT_MASK);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800287
288 regval |= (ASIC3_INTMASK_MASK0 <<
Mark Brown0f76aae2010-12-11 13:08:57 +0000289 (data->irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800290
291 asic3_write_register(asic,
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200292 ASIC3_INTR_BASE +
293 ASIC3_INTR_INT_MASK,
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800294 regval);
295 spin_unlock_irqrestore(&asic->lock, flags);
296}
297
Mark Brown0f76aae2010-12-11 13:08:57 +0000298static int asic3_gpio_irq_type(struct irq_data *data, unsigned int type)
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800299{
Mark Brown0f76aae2010-12-11 13:08:57 +0000300 struct asic3 *asic = irq_data_get_irq_chip_data(data);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800301 u32 bank, index;
302 u16 trigger, level, edge, bit;
303 unsigned long flags;
304
Mark Brown0f76aae2010-12-11 13:08:57 +0000305 bank = asic3_irq_to_bank(asic, data->irq);
306 index = asic3_irq_to_index(asic, data->irq);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800307 bit = 1<<index;
308
309 spin_lock_irqsave(&asic->lock, flags);
310 level = asic3_read_register(asic,
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200311 bank + ASIC3_GPIO_LEVEL_TRIGGER);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800312 edge = asic3_read_register(asic,
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200313 bank + ASIC3_GPIO_EDGE_TRIGGER);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800314 trigger = asic3_read_register(asic,
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200315 bank + ASIC3_GPIO_TRIGGER_TYPE);
Mark Brown0f76aae2010-12-11 13:08:57 +0000316 asic->irq_bothedge[(data->irq - asic->irq_base) >> 4] &= ~bit;
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800317
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100318 if (type == IRQ_TYPE_EDGE_RISING) {
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800319 trigger |= bit;
320 edge |= bit;
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100321 } else if (type == IRQ_TYPE_EDGE_FALLING) {
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800322 trigger |= bit;
323 edge &= ~bit;
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100324 } else if (type == IRQ_TYPE_EDGE_BOTH) {
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800325 trigger |= bit;
Mark Brown0f76aae2010-12-11 13:08:57 +0000326 if (asic3_gpio_get(&asic->gpio, data->irq - asic->irq_base))
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800327 edge &= ~bit;
328 else
329 edge |= bit;
Mark Brown0f76aae2010-12-11 13:08:57 +0000330 asic->irq_bothedge[(data->irq - asic->irq_base) >> 4] |= bit;
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100331 } else if (type == IRQ_TYPE_LEVEL_LOW) {
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800332 trigger &= ~bit;
333 level &= ~bit;
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100334 } else if (type == IRQ_TYPE_LEVEL_HIGH) {
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800335 trigger &= ~bit;
336 level |= bit;
337 } else {
338 /*
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100339 * if type == IRQ_TYPE_NONE, we should mask interrupts, but
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800340 * be careful to not unmask them if mask was also called.
341 * Probably need internal state for mask.
342 */
Samuel Ortiz24f4f2e2008-06-20 11:11:19 +0200343 dev_notice(asic->dev, "irq type not changed\n");
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800344 }
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200345 asic3_write_register(asic, bank + ASIC3_GPIO_LEVEL_TRIGGER,
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800346 level);
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200347 asic3_write_register(asic, bank + ASIC3_GPIO_EDGE_TRIGGER,
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800348 edge);
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200349 asic3_write_register(asic, bank + ASIC3_GPIO_TRIGGER_TYPE,
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800350 trigger);
351 spin_unlock_irqrestore(&asic->lock, flags);
352 return 0;
353}
354
Paul Parsons2fe372f2012-04-11 00:35:34 +0100355static int asic3_gpio_irq_set_wake(struct irq_data *data, unsigned int on)
356{
357 struct asic3 *asic = irq_data_get_irq_chip_data(data);
358 u32 bank, index;
359 u16 bit;
360
361 bank = asic3_irq_to_bank(asic, data->irq);
362 index = asic3_irq_to_index(asic, data->irq);
363 bit = 1<<index;
364
365 asic3_set_register(asic, bank + ASIC3_GPIO_SLEEP_MASK, bit, !on);
366
367 return 0;
368}
369
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800370static struct irq_chip asic3_gpio_irq_chip = {
371 .name = "ASIC3-GPIO",
Mark Brown0f76aae2010-12-11 13:08:57 +0000372 .irq_ack = asic3_mask_gpio_irq,
373 .irq_mask = asic3_mask_gpio_irq,
374 .irq_unmask = asic3_unmask_gpio_irq,
375 .irq_set_type = asic3_gpio_irq_type,
Paul Parsons2fe372f2012-04-11 00:35:34 +0100376 .irq_set_wake = asic3_gpio_irq_set_wake,
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800377};
378
379static struct irq_chip asic3_irq_chip = {
380 .name = "ASIC3",
Mark Brown0f76aae2010-12-11 13:08:57 +0000381 .irq_ack = asic3_mask_irq,
382 .irq_mask = asic3_mask_irq,
383 .irq_unmask = asic3_unmask_irq,
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800384};
385
Philipp Zabel065032f2008-06-21 00:51:38 +0200386static int __init asic3_irq_probe(struct platform_device *pdev)
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800387{
388 struct asic3 *asic = platform_get_drvdata(pdev);
389 unsigned long clksel = 0;
390 unsigned int irq, irq_base;
Roel Kluinc491b2f2008-07-25 19:44:41 -0700391 int ret;
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800392
Roel Kluinc491b2f2008-07-25 19:44:41 -0700393 ret = platform_get_irq(pdev, 0);
394 if (ret < 0)
395 return ret;
396 asic->irq_nr = ret;
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800397
398 /* turn on clock to IRQ controller */
399 clksel |= CLOCK_SEL_CX;
400 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),
401 clksel);
402
403 irq_base = asic->irq_base;
404
405 for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
406 if (irq < asic->irq_base + ASIC3_NUM_GPIOS)
Thomas Gleixnerd5bb1222011-03-25 11:12:32 +0000407 irq_set_chip(irq, &asic3_gpio_irq_chip);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800408 else
Thomas Gleixnerd5bb1222011-03-25 11:12:32 +0000409 irq_set_chip(irq, &asic3_irq_chip);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800410
Thomas Gleixnerd5bb1222011-03-25 11:12:32 +0000411 irq_set_chip_data(irq, asic);
412 irq_set_handler(irq, handle_level_irq);
Rob Herring9bd09f32015-07-27 15:55:20 -0500413 irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800414 }
415
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200416 asic3_write_register(asic, ASIC3_OFFSET(INTR, INT_MASK),
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800417 ASIC3_INTMASK_GINTMASK);
418
Thomas Gleixnerc30e3042015-06-21 20:16:06 +0200419 irq_set_chained_handler_and_data(asic->irq_nr, asic3_irq_demux, asic);
Thomas Gleixnerd5bb1222011-03-25 11:12:32 +0000420 irq_set_irq_type(asic->irq_nr, IRQ_TYPE_EDGE_RISING);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800421
422 return 0;
423}
424
425static void asic3_irq_remove(struct platform_device *pdev)
426{
427 struct asic3 *asic = platform_get_drvdata(pdev);
428 unsigned int irq, irq_base;
429
430 irq_base = asic->irq_base;
431
432 for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
Rob Herring9bd09f32015-07-27 15:55:20 -0500433 irq_set_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
Thomas Gleixnerd6f7ce9f2011-03-25 11:12:35 +0000434 irq_set_chip_and_handler(irq, NULL, NULL);
Thomas Gleixnerd5bb1222011-03-25 11:12:32 +0000435 irq_set_chip_data(irq, NULL);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800436 }
Thomas Gleixnerd5bb1222011-03-25 11:12:32 +0000437 irq_set_chained_handler(asic->irq_nr, NULL);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800438}
439
440/* GPIOs */
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200441static int asic3_gpio_direction(struct gpio_chip *chip,
442 unsigned offset, int out)
443{
444 u32 mask = ASIC3_GPIO_TO_MASK(offset), out_reg;
445 unsigned int gpio_base;
446 unsigned long flags;
447 struct asic3 *asic;
448
449 asic = container_of(chip, struct asic3, gpio);
450 gpio_base = ASIC3_GPIO_TO_BASE(offset);
451
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200452 if (gpio_base > ASIC3_GPIO_D_BASE) {
Samuel Ortiz24f4f2e2008-06-20 11:11:19 +0200453 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
454 gpio_base, offset);
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200455 return -EINVAL;
456 }
457
458 spin_lock_irqsave(&asic->lock, flags);
459
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200460 out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_DIRECTION);
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200461
462 /* Input is 0, Output is 1 */
463 if (out)
464 out_reg |= mask;
465 else
466 out_reg &= ~mask;
467
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200468 asic3_write_register(asic, gpio_base + ASIC3_GPIO_DIRECTION, out_reg);
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200469
470 spin_unlock_irqrestore(&asic->lock, flags);
471
472 return 0;
473
474}
475
476static int asic3_gpio_direction_input(struct gpio_chip *chip,
477 unsigned offset)
478{
479 return asic3_gpio_direction(chip, offset, 0);
480}
481
482static int asic3_gpio_direction_output(struct gpio_chip *chip,
483 unsigned offset, int value)
484{
485 return asic3_gpio_direction(chip, offset, 1);
486}
487
488static int asic3_gpio_get(struct gpio_chip *chip,
489 unsigned offset)
490{
491 unsigned int gpio_base;
492 u32 mask = ASIC3_GPIO_TO_MASK(offset);
493 struct asic3 *asic;
494
495 asic = container_of(chip, struct asic3, gpio);
496 gpio_base = ASIC3_GPIO_TO_BASE(offset);
497
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200498 if (gpio_base > ASIC3_GPIO_D_BASE) {
Samuel Ortiz24f4f2e2008-06-20 11:11:19 +0200499 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
500 gpio_base, offset);
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200501 return -EINVAL;
502 }
503
Linus Walleijf8e3a512015-12-22 15:47:05 +0100504 return !!(asic3_read_register(asic,
505 gpio_base + ASIC3_GPIO_STATUS) & mask);
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200506}
507
508static void asic3_gpio_set(struct gpio_chip *chip,
509 unsigned offset, int value)
510{
511 u32 mask, out_reg;
512 unsigned int gpio_base;
513 unsigned long flags;
514 struct asic3 *asic;
515
516 asic = container_of(chip, struct asic3, gpio);
517 gpio_base = ASIC3_GPIO_TO_BASE(offset);
518
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200519 if (gpio_base > ASIC3_GPIO_D_BASE) {
Samuel Ortiz24f4f2e2008-06-20 11:11:19 +0200520 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
521 gpio_base, offset);
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200522 return;
523 }
524
525 mask = ASIC3_GPIO_TO_MASK(offset);
526
527 spin_lock_irqsave(&asic->lock, flags);
528
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200529 out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_OUT);
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200530
531 if (value)
532 out_reg |= mask;
533 else
534 out_reg &= ~mask;
535
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200536 asic3_write_register(asic, gpio_base + ASIC3_GPIO_OUT, out_reg);
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200537
538 spin_unlock_irqrestore(&asic->lock, flags);
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200539}
540
Paul Parsons450b1152012-01-31 01:18:35 +0000541static int asic3_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
542{
Dmitry Artamonow02269ab2012-04-12 15:33:34 +0400543 struct asic3 *asic = container_of(chip, struct asic3, gpio);
544
Samuel Ortiz12693f62012-04-16 21:28:29 +0200545 return asic->irq_base + offset;
Paul Parsons450b1152012-01-31 01:18:35 +0000546}
547
Philipp Zabel065032f2008-06-21 00:51:38 +0200548static __init int asic3_gpio_probe(struct platform_device *pdev,
549 u16 *gpio_config, int num)
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800550{
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800551 struct asic3 *asic = platform_get_drvdata(pdev);
Samuel Ortiz3b26bf12008-06-20 11:09:51 +0200552 u16 alt_reg[ASIC3_NUM_GPIO_BANKS];
553 u16 out_reg[ASIC3_NUM_GPIO_BANKS];
554 u16 dir_reg[ASIC3_NUM_GPIO_BANKS];
555 int i;
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800556
Russell King59f0cb02008-10-27 11:24:09 +0000557 memset(alt_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
558 memset(out_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
559 memset(dir_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
Samuel Ortiz3b26bf12008-06-20 11:09:51 +0200560
561 /* Enable all GPIOs */
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200562 asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, MASK), 0xffff);
563 asic3_write_register(asic, ASIC3_GPIO_OFFSET(B, MASK), 0xffff);
564 asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, MASK), 0xffff);
565 asic3_write_register(asic, ASIC3_GPIO_OFFSET(D, MASK), 0xffff);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800566
Samuel Ortiz3b26bf12008-06-20 11:09:51 +0200567 for (i = 0; i < num; i++) {
568 u8 alt, pin, dir, init, bank_num, bit_num;
569 u16 config = gpio_config[i];
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800570
Samuel Ortiz3b26bf12008-06-20 11:09:51 +0200571 pin = ASIC3_CONFIG_GPIO_PIN(config);
572 alt = ASIC3_CONFIG_GPIO_ALT(config);
573 dir = ASIC3_CONFIG_GPIO_DIR(config);
574 init = ASIC3_CONFIG_GPIO_INIT(config);
575
576 bank_num = ASIC3_GPIO_TO_BANK(pin);
577 bit_num = ASIC3_GPIO_TO_BIT(pin);
578
579 alt_reg[bank_num] |= (alt << bit_num);
580 out_reg[bank_num] |= (init << bit_num);
581 dir_reg[bank_num] |= (dir << bit_num);
582 }
583
584 for (i = 0; i < ASIC3_NUM_GPIO_BANKS; i++) {
585 asic3_write_register(asic,
586 ASIC3_BANK_TO_BASE(i) +
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200587 ASIC3_GPIO_DIRECTION,
Samuel Ortiz3b26bf12008-06-20 11:09:51 +0200588 dir_reg[i]);
589 asic3_write_register(asic,
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200590 ASIC3_BANK_TO_BASE(i) + ASIC3_GPIO_OUT,
Samuel Ortiz3b26bf12008-06-20 11:09:51 +0200591 out_reg[i]);
592 asic3_write_register(asic,
593 ASIC3_BANK_TO_BASE(i) +
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200594 ASIC3_GPIO_ALT_FUNCTION,
Samuel Ortiz3b26bf12008-06-20 11:09:51 +0200595 alt_reg[i]);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800596 }
597
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200598 return gpiochip_add(&asic->gpio);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800599}
600
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200601static int asic3_gpio_remove(struct platform_device *pdev)
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800602{
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200603 struct asic3 *asic = platform_get_drvdata(pdev);
604
abdoulaye berthe88d5e522014-07-12 22:30:14 +0200605 gpiochip_remove(&asic->gpio);
606 return 0;
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800607}
608
Paul Parsonsc29a8122011-08-09 16:27:43 +0000609static void asic3_clk_enable(struct asic3 *asic, struct asic3_clk *clk)
Philipp Zabele956a2a2009-06-05 18:31:02 +0200610{
611 unsigned long flags;
612 u32 cdex;
613
614 spin_lock_irqsave(&asic->lock, flags);
615 if (clk->enabled++ == 0) {
616 cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));
617 cdex |= clk->cdex;
618 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex);
619 }
620 spin_unlock_irqrestore(&asic->lock, flags);
Philipp Zabele956a2a2009-06-05 18:31:02 +0200621}
622
623static void asic3_clk_disable(struct asic3 *asic, struct asic3_clk *clk)
624{
625 unsigned long flags;
626 u32 cdex;
627
628 WARN_ON(clk->enabled == 0);
629
630 spin_lock_irqsave(&asic->lock, flags);
631 if (--clk->enabled == 0) {
632 cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));
633 cdex &= ~clk->cdex;
634 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex);
635 }
636 spin_unlock_irqrestore(&asic->lock, flags);
637}
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800638
Philipp Zabel9461f652009-06-15 12:10:24 +0200639/* MFD cells (SPI, PWM, LED, DS1WM, MMC) */
640static struct ds1wm_driver_data ds1wm_pdata = {
641 .active_high = 1,
Jean-François Dagenaisf607e7f2011-07-08 15:39:44 -0700642 .reset_recover_delay = 1,
Philipp Zabel9461f652009-06-15 12:10:24 +0200643};
644
645static struct resource ds1wm_resources[] = {
646 {
647 .start = ASIC3_OWM_BASE,
648 .end = ASIC3_OWM_BASE + 0x13,
649 .flags = IORESOURCE_MEM,
650 },
651 {
652 .start = ASIC3_IRQ_OWM,
Mark Brownfe421422010-12-11 13:00:34 +0000653 .end = ASIC3_IRQ_OWM,
Philipp Zabel9461f652009-06-15 12:10:24 +0200654 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
655 },
656};
657
658static int ds1wm_enable(struct platform_device *pdev)
659{
660 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
661
662 /* Turn on external clocks and the OWM clock */
663 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
664 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
665 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_OWM]);
Lee Jonesd43c4292015-10-28 14:11:23 +0000666 usleep_range(1000, 5000);
Philipp Zabel9461f652009-06-15 12:10:24 +0200667
668 /* Reset and enable DS1WM */
669 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET),
670 ASIC3_EXTCF_OWM_RESET, 1);
Lee Jonesd43c4292015-10-28 14:11:23 +0000671 usleep_range(1000, 5000);
Philipp Zabel9461f652009-06-15 12:10:24 +0200672 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET),
673 ASIC3_EXTCF_OWM_RESET, 0);
Lee Jonesd43c4292015-10-28 14:11:23 +0000674 usleep_range(1000, 5000);
Philipp Zabel9461f652009-06-15 12:10:24 +0200675 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
676 ASIC3_EXTCF_OWM_EN, 1);
Lee Jonesd43c4292015-10-28 14:11:23 +0000677 usleep_range(1000, 5000);
Philipp Zabel9461f652009-06-15 12:10:24 +0200678
679 return 0;
680}
681
682static int ds1wm_disable(struct platform_device *pdev)
683{
684 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
685
686 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
687 ASIC3_EXTCF_OWM_EN, 0);
688
689 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_OWM]);
690 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
691 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
692
693 return 0;
694}
695
Geert Uytterhoeven5ac98552013-11-18 14:33:06 +0100696static const struct mfd_cell asic3_cell_ds1wm = {
Philipp Zabel9461f652009-06-15 12:10:24 +0200697 .name = "ds1wm",
698 .enable = ds1wm_enable,
699 .disable = ds1wm_disable,
Samuel Ortiz121ea572011-04-06 11:41:03 +0200700 .platform_data = &ds1wm_pdata,
701 .pdata_size = sizeof(ds1wm_pdata),
Philipp Zabel9461f652009-06-15 12:10:24 +0200702 .num_resources = ARRAY_SIZE(ds1wm_resources),
703 .resources = ds1wm_resources,
704};
705
Ian Molton64e88672010-01-06 13:51:48 +0100706static void asic3_mmc_pwr(struct platform_device *pdev, int state)
707{
708 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
709
710 tmio_core_mmc_pwr(asic->tmio_cnf, 1 - asic->bus_shift, state);
711}
712
713static void asic3_mmc_clk_div(struct platform_device *pdev, int state)
714{
715 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
716
717 tmio_core_mmc_clk_div(asic->tmio_cnf, 1 - asic->bus_shift, state);
718}
719
Philipp Zabel09f05ce2009-06-15 12:10:25 +0200720static struct tmio_mmc_data asic3_mmc_data = {
Ian Molton64e88672010-01-06 13:51:48 +0100721 .hclk = 24576000,
722 .set_pwr = asic3_mmc_pwr,
723 .set_clk_div = asic3_mmc_clk_div,
Philipp Zabel09f05ce2009-06-15 12:10:25 +0200724};
725
726static struct resource asic3_mmc_resources[] = {
727 {
728 .start = ASIC3_SD_CTRL_BASE,
729 .end = ASIC3_SD_CTRL_BASE + 0x3ff,
730 .flags = IORESOURCE_MEM,
731 },
732 {
Philipp Zabel09f05ce2009-06-15 12:10:25 +0200733 .start = 0,
734 .end = 0,
735 .flags = IORESOURCE_IRQ,
736 },
737};
738
739static int asic3_mmc_enable(struct platform_device *pdev)
740{
741 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
742
743 /* Not sure if it must be done bit by bit, but leaving as-is */
744 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
745 ASIC3_SDHWCTRL_LEVCD, 1);
746 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
747 ASIC3_SDHWCTRL_LEVWP, 1);
748 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
749 ASIC3_SDHWCTRL_SUSPEND, 0);
750 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
751 ASIC3_SDHWCTRL_PCLR, 0);
752
753 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
754 /* CLK32 used for card detection and for interruption detection
755 * when HCLK is stopped.
756 */
757 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
Lee Jonesd43c4292015-10-28 14:11:23 +0000758 usleep_range(1000, 5000);
Philipp Zabel09f05ce2009-06-15 12:10:25 +0200759
760 /* HCLK 24.576 MHz, BCLK 12.288 MHz: */
761 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),
762 CLOCK_SEL_CX | CLOCK_SEL_SD_HCLK_SEL);
763
764 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]);
765 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]);
Lee Jonesd43c4292015-10-28 14:11:23 +0000766 usleep_range(1000, 5000);
Philipp Zabel09f05ce2009-06-15 12:10:25 +0200767
768 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
769 ASIC3_EXTCF_SD_MEM_ENABLE, 1);
770
771 /* Enable SD card slot 3.3V power supply */
772 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
773 ASIC3_SDHWCTRL_SDPWR, 1);
774
Ian Molton64e88672010-01-06 13:51:48 +0100775 /* ASIC3_SD_CTRL_BASE assumes 32-bit addressing, TMIO is 16-bit */
776 tmio_core_mmc_enable(asic->tmio_cnf, 1 - asic->bus_shift,
777 ASIC3_SD_CTRL_BASE >> 1);
778
Philipp Zabel09f05ce2009-06-15 12:10:25 +0200779 return 0;
780}
781
782static int asic3_mmc_disable(struct platform_device *pdev)
783{
784 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
785
786 /* Put in suspend mode */
787 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
788 ASIC3_SDHWCTRL_SUSPEND, 1);
789
790 /* Disable clocks */
791 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]);
792 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]);
793 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
794 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
795 return 0;
796}
797
Geert Uytterhoeven5ac98552013-11-18 14:33:06 +0100798static const struct mfd_cell asic3_cell_mmc = {
Philipp Zabel09f05ce2009-06-15 12:10:25 +0200799 .name = "tmio-mmc",
800 .enable = asic3_mmc_enable,
801 .disable = asic3_mmc_disable,
Paul Parsons3c6e3652011-08-09 16:27:24 +0000802 .suspend = asic3_mmc_disable,
803 .resume = asic3_mmc_enable,
Samuel Ortizec719742011-04-06 11:38:14 +0200804 .platform_data = &asic3_mmc_data,
805 .pdata_size = sizeof(asic3_mmc_data),
Philipp Zabel09f05ce2009-06-15 12:10:25 +0200806 .num_resources = ARRAY_SIZE(asic3_mmc_resources),
807 .resources = asic3_mmc_resources,
808};
809
Paul Parsons13ca4f62011-05-13 18:53:03 +0000810static const int clock_ledn[ASIC3_NUM_LEDS] = {
811 [0] = ASIC3_CLOCK_LED0,
812 [1] = ASIC3_CLOCK_LED1,
813 [2] = ASIC3_CLOCK_LED2,
814};
815
816static int asic3_leds_enable(struct platform_device *pdev)
817{
818 const struct mfd_cell *cell = mfd_get_cell(pdev);
819 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
820
821 asic3_clk_enable(asic, &asic->clocks[clock_ledn[cell->id]]);
822
823 return 0;
824}
825
826static int asic3_leds_disable(struct platform_device *pdev)
827{
828 const struct mfd_cell *cell = mfd_get_cell(pdev);
829 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
830
831 asic3_clk_disable(asic, &asic->clocks[clock_ledn[cell->id]]);
832
833 return 0;
834}
835
Paul Parsonse0b13b52011-08-09 16:27:33 +0000836static int asic3_leds_suspend(struct platform_device *pdev)
837{
838 const struct mfd_cell *cell = mfd_get_cell(pdev);
839 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
840
841 while (asic3_gpio_get(&asic->gpio, ASIC3_GPIO(C, cell->id)) != 0)
Lee Jonesd43c4292015-10-28 14:11:23 +0000842 usleep_range(1000, 5000);
Paul Parsonse0b13b52011-08-09 16:27:33 +0000843
844 asic3_clk_disable(asic, &asic->clocks[clock_ledn[cell->id]]);
845
846 return 0;
847}
848
Paul Parsons13ca4f62011-05-13 18:53:03 +0000849static struct mfd_cell asic3_cell_leds[ASIC3_NUM_LEDS] = {
850 [0] = {
851 .name = "leds-asic3",
852 .id = 0,
853 .enable = asic3_leds_enable,
854 .disable = asic3_leds_disable,
Paul Parsonse0b13b52011-08-09 16:27:33 +0000855 .suspend = asic3_leds_suspend,
856 .resume = asic3_leds_enable,
Paul Parsons13ca4f62011-05-13 18:53:03 +0000857 },
858 [1] = {
859 .name = "leds-asic3",
860 .id = 1,
861 .enable = asic3_leds_enable,
862 .disable = asic3_leds_disable,
Paul Parsonse0b13b52011-08-09 16:27:33 +0000863 .suspend = asic3_leds_suspend,
864 .resume = asic3_leds_enable,
Paul Parsons13ca4f62011-05-13 18:53:03 +0000865 },
866 [2] = {
867 .name = "leds-asic3",
868 .id = 2,
869 .enable = asic3_leds_enable,
870 .disable = asic3_leds_disable,
Paul Parsonse0b13b52011-08-09 16:27:33 +0000871 .suspend = asic3_leds_suspend,
872 .resume = asic3_leds_enable,
Paul Parsons13ca4f62011-05-13 18:53:03 +0000873 },
874};
875
Philipp Zabel9461f652009-06-15 12:10:24 +0200876static int __init asic3_mfd_probe(struct platform_device *pdev,
Paul Parsons13ca4f62011-05-13 18:53:03 +0000877 struct asic3_platform_data *pdata,
Philipp Zabel9461f652009-06-15 12:10:24 +0200878 struct resource *mem)
879{
880 struct asic3 *asic = platform_get_drvdata(pdev);
Philipp Zabel09f05ce2009-06-15 12:10:25 +0200881 struct resource *mem_sdio;
882 int irq, ret;
883
884 mem_sdio = platform_get_resource(pdev, IORESOURCE_MEM, 1);
885 if (!mem_sdio)
886 dev_dbg(asic->dev, "no SDIO MEM resource\n");
887
888 irq = platform_get_irq(pdev, 1);
889 if (irq < 0)
890 dev_dbg(asic->dev, "no SDIO IRQ resource\n");
Philipp Zabel9461f652009-06-15 12:10:24 +0200891
892 /* DS1WM */
893 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
894 ASIC3_EXTCF_OWM_SMB, 0);
895
896 ds1wm_resources[0].start >>= asic->bus_shift;
897 ds1wm_resources[0].end >>= asic->bus_shift;
898
Philipp Zabel09f05ce2009-06-15 12:10:25 +0200899 /* MMC */
Sachin Kamat44b61a92014-06-10 15:30:34 +0530900 if (mem_sdio) {
Lee Jonesd43c4292015-10-28 14:11:23 +0000901 asic->tmio_cnf = ioremap((ASIC3_SD_CONFIG_BASE >>
902 asic->bus_shift) + mem_sdio->start,
Paul Parsons74e32d12011-05-15 14:13:11 +0000903 ASIC3_SD_CONFIG_SIZE >> asic->bus_shift);
Sachin Kamat44b61a92014-06-10 15:30:34 +0530904 if (!asic->tmio_cnf) {
905 ret = -ENOMEM;
906 dev_dbg(asic->dev, "Couldn't ioremap SD_CONFIG\n");
907 goto out;
908 }
Ian Molton64e88672010-01-06 13:51:48 +0100909 }
Philipp Zabel09f05ce2009-06-15 12:10:25 +0200910 asic3_mmc_resources[0].start >>= asic->bus_shift;
911 asic3_mmc_resources[0].end >>= asic->bus_shift;
Philipp Zabel09f05ce2009-06-15 12:10:25 +0200912
Paul Parsons4f304242012-04-09 13:18:31 +0100913 if (pdata->clock_rate) {
914 ds1wm_pdata.clock_rate = pdata->clock_rate;
915 ret = mfd_add_devices(&pdev->dev, pdev->id,
Mark Brown0848c942012-09-11 15:16:36 +0800916 &asic3_cell_ds1wm, 1, mem, asic->irq_base, NULL);
Paul Parsons4f304242012-04-09 13:18:31 +0100917 if (ret < 0)
918 goto out;
919 }
Philipp Zabel9461f652009-06-15 12:10:24 +0200920
Paul Parsons13ca4f62011-05-13 18:53:03 +0000921 if (mem_sdio && (irq >= 0)) {
Philipp Zabel09f05ce2009-06-15 12:10:25 +0200922 ret = mfd_add_devices(&pdev->dev, pdev->id,
Mark Brown0848c942012-09-11 15:16:36 +0800923 &asic3_cell_mmc, 1, mem_sdio, irq, NULL);
Paul Parsons13ca4f62011-05-13 18:53:03 +0000924 if (ret < 0)
925 goto out;
926 }
927
Arnd Bergmannb2f0fa82012-08-04 06:20:49 +0000928 ret = 0;
Paul Parsons13ca4f62011-05-13 18:53:03 +0000929 if (pdata->leds) {
930 int i;
931
932 for (i = 0; i < ASIC3_NUM_LEDS; ++i) {
933 asic3_cell_leds[i].platform_data = &pdata->leds[i];
934 asic3_cell_leds[i].pdata_size = sizeof(pdata->leds[i]);
935 }
936 ret = mfd_add_devices(&pdev->dev, 0,
Mark Brown0848c942012-09-11 15:16:36 +0800937 asic3_cell_leds, ASIC3_NUM_LEDS, NULL, 0, NULL);
Paul Parsons13ca4f62011-05-13 18:53:03 +0000938 }
Philipp Zabel09f05ce2009-06-15 12:10:25 +0200939
940 out:
Philipp Zabel9461f652009-06-15 12:10:24 +0200941 return ret;
942}
943
944static void asic3_mfd_remove(struct platform_device *pdev)
945{
Ian Molton64e88672010-01-06 13:51:48 +0100946 struct asic3 *asic = platform_get_drvdata(pdev);
947
Philipp Zabel9461f652009-06-15 12:10:24 +0200948 mfd_remove_devices(&pdev->dev);
Ian Molton64e88672010-01-06 13:51:48 +0100949 iounmap(asic->tmio_cnf);
Philipp Zabel9461f652009-06-15 12:10:24 +0200950}
951
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800952/* Core */
Philipp Zabel065032f2008-06-21 00:51:38 +0200953static int __init asic3_probe(struct platform_device *pdev)
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800954{
Jingoo Han334a41c2013-07-30 17:10:05 +0900955 struct asic3_platform_data *pdata = dev_get_platdata(&pdev->dev);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800956 struct asic3 *asic;
957 struct resource *mem;
958 unsigned long clksel;
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200959 int ret = 0;
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800960
Lee Jones1cee87f2013-05-23 16:25:09 +0100961 asic = devm_kzalloc(&pdev->dev,
962 sizeof(struct asic3), GFP_KERNEL);
Lee Jonesd43c4292015-10-28 14:11:23 +0000963 if (!asic)
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800964 return -ENOMEM;
965
966 spin_lock_init(&asic->lock);
967 platform_set_drvdata(pdev, asic);
968 asic->dev = &pdev->dev;
969
970 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
971 if (!mem) {
Samuel Ortiz24f4f2e2008-06-20 11:11:19 +0200972 dev_err(asic->dev, "no MEM resource\n");
Lee Jones1cee87f2013-05-23 16:25:09 +0100973 return -ENOMEM;
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800974 }
975
Philipp Zabelbe584bd2009-06-05 18:31:04 +0200976 asic->mapping = ioremap(mem->start, resource_size(mem));
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800977 if (!asic->mapping) {
Samuel Ortiz24f4f2e2008-06-20 11:11:19 +0200978 dev_err(asic->dev, "Couldn't ioremap\n");
Lee Jones1cee87f2013-05-23 16:25:09 +0100979 return -ENOMEM;
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800980 }
981
982 asic->irq_base = pdata->irq_base;
983
Philipp Zabel99cdb0c2008-07-10 02:17:02 +0200984 /* calculate bus shift from mem resource */
Philipp Zabelbe584bd2009-06-05 18:31:04 +0200985 asic->bus_shift = 2 - (resource_size(mem) >> 12);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800986
987 clksel = 0;
988 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel);
989
990 ret = asic3_irq_probe(pdev);
991 if (ret < 0) {
Samuel Ortiz24f4f2e2008-06-20 11:11:19 +0200992 dev_err(asic->dev, "Couldn't probe IRQs\n");
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200993 goto out_unmap;
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800994 }
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200995
Paul Parsonsd8e4a882011-08-09 16:27:50 +0000996 asic->gpio.label = "asic3";
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200997 asic->gpio.base = pdata->gpio_base;
998 asic->gpio.ngpio = ASIC3_NUM_GPIOS;
999 asic->gpio.get = asic3_gpio_get;
1000 asic->gpio.set = asic3_gpio_set;
1001 asic->gpio.direction_input = asic3_gpio_direction_input;
1002 asic->gpio.direction_output = asic3_gpio_direction_output;
Paul Parsons450b1152012-01-31 01:18:35 +00001003 asic->gpio.to_irq = asic3_gpio_to_irq;
Samuel Ortiz6f2384c2008-06-20 11:02:19 +02001004
Samuel Ortiz3b26bf12008-06-20 11:09:51 +02001005 ret = asic3_gpio_probe(pdev,
1006 pdata->gpio_config,
1007 pdata->gpio_config_num);
Samuel Ortiz6f2384c2008-06-20 11:02:19 +02001008 if (ret < 0) {
Samuel Ortiz24f4f2e2008-06-20 11:11:19 +02001009 dev_err(asic->dev, "GPIO probe failed\n");
Samuel Ortiz6f2384c2008-06-20 11:02:19 +02001010 goto out_irq;
1011 }
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -08001012
Philipp Zabele956a2a2009-06-05 18:31:02 +02001013 /* Making a per-device copy is only needed for the
1014 * theoretical case of multiple ASIC3s on one board:
1015 */
1016 memcpy(asic->clocks, asic3_clk_init, sizeof(asic3_clk_init));
1017
Paul Parsons13ca4f62011-05-13 18:53:03 +00001018 asic3_mfd_probe(pdev, pdata, mem);
Philipp Zabel9461f652009-06-15 12:10:24 +02001019
Paul Parsonsf22a9c62012-04-05 17:45:04 +01001020 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
1021 (ASIC3_EXTCF_CF0_BUF_EN|ASIC3_EXTCF_CF0_PWAIT_EN), 1);
1022
Samuel Ortiz24f4f2e2008-06-20 11:11:19 +02001023 dev_info(asic->dev, "ASIC3 Core driver\n");
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -08001024
1025 return 0;
1026
Samuel Ortiz6f2384c2008-06-20 11:02:19 +02001027 out_irq:
1028 asic3_irq_remove(pdev);
1029
1030 out_unmap:
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -08001031 iounmap(asic->mapping);
Samuel Ortiz6f2384c2008-06-20 11:02:19 +02001032
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -08001033 return ret;
1034}
1035
Bill Pemberton4740f732012-11-19 13:26:01 -05001036static int asic3_remove(struct platform_device *pdev)
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -08001037{
Samuel Ortiz6f2384c2008-06-20 11:02:19 +02001038 int ret;
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -08001039 struct asic3 *asic = platform_get_drvdata(pdev);
1040
Paul Parsonsf22a9c62012-04-05 17:45:04 +01001041 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
1042 (ASIC3_EXTCF_CF0_BUF_EN|ASIC3_EXTCF_CF0_PWAIT_EN), 0);
1043
Philipp Zabel9461f652009-06-15 12:10:24 +02001044 asic3_mfd_remove(pdev);
1045
Samuel Ortiz6f2384c2008-06-20 11:02:19 +02001046 ret = asic3_gpio_remove(pdev);
1047 if (ret < 0)
1048 return ret;
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -08001049 asic3_irq_remove(pdev);
1050
1051 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), 0);
1052
1053 iounmap(asic->mapping);
1054
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -08001055 return 0;
1056}
1057
1058static void asic3_shutdown(struct platform_device *pdev)
1059{
1060}
1061
1062static struct platform_driver asic3_device_driver = {
1063 .driver = {
1064 .name = "asic3",
1065 },
Bill Pemberton84449212012-11-19 13:20:24 -05001066 .remove = asic3_remove,
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -08001067 .shutdown = asic3_shutdown,
1068};
1069
1070static int __init asic3_init(void)
1071{
1072 int retval = 0;
Lee Jonesd43c4292015-10-28 14:11:23 +00001073
Philipp Zabel065032f2008-06-21 00:51:38 +02001074 retval = platform_driver_probe(&asic3_device_driver, asic3_probe);
Lee Jonesd43c4292015-10-28 14:11:23 +00001075
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -08001076 return retval;
1077}
1078
1079subsys_initcall(asic3_init);