blob: d2f5e7e3703efe4001c770b080260537159712ce [file] [log] [blame]
Noam Camus09dcd192016-11-16 08:31:11 +02001/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef SOC_NPS_MTM_H
34#define SOC_NPS_MTM_H
35
36#define CTOP_INST_HWSCHD_OFF_R3 0x3B6F00BF
37#define CTOP_INST_HWSCHD_RESTORE_R3 0x3E6F70C3
38
39static inline void hw_schd_save(unsigned int *flags)
40{
41 __asm__ __volatile__(
42 " .word %1\n"
43 " st r3,[%0]\n"
44 :
45 : "r"(flags), "i"(CTOP_INST_HWSCHD_OFF_R3)
46 : "r3", "memory");
47}
48
49static inline void hw_schd_restore(unsigned int flags)
50{
51 __asm__ __volatile__(
52 " mov r3, %0\n"
53 " .word %1\n"
54 :
55 : "r"(flags), "i"(CTOP_INST_HWSCHD_RESTORE_R3)
56 : "r3");
57}
58
59#endif /* SOC_NPS_MTM_H */