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gerrit-public.fairphone.software / kernel / msm-4.19 / 649a59cf9be6dc923b660a65c778900a59d40815 / . / arch / arm / boot / dts / wm8850.dtsi
blob: 297aa05800da113d52adaa4a9df4ad80f4f8ecb6 [file] [log] [blame]
Tony Priskdef4d6c2013-01-19 19:44:28 +1300[diff] [blame]1/*
2 * wm8850.dtsi - Device tree file for Wondermedia WM8850 SoC
3 *
4 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
5 *
6 * Licensed under GPLv2 or later
7 */
8
9/include/ "skeleton.dtsi"
10
11/ {
12 compatible = "wm,wm8850";
13
14 aliases {
15 serial0 = &uart0;
16 serial1 = &uart1;
17 serial2 = &uart2;
18 serial3 = &uart3;
19 };
20
21 soc {
22 #address-cells = <1>;
23 #size-cells = <1>;
24 compatible = "simple-bus";
25 ranges;
26 interrupt-parent = <&intc0>;
27
28 intc0: interrupt-controller@d8140000 {
29 compatible = "via,vt8500-intc";
30 interrupt-controller;
31 reg = <0xd8140000 0x10000>;
32 #interrupt-cells = <1>;
33 };
34
35 /* Secondary IC cascaded to intc0 */
36 intc1: interrupt-controller@d8150000 {
37 compatible = "via,vt8500-intc";
38 interrupt-controller;
39 #interrupt-cells = <1>;
40 reg = <0xD8150000 0x10000>;
41 interrupts = <56 57 58 59 60 61 62 63>;
42 };
43
44 gpio: gpio-controller@d8110000 {
45 compatible = "wm,wm8650-gpio";
46 gpio-controller;
47 reg = <0xd8110000 0x10000>;
48 #gpio-cells = <3>;
49 };
50
Tony Prisk649a59c2013-02-20 09:52:23 +1300[diff] [blame^]51 pinctrl: pinctrl@d8110000 {
52 compatible = "wm,wm8850-pinctrl";
53 reg = <0xd8110000 0x10000>;
54 interrupt-controller;
55 #interrupt-cells = <2>;
56 gpio-controller;
57 #gpio-cells = <2>;
58 };
59
Tony Priskdef4d6c2013-01-19 19:44:28 +1300[diff] [blame]60 pmc@d8130000 {
61 compatible = "via,vt8500-pmc";
62 reg = <0xd8130000 0x1000>;
63
64 clocks {
65 #address-cells = <1>;
66 #size-cells = <0>;
67
68 ref25: ref25M {
69 #clock-cells = <0>;
70 compatible = "fixed-clock";
71 clock-frequency = <25000000>;
72 };
73
74 ref24: ref24M {
75 #clock-cells = <0>;
76 compatible = "fixed-clock";
77 clock-frequency = <24000000>;
78 };
79
80 plla: plla {
81 #clock-cells = <0>;
82 compatible = "wm,wm8750-pll-clock";
83 clocks = <&ref25>;
84 reg = <0x200>;
85 };
86
87 pllb: pllb {
88 #clock-cells = <0>;
89 compatible = "wm,wm8750-pll-clock";
90 clocks = <&ref25>;
91 reg = <0x204>;
92 };
93
94 clkuart0: uart0 {
95 #clock-cells = <0>;
96 compatible = "via,vt8500-device-clock";
97 clocks = <&ref24>;
98 enable-reg = <0x254>;
99 enable-bit = <24>;
100 };
101
102 clkuart1: uart1 {
103 #clock-cells = <0>;
104 compatible = "via,vt8500-device-clock";
105 clocks = <&ref24>;
106 enable-reg = <0x254>;
107 enable-bit = <25>;
108 };
109
110 clkuart2: uart2 {
111 #clock-cells = <0>;
112 compatible = "via,vt8500-device-clock";
113 clocks = <&ref24>;
114 enable-reg = <0x254>;
115 enable-bit = <26>;
116 };
117
118 clkuart3: uart3 {
119 #clock-cells = <0>;
120 compatible = "via,vt8500-device-clock";
121 clocks = <&ref24>;
122 enable-reg = <0x254>;
123 enable-bit = <27>;
124 };
125
126 clkpwm: pwm {
127 #clock-cells = <0>;
128 compatible = "via,vt8500-device-clock";
129 clocks = <&pllb>;
130 divisor-reg = <0x350>;
131 enable-reg = <0x250>;
132 enable-bit = <17>;
133 };
134
135 clksdhc: sdhc {
136 #clock-cells = <0>;
137 compatible = "via,vt8500-device-clock";
138 clocks = <&pllb>;
139 divisor-reg = <0x330>;
140 divisor-mask = <0x3f>;
141 enable-reg = <0x250>;
142 enable-bit = <0>;
143 };
144 };
145 };
146
147 fb@d8051700 {
148 compatible = "wm,wm8505-fb";
149 reg = <0xd8051700 0x200>;
150 display = <&display>;
151 default-mode = <&mode0>;
152 };
153
154 ge_rops@d8050400 {
155 compatible = "wm,prizm-ge-rops";
156 reg = <0xd8050400 0x100>;
157 };
158
159 pwm: pwm@d8220000 {
160 #pwm-cells = <3>;
161 compatible = "via,vt8500-pwm";
162 reg = <0xd8220000 0x100>;
163 clocks = <&clkpwm>;
164 };
165
166 timer@d8130100 {
167 compatible = "via,vt8500-timer";
168 reg = <0xd8130100 0x28>;
169 interrupts = <36>;
170 };
171
172 ehci@d8007900 {
173 compatible = "via,vt8500-ehci";
174 reg = <0xd8007900 0x200>;
175 interrupts = <26>;
176 };
177
178 uhci@d8007b00 {
179 compatible = "platform-uhci";
180 reg = <0xd8007b00 0x200>;
181 interrupts = <26>;
182 };
183
184 uhci@d8008d00 {
185 compatible = "platform-uhci";
186 reg = <0xd8008d00 0x200>;
187 interrupts = <26>;
188 };
189
190 uart0: uart@d8200000 {
191 compatible = "via,vt8500-uart";
192 reg = <0xd8200000 0x1040>;
193 interrupts = <32>;
194 clocks = <&clkuart0>;
195 };
196
197 uart1: uart@d82b0000 {
198 compatible = "via,vt8500-uart";
199 reg = <0xd82b0000 0x1040>;
200 interrupts = <33>;
201 clocks = <&clkuart1>;
202 };
203
204 uart2: uart@d8210000 {
205 compatible = "via,vt8500-uart";
206 reg = <0xd8210000 0x1040>;
207 interrupts = <47>;
208 clocks = <&clkuart2>;
209 };
210
211 uart3: uart@d82c0000 {
212 compatible = "via,vt8500-uart";
213 reg = <0xd82c0000 0x1040>;
214 interrupts = <50>;
215 clocks = <&clkuart3>;
216 };
217
218 rtc@d8100000 {
219 compatible = "via,vt8500-rtc";
220 reg = <0xd8100000 0x10000>;
221 interrupts = <48>;
222 };
223
224 sdhc@d800a000 {
225 compatible = "wm,wm8505-sdhc";
226 reg = <0xd800a000 0x1000>;
227 interrupts = <20 21>;
228 clocks = <&clksdhc>;
229 bus-width = <4>;
230 sdon-inverted;
231 };
232 };
233};