blob: a2dd218e35b9e07dcbe3ce3c20c94907a642b878 [file] [log] [blame]
Alex Deucher97b2e202015-04-20 16:51:00 -04001/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
31#include <linux/atomic.h>
32#include <linux/wait.h>
33#include <linux/list.h>
34#include <linux/kref.h>
Christian Königa9f87f62017-03-30 14:03:59 +020035#include <linux/rbtree.h>
Alex Deucher97b2e202015-04-20 16:51:00 -040036#include <linux/hashtable.h>
Chris Wilsonf54d1862016-10-25 13:00:45 +010037#include <linux/dma-fence.h>
Alex Deucher97b2e202015-04-20 16:51:00 -040038
39#include <ttm/ttm_bo_api.h>
40#include <ttm/ttm_bo_driver.h>
41#include <ttm/ttm_placement.h>
42#include <ttm/ttm_module.h>
43#include <ttm/ttm_execbuf_util.h>
44
Chunming Zhoud03846a2015-07-28 14:20:03 -040045#include <drm/drmP.h>
Alex Deucher97b2e202015-04-20 16:51:00 -040046#include <drm/drm_gem.h>
Chunming Zhou7e5a5472015-04-24 17:37:30 +080047#include <drm/amdgpu_drm.h>
Alex Deucher97b2e202015-04-20 16:51:00 -040048
yanyang15fc3aee2015-05-22 14:39:35 -040049#include "amd_shared.h"
Alex Deucher97b2e202015-04-20 16:51:00 -040050#include "amdgpu_mode.h"
51#include "amdgpu_ih.h"
52#include "amdgpu_irq.h"
53#include "amdgpu_ucode.h"
Flora Cuic632d792016-08-02 11:32:41 +080054#include "amdgpu_ttm.h"
Huang Rui0e5ca0d2017-03-03 18:37:23 -050055#include "amdgpu_psp.h"
Alex Deucher97b2e202015-04-20 16:51:00 -040056#include "amdgpu_gds.h"
Christian König56113502016-09-28 12:36:44 +020057#include "amdgpu_sync.h"
Christian König78023012016-09-28 15:33:18 +020058#include "amdgpu_ring.h"
Christian König073440d2016-09-28 15:41:50 +020059#include "amdgpu_vm.h"
Alex Deucher1f7371b2015-12-02 17:46:21 -050060#include "amd_powerplay.h"
Alex Deuchercf0978812016-10-07 11:40:09 -040061#include "amdgpu_dpm.h"
Maruthi Bayyavarapua8fe58c2015-09-22 17:05:20 -040062#include "amdgpu_acp.h"
Leo Liu4df654d2017-01-02 10:07:33 -050063#include "amdgpu_uvd.h"
Leo Liu5e568172017-01-10 11:02:58 -050064#include "amdgpu_vce.h"
Alex Deucher97b2e202015-04-20 16:51:00 -040065
Alex Deucherb80d8472015-08-16 22:55:02 -040066#include "gpu_scheduler.h"
Monk Liuceeb50e2016-09-19 12:13:58 +080067#include "amdgpu_virt.h"
Alex Deucherb80d8472015-08-16 22:55:02 -040068
Alex Deucher97b2e202015-04-20 16:51:00 -040069/*
70 * Modules parameters.
71 */
72extern int amdgpu_modeset;
73extern int amdgpu_vram_limit;
74extern int amdgpu_gart_size;
Marek Olšák95844d22016-08-17 23:49:27 +020075extern int amdgpu_moverate;
Alex Deucher97b2e202015-04-20 16:51:00 -040076extern int amdgpu_benchmarking;
77extern int amdgpu_testing;
78extern int amdgpu_audio;
79extern int amdgpu_disp_priority;
80extern int amdgpu_hw_i2c;
81extern int amdgpu_pcie_gen2;
82extern int amdgpu_msi;
83extern int amdgpu_lockup_timeout;
84extern int amdgpu_dpm;
Huang Ruie635ee02016-11-01 15:35:38 +080085extern int amdgpu_fw_load_type;
Alex Deucher97b2e202015-04-20 16:51:00 -040086extern int amdgpu_aspm;
87extern int amdgpu_runtime_pm;
Alex Deucher97b2e202015-04-20 16:51:00 -040088extern unsigned amdgpu_ip_block_mask;
89extern int amdgpu_bapm;
90extern int amdgpu_deep_color;
91extern int amdgpu_vm_size;
92extern int amdgpu_vm_block_size;
Christian Königd9c13152015-09-28 12:31:26 +020093extern int amdgpu_vm_fault_stop;
Christian Königb495bd32015-09-10 14:00:35 +020094extern int amdgpu_vm_debug;
Jammy Zhou1333f722015-07-30 16:36:58 +080095extern int amdgpu_sched_jobs;
Jammy Zhou4afcb302015-07-30 16:44:05 +080096extern int amdgpu_sched_hw_submission;
Rex Zhu3ca67302016-11-02 13:38:37 +080097extern int amdgpu_no_evict;
98extern int amdgpu_direct_gma_size;
Alex Deuchercd474ba2016-02-04 10:21:23 -050099extern unsigned amdgpu_pcie_gen_cap;
100extern unsigned amdgpu_pcie_lane_cap;
Nicolai Hähnle395d1fb2016-06-02 12:32:07 +0200101extern unsigned amdgpu_cg_mask;
102extern unsigned amdgpu_pg_mask;
Nicolai Hähnle6f8941a2016-06-17 19:31:33 +0200103extern char *amdgpu_disable_cu;
Emily Deng9accf2f2016-08-10 16:01:25 +0800104extern char *amdgpu_virtual_display;
Rex Zhu5141e9d2016-09-06 16:34:37 +0800105extern unsigned amdgpu_pp_feature_mask;
Christian König6a7f76e2016-08-24 15:51:49 +0200106extern int amdgpu_vram_page_split;
Alex Deucherbce23e02017-03-28 12:52:08 -0400107extern int amdgpu_ngg;
108extern int amdgpu_prim_buf_per_se;
109extern int amdgpu_pos_buf_per_se;
110extern int amdgpu_cntl_sb_buf_per_se;
111extern int amdgpu_param_buf_per_se;
Monk Liu65781c72017-05-11 13:36:44 +0800112extern int amdgpu_job_hang_limit;
Alex Deucher97b2e202015-04-20 16:51:00 -0400113
Chunming Zhou55ed8caf2017-04-21 16:40:00 +0800114#define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */
Chunming Zhou4b559c92015-07-21 15:53:04 +0800115#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
Alex Deucher97b2e202015-04-20 16:51:00 -0400116#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
117#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
118/* AMDGPU_IB_POOL_SIZE must be a power of 2 */
119#define AMDGPU_IB_POOL_SIZE 16
120#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
121#define AMDGPUFB_CONN_LIMIT 4
Alex Deuchera5bde2f2016-09-23 16:23:41 -0400122#define AMDGPU_BIOS_NUM_SCRATCH 16
Alex Deucher97b2e202015-04-20 16:51:00 -0400123
Jammy Zhou36f523a2015-09-01 12:54:27 +0800124/* max number of IP instances */
125#define AMDGPU_MAX_SDMA_INSTANCES 2
126
Alex Deucher97b2e202015-04-20 16:51:00 -0400127/* hard reset data */
128#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
129
130/* reset flags */
131#define AMDGPU_RESET_GFX (1 << 0)
132#define AMDGPU_RESET_COMPUTE (1 << 1)
133#define AMDGPU_RESET_DMA (1 << 2)
134#define AMDGPU_RESET_CP (1 << 3)
135#define AMDGPU_RESET_GRBM (1 << 4)
136#define AMDGPU_RESET_DMA1 (1 << 5)
137#define AMDGPU_RESET_RLC (1 << 6)
138#define AMDGPU_RESET_SEM (1 << 7)
139#define AMDGPU_RESET_IH (1 << 8)
140#define AMDGPU_RESET_VMC (1 << 9)
141#define AMDGPU_RESET_MC (1 << 10)
142#define AMDGPU_RESET_DISPLAY (1 << 11)
143#define AMDGPU_RESET_UVD (1 << 12)
144#define AMDGPU_RESET_VCE (1 << 13)
145#define AMDGPU_RESET_VCE1 (1 << 14)
146
Alex Deucher97b2e202015-04-20 16:51:00 -0400147/* GFX current status */
148#define AMDGPU_GFX_NORMAL_MODE 0x00000000L
149#define AMDGPU_GFX_SAFE_MODE 0x00000001L
150#define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
151#define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
152#define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
153
154/* max cursor sizes (in pixels) */
155#define CIK_CURSOR_WIDTH 128
156#define CIK_CURSOR_HEIGHT 128
157
158struct amdgpu_device;
Alex Deucher97b2e202015-04-20 16:51:00 -0400159struct amdgpu_ib;
Alex Deucher97b2e202015-04-20 16:51:00 -0400160struct amdgpu_cs_parser;
Chunming Zhoubb977d32015-08-18 15:16:40 +0800161struct amdgpu_job;
Alex Deucher97b2e202015-04-20 16:51:00 -0400162struct amdgpu_irq_src;
Alex Deucher0b492a42015-08-16 22:48:26 -0400163struct amdgpu_fpriv;
Alex Deucher97b2e202015-04-20 16:51:00 -0400164
165enum amdgpu_cp_irq {
166 AMDGPU_CP_IRQ_GFX_EOP = 0,
167 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
168 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
169 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
170 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
171 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
172 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
173 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
174 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
175
176 AMDGPU_CP_IRQ_LAST
177};
178
179enum amdgpu_sdma_irq {
180 AMDGPU_SDMA_IRQ_TRAP0 = 0,
181 AMDGPU_SDMA_IRQ_TRAP1,
182
183 AMDGPU_SDMA_IRQ_LAST
184};
185
186enum amdgpu_thermal_irq {
187 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
188 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
189
190 AMDGPU_THERMAL_IRQ_LAST
191};
192
Xiangliang Yu4e638ae2016-12-23 15:00:01 +0800193enum amdgpu_kiq_irq {
194 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
195 AMDGPU_CP_KIQ_IRQ_LAST
196};
197
Alex Deucher97b2e202015-04-20 16:51:00 -0400198int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
yanyang15fc3aee2015-05-22 14:39:35 -0400199 enum amd_ip_block_type block_type,
200 enum amd_clockgating_state state);
Alex Deucher97b2e202015-04-20 16:51:00 -0400201int amdgpu_set_powergating_state(struct amdgpu_device *adev,
yanyang15fc3aee2015-05-22 14:39:35 -0400202 enum amd_ip_block_type block_type,
203 enum amd_powergating_state state);
Huang Rui6cb2d4e2017-01-05 18:44:41 +0800204void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags);
Alex Deucher5dbbb602016-06-23 11:41:04 -0400205int amdgpu_wait_for_idle(struct amdgpu_device *adev,
206 enum amd_ip_block_type block_type);
207bool amdgpu_is_idle(struct amdgpu_device *adev,
208 enum amd_ip_block_type block_type);
Alex Deucher97b2e202015-04-20 16:51:00 -0400209
Alex Deuchera1255102016-10-13 17:41:13 -0400210#define AMDGPU_MAX_IP_NUM 16
211
212struct amdgpu_ip_block_status {
213 bool valid;
214 bool sw;
215 bool hw;
216 bool late_initialized;
217 bool hang;
218};
219
Alex Deucher97b2e202015-04-20 16:51:00 -0400220struct amdgpu_ip_block_version {
Alex Deuchera1255102016-10-13 17:41:13 -0400221 const enum amd_ip_block_type type;
222 const u32 major;
223 const u32 minor;
224 const u32 rev;
yanyang15fc3aee2015-05-22 14:39:35 -0400225 const struct amd_ip_funcs *funcs;
Alex Deucher97b2e202015-04-20 16:51:00 -0400226};
227
Alex Deuchera1255102016-10-13 17:41:13 -0400228struct amdgpu_ip_block {
229 struct amdgpu_ip_block_status status;
230 const struct amdgpu_ip_block_version *version;
231};
232
Alex Deucher97b2e202015-04-20 16:51:00 -0400233int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
yanyang15fc3aee2015-05-22 14:39:35 -0400234 enum amd_ip_block_type type,
Alex Deucher97b2e202015-04-20 16:51:00 -0400235 u32 major, u32 minor);
236
Alex Deuchera1255102016-10-13 17:41:13 -0400237struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev,
238 enum amd_ip_block_type type);
239
240int amdgpu_ip_block_add(struct amdgpu_device *adev,
241 const struct amdgpu_ip_block_version *ip_block_version);
Alex Deucher97b2e202015-04-20 16:51:00 -0400242
243/* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
244struct amdgpu_buffer_funcs {
245 /* maximum bytes in a single operation */
246 uint32_t copy_max_bytes;
247
248 /* number of dw to reserve per operation */
249 unsigned copy_num_dw;
250
251 /* used for buffer migration */
Chunming Zhouc7ae72c2015-08-25 17:23:45 +0800252 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
Alex Deucher97b2e202015-04-20 16:51:00 -0400253 /* src addr in bytes */
254 uint64_t src_offset,
255 /* dst addr in bytes */
256 uint64_t dst_offset,
257 /* number of byte to transfer */
258 uint32_t byte_count);
259
260 /* maximum bytes in a single operation */
261 uint32_t fill_max_bytes;
262
263 /* number of dw to reserve per operation */
264 unsigned fill_num_dw;
265
266 /* used for buffer clearing */
Chunming Zhou6e7a3842015-08-27 13:46:09 +0800267 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
Alex Deucher97b2e202015-04-20 16:51:00 -0400268 /* value to write to memory */
269 uint32_t src_data,
270 /* dst addr in bytes */
271 uint64_t dst_offset,
272 /* number of byte to fill */
273 uint32_t byte_count);
274};
275
276/* provided by hw blocks that can write ptes, e.g., sdma */
277struct amdgpu_vm_pte_funcs {
278 /* copy pte entries from GART */
279 void (*copy_pte)(struct amdgpu_ib *ib,
280 uint64_t pe, uint64_t src,
281 unsigned count);
282 /* write pte one entry at a time with addr mapping */
Christian Königde9ea7b2016-08-12 11:33:30 +0200283 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,
284 uint64_t value, unsigned count,
285 uint32_t incr);
Alex Deucher97b2e202015-04-20 16:51:00 -0400286 /* for linear pte/pde updates without addr mapping */
287 void (*set_pte_pde)(struct amdgpu_ib *ib,
288 uint64_t pe,
289 uint64_t addr, unsigned count,
Chunming Zhou6b777602016-09-21 16:19:19 +0800290 uint32_t incr, uint64_t flags);
Alex Deucher97b2e202015-04-20 16:51:00 -0400291};
292
293/* provided by the gmc block */
294struct amdgpu_gart_funcs {
295 /* flush the vm tlb via mmio */
296 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
297 uint32_t vmid);
298 /* write pte/pde updates using the cpu */
299 int (*set_pte_pde)(struct amdgpu_device *adev,
300 void *cpu_pt_addr, /* cpu addr of page table */
301 uint32_t gpu_page_idx, /* pte/pde to update */
302 uint64_t addr, /* addr to write into pte/pde */
Chunming Zhou6b777602016-09-21 16:19:19 +0800303 uint64_t flags); /* access flags */
Christian König284710f2017-01-30 11:09:31 +0100304 /* enable/disable PRT support */
305 void (*set_prt)(struct amdgpu_device *adev, bool enable);
Alex Xie54635452017-02-14 12:22:57 -0500306 /* set pte flags based per asic */
307 uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev,
308 uint32_t flags);
Alex Xiee60f8db2017-03-09 11:36:26 -0500309 /* adjust mc addr in fb for APU case */
310 u64 (*adjust_mc_addr)(struct amdgpu_device *adev, u64 addr);
Christian König03f89fe2017-04-04 16:07:45 +0200311 uint32_t (*get_invalidate_req)(unsigned int vm_id);
Alex Xiee60f8db2017-03-09 11:36:26 -0500312};
313
Alex Deucher97b2e202015-04-20 16:51:00 -0400314/* provided by the ih block */
315struct amdgpu_ih_funcs {
316 /* ring read/write ptr handling, called from interrupt context */
317 u32 (*get_wptr)(struct amdgpu_device *adev);
318 void (*decode_iv)(struct amdgpu_device *adev,
319 struct amdgpu_iv_entry *entry);
320 void (*set_rptr)(struct amdgpu_device *adev);
321};
322
Alex Deucher97b2e202015-04-20 16:51:00 -0400323/*
324 * BIOS.
325 */
326bool amdgpu_get_bios(struct amdgpu_device *adev);
327bool amdgpu_read_bios(struct amdgpu_device *adev);
328
329/*
330 * Dummy page
331 */
332struct amdgpu_dummy_page {
333 struct page *page;
334 dma_addr_t addr;
335};
336int amdgpu_dummy_page_init(struct amdgpu_device *adev);
337void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
338
339
340/*
341 * Clocks
342 */
343
344#define AMDGPU_MAX_PPLL 3
345
346struct amdgpu_clock {
347 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
348 struct amdgpu_pll spll;
349 struct amdgpu_pll mpll;
350 /* 10 Khz units */
351 uint32_t default_mclk;
352 uint32_t default_sclk;
353 uint32_t default_dispclk;
354 uint32_t current_dispclk;
355 uint32_t dp_extclk;
356 uint32_t max_pixel_clock;
357};
358
359/*
Flora Cuic632d792016-08-02 11:32:41 +0800360 * BO.
Alex Deucher97b2e202015-04-20 16:51:00 -0400361 */
Alex Deucher97b2e202015-04-20 16:51:00 -0400362struct amdgpu_bo_list_entry {
363 struct amdgpu_bo *robj;
364 struct ttm_validate_buffer tv;
365 struct amdgpu_bo_va *bo_va;
Alex Deucher97b2e202015-04-20 16:51:00 -0400366 uint32_t priority;
Christian König2f568db2016-02-23 12:36:59 +0100367 struct page **user_pages;
368 int user_invalidated;
Alex Deucher97b2e202015-04-20 16:51:00 -0400369};
370
371struct amdgpu_bo_va_mapping {
372 struct list_head list;
Christian Königa9f87f62017-03-30 14:03:59 +0200373 struct rb_node rb;
374 uint64_t start;
375 uint64_t last;
376 uint64_t __subtree_last;
Alex Deucher97b2e202015-04-20 16:51:00 -0400377 uint64_t offset;
Christian König268c3002017-01-18 14:49:43 +0100378 uint64_t flags;
Alex Deucher97b2e202015-04-20 16:51:00 -0400379};
380
381/* bo virtual addresses in a specific vm */
382struct amdgpu_bo_va {
383 /* protected by bo being reserved */
384 struct list_head bo_list;
Chris Wilsonf54d1862016-10-25 13:00:45 +0100385 struct dma_fence *last_pt_update;
Alex Deucher97b2e202015-04-20 16:51:00 -0400386 unsigned ref_count;
387
Christian König7fc11952015-07-30 11:53:42 +0200388 /* protected by vm mutex and spinlock */
Alex Deucher97b2e202015-04-20 16:51:00 -0400389 struct list_head vm_status;
390
Christian König7fc11952015-07-30 11:53:42 +0200391 /* mappings for this bo_va */
392 struct list_head invalids;
393 struct list_head valids;
394
Alex Deucher97b2e202015-04-20 16:51:00 -0400395 /* constant after initialization */
396 struct amdgpu_vm *vm;
397 struct amdgpu_bo *bo;
398};
399
Chunming Zhou7e5a5472015-04-24 17:37:30 +0800400#define AMDGPU_GEM_DOMAIN_MAX 0x3
401
Alex Deucher97b2e202015-04-20 16:51:00 -0400402struct amdgpu_bo {
Alex Deucher97b2e202015-04-20 16:51:00 -0400403 /* Protected by tbo.reserved */
Christian König1ea863f2015-12-18 22:13:12 +0100404 u32 prefered_domains;
405 u32 allowed_domains;
Chunming Zhou7e5a5472015-04-24 17:37:30 +0800406 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
Alex Deucher97b2e202015-04-20 16:51:00 -0400407 struct ttm_placement placement;
408 struct ttm_buffer_object tbo;
409 struct ttm_bo_kmap_obj kmap;
410 u64 flags;
411 unsigned pin_count;
412 void *kptr;
413 u64 tiling_flags;
414 u64 metadata_flags;
415 void *metadata;
416 u32 metadata_size;
Mario Kleiner8e94a462016-11-09 02:25:15 +0100417 unsigned prime_shared_count;
Alex Deucher97b2e202015-04-20 16:51:00 -0400418 /* list of all virtual address to which this bo
419 * is associated to
420 */
421 struct list_head va;
422 /* Constant after initialization */
Alex Deucher97b2e202015-04-20 16:51:00 -0400423 struct drm_gem_object gem_base;
Christian König82b9c552015-11-27 16:49:00 +0100424 struct amdgpu_bo *parent;
Chunming Zhoue7893c42016-07-26 14:13:21 +0800425 struct amdgpu_bo *shadow;
Alex Deucher97b2e202015-04-20 16:51:00 -0400426
427 struct ttm_bo_kmap_obj dma_buf_vmap;
Alex Deucher97b2e202015-04-20 16:51:00 -0400428 struct amdgpu_mn *mn;
429 struct list_head mn_list;
Chunming Zhou0c4e7fa2016-08-17 11:41:30 +0800430 struct list_head shadow_list;
Alex Deucher97b2e202015-04-20 16:51:00 -0400431};
432#define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
433
434void amdgpu_gem_object_free(struct drm_gem_object *obj);
435int amdgpu_gem_object_open(struct drm_gem_object *obj,
436 struct drm_file *file_priv);
437void amdgpu_gem_object_close(struct drm_gem_object *obj,
438 struct drm_file *file_priv);
439unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
440struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
Christian König4d9c5142016-05-03 18:46:19 +0200441struct drm_gem_object *
442amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
443 struct dma_buf_attachment *attach,
444 struct sg_table *sg);
Alex Deucher97b2e202015-04-20 16:51:00 -0400445struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
446 struct drm_gem_object *gobj,
447 int flags);
448int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
449void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
450struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
451void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
452void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
453int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
454
455/* sub-allocation manager, it has to be protected by another lock.
456 * By conception this is an helper for other part of the driver
457 * like the indirect buffer or semaphore, which both have their
458 * locking.
459 *
460 * Principe is simple, we keep a list of sub allocation in offset
461 * order (first entry has offset == 0, last entry has the highest
462 * offset).
463 *
464 * When allocating new object we first check if there is room at
465 * the end total_size - (last_object_offset + last_object_size) >=
466 * alloc_size. If so we allocate new object there.
467 *
468 * When there is not enough room at the end, we start waiting for
469 * each sub object until we reach object_offset+object_size >=
470 * alloc_size, this object then become the sub object we return.
471 *
472 * Alignment can't be bigger than page size.
473 *
474 * Hole are not considered for allocation to keep things simple.
475 * Assumption is that there won't be hole (all object on same
476 * alignment).
477 */
Christian König6ba60b82016-03-11 14:50:08 +0100478
479#define AMDGPU_SA_NUM_FENCE_LISTS 32
480
Alex Deucher97b2e202015-04-20 16:51:00 -0400481struct amdgpu_sa_manager {
482 wait_queue_head_t wq;
483 struct amdgpu_bo *bo;
484 struct list_head *hole;
Christian König6ba60b82016-03-11 14:50:08 +0100485 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
Alex Deucher97b2e202015-04-20 16:51:00 -0400486 struct list_head olist;
487 unsigned size;
488 uint64_t gpu_addr;
489 void *cpu_ptr;
490 uint32_t domain;
491 uint32_t align;
492};
493
Alex Deucher97b2e202015-04-20 16:51:00 -0400494/* sub-allocation buffer */
495struct amdgpu_sa_bo {
496 struct list_head olist;
497 struct list_head flist;
498 struct amdgpu_sa_manager *manager;
499 unsigned soffset;
500 unsigned eoffset;
Chris Wilsonf54d1862016-10-25 13:00:45 +0100501 struct dma_fence *fence;
Alex Deucher97b2e202015-04-20 16:51:00 -0400502};
503
504/*
505 * GEM objects.
506 */
Christian König418aa0c2016-02-15 16:59:57 +0100507void amdgpu_gem_force_release(struct amdgpu_device *adev);
Alex Deucher97b2e202015-04-20 16:51:00 -0400508int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
509 int alignment, u32 initial_domain,
510 u64 flags, bool kernel,
511 struct drm_gem_object **obj);
512
513int amdgpu_mode_dumb_create(struct drm_file *file_priv,
514 struct drm_device *dev,
515 struct drm_mode_create_dumb *args);
516int amdgpu_mode_dumb_mmap(struct drm_file *filp,
517 struct drm_device *dev,
518 uint32_t handle, uint64_t *offset_p);
Rex Zhud573de22016-05-12 13:27:28 +0800519int amdgpu_fence_slab_init(void);
520void amdgpu_fence_slab_fini(void);
Alex Deucher97b2e202015-04-20 16:51:00 -0400521
522/*
523 * GART structures, functions & helpers
524 */
525struct amdgpu_mc;
526
527#define AMDGPU_GPU_PAGE_SIZE 4096
528#define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
529#define AMDGPU_GPU_PAGE_SHIFT 12
530#define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
531
532struct amdgpu_gart {
533 dma_addr_t table_addr;
534 struct amdgpu_bo *robj;
535 void *ptr;
536 unsigned num_gpu_pages;
537 unsigned num_cpu_pages;
538 unsigned table_size;
Christian Königa1d29472016-03-30 14:42:57 +0200539#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
Alex Deucher97b2e202015-04-20 16:51:00 -0400540 struct page **pages;
Christian Königa1d29472016-03-30 14:42:57 +0200541#endif
Alex Deucher97b2e202015-04-20 16:51:00 -0400542 bool ready;
Alex Xie4b98e0c2017-02-14 12:31:36 -0500543
544 /* Asic default pte flags */
545 uint64_t gart_pte_flags;
546
Alex Deucher97b2e202015-04-20 16:51:00 -0400547 const struct amdgpu_gart_funcs *gart_funcs;
548};
549
550int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
551void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
552int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
553void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
554int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
555void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
556int amdgpu_gart_init(struct amdgpu_device *adev);
557void amdgpu_gart_fini(struct amdgpu_device *adev);
Roger.He738f64c2017-05-05 13:27:10 +0800558int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
Alex Deucher97b2e202015-04-20 16:51:00 -0400559 int pages);
Felix Kuehlingcab0b8d2016-08-12 19:25:21 -0400560int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
Alex Deucher97b2e202015-04-20 16:51:00 -0400561 int pages, struct page **pagelist,
Chunming Zhou6b777602016-09-21 16:19:19 +0800562 dma_addr_t *dma_addr, uint64_t flags);
Chunming Zhou2c0d7312016-08-30 16:36:25 +0800563int amdgpu_ttm_recover_gart(struct amdgpu_device *adev);
Alex Deucher97b2e202015-04-20 16:51:00 -0400564
565/*
Alex Xiee60f8db2017-03-09 11:36:26 -0500566 * VMHUB structures, functions & helpers
567 */
568struct amdgpu_vmhub {
569 uint32_t ctx0_ptb_addr_lo32;
570 uint32_t ctx0_ptb_addr_hi32;
571 uint32_t vm_inv_eng0_req;
572 uint32_t vm_inv_eng0_ack;
573 uint32_t vm_context0_cntl;
574 uint32_t vm_l2_pro_fault_status;
575 uint32_t vm_l2_pro_fault_cntl;
Alex Xiee60f8db2017-03-09 11:36:26 -0500576};
577
578/*
Alex Deucher97b2e202015-04-20 16:51:00 -0400579 * GPU MC structures, functions & helpers
580 */
581struct amdgpu_mc {
582 resource_size_t aper_size;
583 resource_size_t aper_base;
584 resource_size_t agp_base;
585 /* for some chips with <= 32MB we need to lie
586 * about vram size near mc fb location */
587 u64 mc_vram_size;
588 u64 visible_vram_size;
589 u64 gtt_size;
590 u64 gtt_start;
591 u64 gtt_end;
592 u64 vram_start;
593 u64 vram_end;
594 unsigned vram_width;
595 u64 real_vram_size;
596 int vram_mtrr;
597 u64 gtt_base_align;
598 u64 mc_mask;
599 const struct firmware *fw; /* MC firmware */
600 uint32_t fw_version;
601 struct amdgpu_irq_src vm_fault;
Ken Wang81c59f52015-06-03 21:02:01 +0800602 uint32_t vram_type;
Chunming Zhou50b01972016-07-18 16:59:24 +0800603 uint32_t srbm_soft_reset;
604 struct amdgpu_mode_mc_save save;
Christian Königf7c35ab2017-01-27 11:56:05 +0100605 bool prt_warning;
Junwei Zhang8fe73322016-03-10 14:20:39 +0800606 /* apertures */
607 u64 shared_aperture_start;
608 u64 shared_aperture_end;
609 u64 private_aperture_start;
610 u64 private_aperture_end;
Alex Xiee60f8db2017-03-09 11:36:26 -0500611 /* protects concurrent invalidation */
612 spinlock_t invalidate_lock;
Alex Deucher97b2e202015-04-20 16:51:00 -0400613};
614
615/*
616 * GPU doorbell structures, functions & helpers
617 */
618typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
619{
620 AMDGPU_DOORBELL_KIQ = 0x000,
621 AMDGPU_DOORBELL_HIQ = 0x001,
622 AMDGPU_DOORBELL_DIQ = 0x002,
623 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
624 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
625 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
626 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
627 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
628 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
629 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
630 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
631 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
632 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
633 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
634 AMDGPU_DOORBELL_IH = 0x1E8,
635 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
636 AMDGPU_DOORBELL_INVALID = 0xFFFF
637} AMDGPU_DOORBELL_ASSIGNMENT;
638
639struct amdgpu_doorbell {
640 /* doorbell mmio */
641 resource_size_t base;
642 resource_size_t size;
643 u32 __iomem *ptr;
644 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
645};
646
Ken Wang39807b92016-03-18 15:41:42 +0800647/*
648 * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space
649 */
650typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
651{
652 /*
653 * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in
654 * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range.
655 * Compute related doorbells are allocated from 0x00 to 0x8a
656 */
657
658
659 /* kernel scheduling */
660 AMDGPU_DOORBELL64_KIQ = 0x00,
661
662 /* HSA interface queue and debug queue */
663 AMDGPU_DOORBELL64_HIQ = 0x01,
664 AMDGPU_DOORBELL64_DIQ = 0x02,
665
666 /* Compute engines */
667 AMDGPU_DOORBELL64_MEC_RING0 = 0x03,
668 AMDGPU_DOORBELL64_MEC_RING1 = 0x04,
669 AMDGPU_DOORBELL64_MEC_RING2 = 0x05,
670 AMDGPU_DOORBELL64_MEC_RING3 = 0x06,
671 AMDGPU_DOORBELL64_MEC_RING4 = 0x07,
672 AMDGPU_DOORBELL64_MEC_RING5 = 0x08,
673 AMDGPU_DOORBELL64_MEC_RING6 = 0x09,
674 AMDGPU_DOORBELL64_MEC_RING7 = 0x0a,
675
676 /* User queue doorbell range (128 doorbells) */
677 AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b,
678 AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a,
679
680 /* Graphics engine */
681 AMDGPU_DOORBELL64_GFX_RING0 = 0x8b,
682
683 /*
684 * Other graphics doorbells can be allocated here: from 0x8c to 0xef
685 * Graphics voltage island aperture 1
686 * default non-graphics QWORD index is 0xF0 - 0xFF inclusive
687 */
688
689 /* sDMA engines */
690 AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xF0,
691 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1,
692 AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xF2,
693 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3,
694
695 /* Interrupt handler */
696 AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */
697 AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */
698 AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */
699
Monk Liue6b3ecb2016-12-30 16:18:56 +0800700 /* VCN engine use 32 bits doorbell */
701 AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */
702 AMDGPU_DOORBELL64_VCN2_3 = 0xF9,
703 AMDGPU_DOORBELL64_VCN4_5 = 0xFA,
704 AMDGPU_DOORBELL64_VCN6_7 = 0xFB,
705
706 /* overlap the doorbell assignment with VCN as they are mutually exclusive
707 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD
708 */
709 AMDGPU_DOORBELL64_RING0_1 = 0xF8,
710 AMDGPU_DOORBELL64_RING2_3 = 0xF9,
711 AMDGPU_DOORBELL64_RING4_5 = 0xFA,
712 AMDGPU_DOORBELL64_RING6_7 = 0xFB,
713
714 AMDGPU_DOORBELL64_UVD_RING0_1 = 0xFC,
715 AMDGPU_DOORBELL64_UVD_RING2_3 = 0xFD,
716 AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFE,
717 AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFF,
Ken Wang39807b92016-03-18 15:41:42 +0800718
719 AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF,
720 AMDGPU_DOORBELL64_INVALID = 0xFFFF
721} AMDGPU_DOORBELL64_ASSIGNMENT;
722
723
Alex Deucher97b2e202015-04-20 16:51:00 -0400724void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
725 phys_addr_t *aperture_base,
726 size_t *aperture_size,
727 size_t *start_offset);
728
729/*
730 * IRQS.
731 */
732
733struct amdgpu_flip_work {
Michel Dänzer325cbba2016-08-04 12:39:37 +0900734 struct delayed_work flip_work;
Alex Deucher97b2e202015-04-20 16:51:00 -0400735 struct work_struct unpin_work;
736 struct amdgpu_device *adev;
737 int crtc_id;
Michel Dänzer325cbba2016-08-04 12:39:37 +0900738 u32 target_vblank;
Alex Deucher97b2e202015-04-20 16:51:00 -0400739 uint64_t base;
740 struct drm_pending_vblank_event *event;
Christian König765e7fb2016-09-15 15:06:50 +0200741 struct amdgpu_bo *old_abo;
Chris Wilsonf54d1862016-10-25 13:00:45 +0100742 struct dma_fence *excl;
Christian König1ffd2652015-08-11 17:29:52 +0200743 unsigned shared_count;
Chris Wilsonf54d1862016-10-25 13:00:45 +0100744 struct dma_fence **shared;
745 struct dma_fence_cb cb;
Alex Deuchercb9e59d2016-05-05 16:03:57 -0400746 bool async;
Alex Deucher97b2e202015-04-20 16:51:00 -0400747};
748
749
750/*
751 * CP & rings.
752 */
753
754struct amdgpu_ib {
755 struct amdgpu_sa_bo *sa_bo;
756 uint32_t length_dw;
757 uint64_t gpu_addr;
758 uint32_t *ptr;
Jammy Zhoude807f82015-05-11 23:41:41 +0800759 uint32_t flags;
Alex Deucher97b2e202015-04-20 16:51:00 -0400760};
761
Nils Wallménius62250a92016-04-10 16:30:00 +0200762extern const struct amd_sched_backend_ops amdgpu_sched_ops;
Chunming Zhouc1b69ed2015-07-21 13:45:14 +0800763
Christian König50838c82016-02-03 13:44:52 +0100764int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
Monk Liuc5637832016-04-19 20:11:32 +0800765 struct amdgpu_job **job, struct amdgpu_vm *vm);
Christian Königd71518b2016-02-01 12:20:25 +0100766int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
767 struct amdgpu_job **job);
Monk Liub6723c82016-03-10 12:14:44 +0800768
Christian Königa5fb4ec2016-06-29 15:10:31 +0200769void amdgpu_job_free_resources(struct amdgpu_job *job);
Christian König50838c82016-02-03 13:44:52 +0100770void amdgpu_job_free(struct amdgpu_job *job);
Christian Königd71518b2016-02-01 12:20:25 +0100771int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
Christian König2bd9ccf2016-02-01 12:53:58 +0100772 struct amd_sched_entity *entity, void *owner,
Chris Wilsonf54d1862016-10-25 13:00:45 +0100773 struct dma_fence **f);
Christian König8b4fb002015-11-15 16:04:16 +0100774
Alex Deucher97b2e202015-04-20 16:51:00 -0400775/*
776 * context related structures
777 */
778
Christian König21c16bf2015-07-07 17:24:49 +0200779struct amdgpu_ctx_ring {
Christian König91404fb2015-08-05 18:33:21 +0200780 uint64_t sequence;
Chris Wilsonf54d1862016-10-25 13:00:45 +0100781 struct dma_fence **fences;
Christian König91404fb2015-08-05 18:33:21 +0200782 struct amd_sched_entity entity;
Christian König21c16bf2015-07-07 17:24:49 +0200783};
784
Alex Deucher97b2e202015-04-20 16:51:00 -0400785struct amdgpu_ctx {
Alex Deucher0b492a42015-08-16 22:48:26 -0400786 struct kref refcount;
Chunming Zhou9cb7e5a2015-07-21 13:17:19 +0800787 struct amdgpu_device *adev;
Alex Deucher0b492a42015-08-16 22:48:26 -0400788 unsigned reset_counter;
Christian König21c16bf2015-07-07 17:24:49 +0200789 spinlock_t ring_lock;
Chris Wilsonf54d1862016-10-25 13:00:45 +0100790 struct dma_fence **fences;
Christian König21c16bf2015-07-07 17:24:49 +0200791 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
Monk Liu753ad492016-08-26 13:28:28 +0800792 bool preamble_presented;
Alex Deucher97b2e202015-04-20 16:51:00 -0400793};
794
795struct amdgpu_ctx_mgr {
Alex Deucher0b492a42015-08-16 22:48:26 -0400796 struct amdgpu_device *adev;
797 struct mutex lock;
798 /* protected by lock */
799 struct idr ctx_handles;
Alex Deucher97b2e202015-04-20 16:51:00 -0400800};
801
Alex Deucher0b492a42015-08-16 22:48:26 -0400802struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
803int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
804
Christian König21c16bf2015-07-07 17:24:49 +0200805uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
Chris Wilsonf54d1862016-10-25 13:00:45 +0100806 struct dma_fence *fence);
807struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
Christian König21c16bf2015-07-07 17:24:49 +0200808 struct amdgpu_ring *ring, uint64_t seq);
809
Alex Deucher0b492a42015-08-16 22:48:26 -0400810int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
811 struct drm_file *filp);
812
Christian Königefd4ccb2015-08-04 16:20:31 +0200813void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
814void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
Alex Deucher0b492a42015-08-16 22:48:26 -0400815
Alex Deucher97b2e202015-04-20 16:51:00 -0400816/*
817 * file private structure
818 */
819
820struct amdgpu_fpriv {
821 struct amdgpu_vm vm;
Junwei Zhangb85891b2017-01-16 13:59:01 +0800822 struct amdgpu_bo_va *prt_va;
Alex Deucher97b2e202015-04-20 16:51:00 -0400823 struct mutex bo_list_lock;
824 struct idr bo_list_handles;
Alex Deucher0b492a42015-08-16 22:48:26 -0400825 struct amdgpu_ctx_mgr ctx_mgr;
Alex Deucher97b2e202015-04-20 16:51:00 -0400826};
827
828/*
829 * residency list
830 */
831
832struct amdgpu_bo_list {
833 struct mutex lock;
834 struct amdgpu_bo *gds_obj;
835 struct amdgpu_bo *gws_obj;
836 struct amdgpu_bo *oa_obj;
Christian König211dff52016-02-22 15:40:59 +0100837 unsigned first_userptr;
Alex Deucher97b2e202015-04-20 16:51:00 -0400838 unsigned num_entries;
839 struct amdgpu_bo_list_entry *array;
840};
841
842struct amdgpu_bo_list *
843amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
Christian König636ce252015-12-18 21:26:47 +0100844void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
845 struct list_head *validated);
Alex Deucher97b2e202015-04-20 16:51:00 -0400846void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
847void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
848
849/*
850 * GFX stuff
851 */
852#include "clearstate_defs.h"
853
Alex Deucher79e54122016-04-08 15:45:13 -0400854struct amdgpu_rlc_funcs {
855 void (*enter_safe_mode)(struct amdgpu_device *adev);
856 void (*exit_safe_mode)(struct amdgpu_device *adev);
857};
858
Alex Deucher97b2e202015-04-20 16:51:00 -0400859struct amdgpu_rlc {
860 /* for power gating */
861 struct amdgpu_bo *save_restore_obj;
862 uint64_t save_restore_gpu_addr;
863 volatile uint32_t *sr_ptr;
864 const u32 *reg_list;
865 u32 reg_list_size;
866 /* for clear state */
867 struct amdgpu_bo *clear_state_obj;
868 uint64_t clear_state_gpu_addr;
869 volatile uint32_t *cs_ptr;
870 const struct cs_section_def *cs_data;
871 u32 clear_state_size;
872 /* for cp tables */
873 struct amdgpu_bo *cp_table_obj;
874 uint64_t cp_table_gpu_addr;
875 volatile uint32_t *cp_table_ptr;
876 u32 cp_table_size;
Alex Deucher79e54122016-04-08 15:45:13 -0400877
878 /* safe mode for updating CG/PG state */
879 bool in_safe_mode;
880 const struct amdgpu_rlc_funcs *funcs;
Eric Huang2b6cd972016-04-14 17:26:07 -0400881
882 /* for firmware data */
883 u32 save_and_restore_offset;
884 u32 clear_state_descriptor_offset;
885 u32 avail_scratch_ram_locations;
886 u32 reg_restore_list_size;
887 u32 reg_list_format_start;
888 u32 reg_list_format_separate_start;
889 u32 starting_offsets_start;
890 u32 reg_list_format_size_bytes;
891 u32 reg_list_size_bytes;
892
893 u32 *register_list_format;
894 u32 *register_restore;
Alex Deucher97b2e202015-04-20 16:51:00 -0400895};
896
897struct amdgpu_mec {
898 struct amdgpu_bo *hpd_eop_obj;
899 u64 hpd_eop_gpu_addr;
Ken Wangb1023572017-03-03 17:59:39 -0500900 struct amdgpu_bo *mec_fw_obj;
901 u64 mec_fw_gpu_addr;
Alex Deucher97b2e202015-04-20 16:51:00 -0400902 u32 num_pipe;
903 u32 num_mec;
904 u32 num_queue;
Xiangliang Yu59a82d72017-02-17 16:03:10 +0800905 void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1];
Alex Deucher97b2e202015-04-20 16:51:00 -0400906};
907
Xiangliang Yu4e638ae2016-12-23 15:00:01 +0800908struct amdgpu_kiq {
909 u64 eop_gpu_addr;
910 struct amdgpu_bo *eop_obj;
Shaoyun Liucdf6adb2017-04-28 17:18:26 -0400911 struct mutex ring_mutex;
Xiangliang Yu4e638ae2016-12-23 15:00:01 +0800912 struct amdgpu_ring ring;
913 struct amdgpu_irq_src irq;
914};
915
Alex Deucher97b2e202015-04-20 16:51:00 -0400916/*
917 * GPU scratch registers structures, functions & helpers
918 */
919struct amdgpu_scratch {
920 unsigned num_reg;
921 uint32_t reg_base;
Nils Wallménius50261152017-01-16 21:56:48 +0100922 uint32_t free_mask;
Alex Deucher97b2e202015-04-20 16:51:00 -0400923};
924
925/*
926 * GFX configurations
927 */
Alex Deuchere3fa7632016-10-10 10:56:21 -0400928#define AMDGPU_GFX_MAX_SE 4
929#define AMDGPU_GFX_MAX_SH_PER_SE 2
930
931struct amdgpu_rb_config {
932 uint32_t rb_backend_disable;
933 uint32_t user_rb_backend_disable;
934 uint32_t raster_config;
935 uint32_t raster_config_1;
936};
937
Andrey Grodzovskyd0e95752016-12-12 13:40:37 -0500938struct gb_addr_config {
939 uint16_t pipe_interleave_size;
940 uint8_t num_pipes;
941 uint8_t max_compress_frags;
942 uint8_t num_banks;
943 uint8_t num_se;
944 uint8_t num_rb_per_se;
945};
946
Junwei Zhangea323f82017-02-21 10:32:37 +0800947struct amdgpu_gfx_config {
Alex Deucher97b2e202015-04-20 16:51:00 -0400948 unsigned max_shader_engines;
949 unsigned max_tile_pipes;
950 unsigned max_cu_per_sh;
951 unsigned max_sh_per_se;
952 unsigned max_backends_per_se;
953 unsigned max_texture_channel_caches;
954 unsigned max_gprs;
955 unsigned max_gs_threads;
956 unsigned max_hw_contexts;
957 unsigned sc_prim_fifo_size_frontend;
958 unsigned sc_prim_fifo_size_backend;
959 unsigned sc_hiz_tile_fifo_size;
960 unsigned sc_earlyz_tile_fifo_size;
961
962 unsigned num_tile_pipes;
963 unsigned backend_enable_mask;
964 unsigned mem_max_burst_length_bytes;
965 unsigned mem_row_size_in_kb;
966 unsigned shader_engine_tile_size;
967 unsigned num_gpus;
968 unsigned multi_gpu_tile_size;
969 unsigned mc_arb_ramcfg;
970 unsigned gb_addr_config;
Alex Deucher8f8e00c2016-02-12 00:39:13 -0500971 unsigned num_rbs;
Junwei Zhang408bfe72017-04-27 11:12:07 +0800972 unsigned gs_vgt_table_depth;
973 unsigned gs_prim_buffer_depth;
Alex Deucher97b2e202015-04-20 16:51:00 -0400974
975 uint32_t tile_mode_array[32];
976 uint32_t macrotile_mode_array[16];
Alex Deuchere3fa7632016-10-10 10:56:21 -0400977
Andrey Grodzovskyd0e95752016-12-12 13:40:37 -0500978 struct gb_addr_config gb_addr_config_fields;
Alex Deuchere3fa7632016-10-10 10:56:21 -0400979 struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
Junwei Zhangdf6e2c42017-02-17 11:05:49 +0800980
981 /* gfx configure feature */
982 uint32_t double_offchip_lds_buf;
Alex Deucher97b2e202015-04-20 16:51:00 -0400983};
984
Alex Deucher7dae69a2016-05-03 16:25:53 -0400985struct amdgpu_cu_info {
986 uint32_t number; /* total active CU number */
987 uint32_t ao_cu_mask;
Junwei Zhang408bfe72017-04-27 11:12:07 +0800988 uint32_t wave_front_size;
Alex Deucher7dae69a2016-05-03 16:25:53 -0400989 uint32_t bitmap[4][4];
990};
991
Alex Deucherb95e31f2016-07-07 15:01:42 -0400992struct amdgpu_gfx_funcs {
993 /* get the gpu clock counter */
994 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
Tom St Denis9559ef52016-06-28 10:26:48 -0400995 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
Tom St Denis472259f2016-10-14 09:49:09 -0400996 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields);
Tom St Denisc5a60ce2016-12-05 11:39:19 -0500997 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst);
998 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst);
Alex Deucherb95e31f2016-07-07 15:01:42 -0400999};
1000
Alex Deucherbce23e02017-03-28 12:52:08 -04001001struct amdgpu_ngg_buf {
1002 struct amdgpu_bo *bo;
1003 uint64_t gpu_addr;
1004 uint32_t size;
1005 uint32_t bo_size;
1006};
1007
1008enum {
Guenter Roeckaf8baf12017-05-03 23:49:18 -07001009 NGG_PRIM = 0,
1010 NGG_POS,
1011 NGG_CNTL,
1012 NGG_PARAM,
Alex Deucherbce23e02017-03-28 12:52:08 -04001013 NGG_BUF_MAX
1014};
1015
1016struct amdgpu_ngg {
1017 struct amdgpu_ngg_buf buf[NGG_BUF_MAX];
1018 uint32_t gds_reserve_addr;
1019 uint32_t gds_reserve_size;
1020 bool init;
1021};
1022
Alex Deucher97b2e202015-04-20 16:51:00 -04001023struct amdgpu_gfx {
1024 struct mutex gpu_clock_mutex;
Junwei Zhangea323f82017-02-21 10:32:37 +08001025 struct amdgpu_gfx_config config;
Alex Deucher97b2e202015-04-20 16:51:00 -04001026 struct amdgpu_rlc rlc;
1027 struct amdgpu_mec mec;
Xiangliang Yu4e638ae2016-12-23 15:00:01 +08001028 struct amdgpu_kiq kiq;
Alex Deucher97b2e202015-04-20 16:51:00 -04001029 struct amdgpu_scratch scratch;
1030 const struct firmware *me_fw; /* ME firmware */
1031 uint32_t me_fw_version;
1032 const struct firmware *pfp_fw; /* PFP firmware */
1033 uint32_t pfp_fw_version;
1034 const struct firmware *ce_fw; /* CE firmware */
1035 uint32_t ce_fw_version;
1036 const struct firmware *rlc_fw; /* RLC firmware */
1037 uint32_t rlc_fw_version;
1038 const struct firmware *mec_fw; /* MEC firmware */
1039 uint32_t mec_fw_version;
1040 const struct firmware *mec2_fw; /* MEC2 firmware */
1041 uint32_t mec2_fw_version;
Ken Wang02558a02015-06-03 19:52:06 +08001042 uint32_t me_feature_version;
1043 uint32_t ce_feature_version;
1044 uint32_t pfp_feature_version;
Jammy Zhou351643d2015-08-04 10:43:50 +08001045 uint32_t rlc_feature_version;
1046 uint32_t mec_feature_version;
1047 uint32_t mec2_feature_version;
Alex Deucher97b2e202015-04-20 16:51:00 -04001048 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
1049 unsigned num_gfx_rings;
1050 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
1051 unsigned num_compute_rings;
1052 struct amdgpu_irq_src eop_irq;
1053 struct amdgpu_irq_src priv_reg_irq;
1054 struct amdgpu_irq_src priv_inst_irq;
1055 /* gfx status */
Alex Deucher7dae69a2016-05-03 16:25:53 -04001056 uint32_t gfx_current_status;
Ken Wanga101a892015-06-03 17:47:54 +08001057 /* ce ram size*/
Alex Deucher7dae69a2016-05-03 16:25:53 -04001058 unsigned ce_ram_size;
1059 struct amdgpu_cu_info cu_info;
Alex Deucherb95e31f2016-07-07 15:01:42 -04001060 const struct amdgpu_gfx_funcs *funcs;
Chunming Zhou3d7c6382016-07-15 11:28:30 +08001061
1062 /* reset mask */
1063 uint32_t grbm_soft_reset;
1064 uint32_t srbm_soft_reset;
Monk Liu223049c2017-01-26 15:32:16 +08001065 bool in_reset;
David Panaritib4e40672017-03-28 12:57:31 -04001066 /* s3/s4 mask */
1067 bool in_suspend;
Alex Deucherbce23e02017-03-28 12:52:08 -04001068 /* NGG */
1069 struct amdgpu_ngg ngg;
Alex Deucher97b2e202015-04-20 16:51:00 -04001070};
1071
Christian Königb07c60c2016-01-31 12:29:04 +01001072int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
Alex Deucher97b2e202015-04-20 16:51:00 -04001073 unsigned size, struct amdgpu_ib *ib);
Christian König4d9c5142016-05-03 18:46:19 +02001074void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
Chris Wilsonf54d1862016-10-25 13:00:45 +01001075 struct dma_fence *f);
Christian Königb07c60c2016-01-31 12:29:04 +01001076int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
Junwei Zhang50ddc752017-01-23 16:30:38 +08001077 struct amdgpu_ib *ibs, struct amdgpu_job *job,
1078 struct dma_fence **f);
Alex Deucher97b2e202015-04-20 16:51:00 -04001079int amdgpu_ib_pool_init(struct amdgpu_device *adev);
1080void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
1081int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
Alex Deucher97b2e202015-04-20 16:51:00 -04001082
1083/*
1084 * CS.
1085 */
1086struct amdgpu_cs_chunk {
1087 uint32_t chunk_id;
1088 uint32_t length_dw;
Christian König758ac172016-05-06 22:14:00 +02001089 void *kdata;
Alex Deucher97b2e202015-04-20 16:51:00 -04001090};
1091
1092struct amdgpu_cs_parser {
1093 struct amdgpu_device *adev;
1094 struct drm_file *filp;
Christian König3cb485f2015-05-11 15:34:59 +02001095 struct amdgpu_ctx *ctx;
Christian Königc3cca412015-12-15 14:41:33 +01001096
Alex Deucher97b2e202015-04-20 16:51:00 -04001097 /* chunks */
1098 unsigned nchunks;
1099 struct amdgpu_cs_chunk *chunks;
Alex Deucher97b2e202015-04-20 16:51:00 -04001100
Christian König50838c82016-02-03 13:44:52 +01001101 /* scheduler job object */
1102 struct amdgpu_job *job;
Alex Deucher97b2e202015-04-20 16:51:00 -04001103
Christian Königc3cca412015-12-15 14:41:33 +01001104 /* buffer objects */
1105 struct ww_acquire_ctx ticket;
1106 struct amdgpu_bo_list *bo_list;
1107 struct amdgpu_bo_list_entry vm_pd;
1108 struct list_head validated;
Chris Wilsonf54d1862016-10-25 13:00:45 +01001109 struct dma_fence *fence;
Christian Königc3cca412015-12-15 14:41:33 +01001110 uint64_t bytes_moved_threshold;
1111 uint64_t bytes_moved;
Christian König662bfa62016-09-01 12:13:18 +02001112 struct amdgpu_bo_list_entry *evictable;
Alex Deucher97b2e202015-04-20 16:51:00 -04001113
1114 /* user fence */
Christian König91acbeb2015-12-14 16:42:31 +01001115 struct amdgpu_bo_list_entry uf_entry;
Alex Deucher97b2e202015-04-20 16:51:00 -04001116};
1117
Monk Liu753ad492016-08-26 13:28:28 +08001118#define AMDGPU_PREAMBLE_IB_PRESENT (1 << 0) /* bit set means command submit involves a preamble IB */
1119#define AMDGPU_PREAMBLE_IB_PRESENT_FIRST (1 << 1) /* bit set means preamble IB is first presented in belonging context */
1120#define AMDGPU_HAVE_CTX_SWITCH (1 << 2) /* bit set means context switch occured */
1121
Chunming Zhoubb977d32015-08-18 15:16:40 +08001122struct amdgpu_job {
1123 struct amd_sched_job base;
1124 struct amdgpu_device *adev;
Christian Königedf600d2016-05-03 15:54:54 +02001125 struct amdgpu_vm *vm;
Christian Königb07c60c2016-01-31 12:29:04 +01001126 struct amdgpu_ring *ring;
Christian Könige86f9ce2016-02-08 12:13:05 +01001127 struct amdgpu_sync sync;
Chunming Zhoudf83d1e2017-05-09 15:50:22 +08001128 struct amdgpu_sync sched_sync;
Chunming Zhoubb977d32015-08-18 15:16:40 +08001129 struct amdgpu_ib *ibs;
Chris Wilsonf54d1862016-10-25 13:00:45 +01001130 struct dma_fence *fence; /* the hw fence */
Monk Liu753ad492016-08-26 13:28:28 +08001131 uint32_t preamble_status;
Chunming Zhoubb977d32015-08-18 15:16:40 +08001132 uint32_t num_ibs;
Christian Könige2840222015-11-05 19:49:48 +01001133 void *owner;
Monk Liu3aecd242016-08-25 15:40:48 +08001134 uint64_t fence_ctx; /* the fence_context this job uses */
Chunming Zhoufd53be32016-07-01 17:59:01 +08001135 bool vm_needs_flush;
Christian Königd88bf582016-05-06 17:50:03 +02001136 unsigned vm_id;
1137 uint64_t vm_pd_addr;
1138 uint32_t gds_base, gds_size;
1139 uint32_t gws_base, gws_size;
1140 uint32_t oa_base, oa_size;
Christian König758ac172016-05-06 22:14:00 +02001141
1142 /* user fence handling */
Christian Königb5f5acb2016-06-29 13:26:41 +02001143 uint64_t uf_addr;
Christian König758ac172016-05-06 22:14:00 +02001144 uint64_t uf_sequence;
1145
Chunming Zhoubb977d32015-08-18 15:16:40 +08001146};
Junwei Zhanga6db8a32015-09-09 09:21:19 +08001147#define to_amdgpu_job(sched_job) \
1148 container_of((sched_job), struct amdgpu_job, base)
Chunming Zhoubb977d32015-08-18 15:16:40 +08001149
Christian König7270f832016-01-31 11:00:41 +01001150static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
1151 uint32_t ib_idx, int idx)
Alex Deucher97b2e202015-04-20 16:51:00 -04001152{
Christian König50838c82016-02-03 13:44:52 +01001153 return p->job->ibs[ib_idx].ptr[idx];
Alex Deucher97b2e202015-04-20 16:51:00 -04001154}
1155
Christian König7270f832016-01-31 11:00:41 +01001156static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
1157 uint32_t ib_idx, int idx,
1158 uint32_t value)
1159{
Christian König50838c82016-02-03 13:44:52 +01001160 p->job->ibs[ib_idx].ptr[idx] = value;
Christian König7270f832016-01-31 11:00:41 +01001161}
1162
Alex Deucher97b2e202015-04-20 16:51:00 -04001163/*
1164 * Writeback
1165 */
1166#define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1167
1168struct amdgpu_wb {
1169 struct amdgpu_bo *wb_obj;
1170 volatile uint32_t *wb;
1171 uint64_t gpu_addr;
1172 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1173 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1174};
1175
1176int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1177void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
Ken Wang70142852016-03-18 15:08:49 +08001178int amdgpu_wb_get_64bit(struct amdgpu_device *adev, u32 *wb);
1179void amdgpu_wb_free_64bit(struct amdgpu_device *adev, u32 wb);
Alex Deucher97b2e202015-04-20 16:51:00 -04001180
Alex Deucherd0dd7f02015-11-11 19:45:06 -05001181void amdgpu_get_pcie_info(struct amdgpu_device *adev);
1182
Alex Deucher97b2e202015-04-20 16:51:00 -04001183/*
Alex Deucher97b2e202015-04-20 16:51:00 -04001184 * SDMA
1185 */
Alex Deucherc113ea12015-10-08 16:30:37 -04001186struct amdgpu_sdma_instance {
Alex Deucher97b2e202015-04-20 16:51:00 -04001187 /* SDMA firmware */
1188 const struct firmware *fw;
1189 uint32_t fw_version;
Jammy Zhoucfa21042015-08-04 10:50:47 +08001190 uint32_t feature_version;
Alex Deucher97b2e202015-04-20 16:51:00 -04001191
1192 struct amdgpu_ring ring;
Jammy Zhou18111de2015-08-31 14:06:39 +08001193 bool burst_nop;
Alex Deucher97b2e202015-04-20 16:51:00 -04001194};
1195
Alex Deucherc113ea12015-10-08 16:30:37 -04001196struct amdgpu_sdma {
1197 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
Ken Wang30d15742016-01-19 14:05:23 +08001198#ifdef CONFIG_DRM_AMDGPU_SI
1199 //SI DMA has a difference trap irq number for the second engine
1200 struct amdgpu_irq_src trap_irq_1;
1201#endif
Alex Deucherc113ea12015-10-08 16:30:37 -04001202 struct amdgpu_irq_src trap_irq;
1203 struct amdgpu_irq_src illegal_inst_irq;
Christian Königedf600d2016-05-03 15:54:54 +02001204 int num_instances;
Chunming Zhoue702a682016-07-13 10:28:56 +08001205 uint32_t srbm_soft_reset;
Alex Deucherc113ea12015-10-08 16:30:37 -04001206};
1207
Alex Deucher97b2e202015-04-20 16:51:00 -04001208/*
1209 * Firmware
1210 */
Huang Ruie635ee02016-11-01 15:35:38 +08001211enum amdgpu_firmware_load_type {
1212 AMDGPU_FW_LOAD_DIRECT = 0,
1213 AMDGPU_FW_LOAD_SMU,
1214 AMDGPU_FW_LOAD_PSP,
1215};
1216
Alex Deucher97b2e202015-04-20 16:51:00 -04001217struct amdgpu_firmware {
1218 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
Huang Ruie635ee02016-11-01 15:35:38 +08001219 enum amdgpu_firmware_load_type load_type;
Alex Deucher97b2e202015-04-20 16:51:00 -04001220 struct amdgpu_bo *fw_buf;
1221 unsigned int fw_size;
Huang Rui2445b222017-03-03 16:20:35 -05001222 unsigned int max_ucodes;
Huang Rui0e5ca0d2017-03-03 18:37:23 -05001223 /* firmwares are loaded by psp instead of smu from vega10 */
1224 const struct amdgpu_psp_funcs *funcs;
1225 struct amdgpu_bo *rbuf;
1226 struct mutex mutex;
Alex Deucher97b2e202015-04-20 16:51:00 -04001227};
1228
1229/*
1230 * Benchmarking
1231 */
1232void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1233
1234
1235/*
1236 * Testing
1237 */
1238void amdgpu_test_moves(struct amdgpu_device *adev);
Alex Deucher97b2e202015-04-20 16:51:00 -04001239
1240/*
1241 * MMU Notifier
1242 */
1243#if defined(CONFIG_MMU_NOTIFIER)
1244int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
1245void amdgpu_mn_unregister(struct amdgpu_bo *bo);
1246#else
Harry Wentland1d1106b2015-07-15 07:10:41 -04001247static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
Alex Deucher97b2e202015-04-20 16:51:00 -04001248{
1249 return -ENODEV;
1250}
Harry Wentland1d1106b2015-07-15 07:10:41 -04001251static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
Alex Deucher97b2e202015-04-20 16:51:00 -04001252#endif
1253
1254/*
1255 * Debugfs
1256 */
1257struct amdgpu_debugfs {
Nils Wallménius06ab6832016-05-02 12:46:15 -04001258 const struct drm_info_list *files;
Alex Deucher97b2e202015-04-20 16:51:00 -04001259 unsigned num_files;
1260};
1261
1262int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
Nils Wallménius06ab6832016-05-02 12:46:15 -04001263 const struct drm_info_list *files,
Alex Deucher97b2e202015-04-20 16:51:00 -04001264 unsigned nfiles);
1265int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
1266
1267#if defined(CONFIG_DEBUG_FS)
1268int amdgpu_debugfs_init(struct drm_minor *minor);
Alex Deucher97b2e202015-04-20 16:51:00 -04001269#endif
1270
Huang Rui50ab2532016-06-12 15:51:09 +08001271int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev);
1272
Alex Deucher97b2e202015-04-20 16:51:00 -04001273/*
1274 * amdgpu smumgr functions
1275 */
1276struct amdgpu_smumgr_funcs {
1277 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1278 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1279 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1280};
1281
1282/*
1283 * amdgpu smumgr
1284 */
1285struct amdgpu_smumgr {
1286 struct amdgpu_bo *toc_buf;
1287 struct amdgpu_bo *smu_buf;
1288 /* asic priv smu data */
1289 void *priv;
1290 spinlock_t smu_lock;
1291 /* smumgr functions */
1292 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1293 /* ucode loading complete flag */
1294 uint32_t fw_flags;
1295};
1296
1297/*
1298 * ASIC specific register table accessible by UMD
1299 */
1300struct amdgpu_allowed_register_entry {
1301 uint32_t reg_offset;
Alex Deucher97b2e202015-04-20 16:51:00 -04001302 bool grbm_indexed;
1303};
1304
Alex Deucher97b2e202015-04-20 16:51:00 -04001305/*
1306 * ASIC specific functions.
1307 */
1308struct amdgpu_asic_funcs {
1309 bool (*read_disabled_bios)(struct amdgpu_device *adev);
Alex Deucher7946b872015-11-24 10:14:28 -05001310 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
1311 u8 *bios, u32 length_bytes);
Alex Deucher97b2e202015-04-20 16:51:00 -04001312 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1313 u32 sh_num, u32 reg_offset, u32 *value);
1314 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1315 int (*reset)(struct amdgpu_device *adev);
Alex Deucher97b2e202015-04-20 16:51:00 -04001316 /* get the reference clock */
1317 u32 (*get_xclk)(struct amdgpu_device *adev);
Alex Deucher97b2e202015-04-20 16:51:00 -04001318 /* MM block clocks */
1319 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1320 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -04001321 /* static power management */
1322 int (*get_pcie_lanes)(struct amdgpu_device *adev);
1323 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
Alex Deucherbbf282d2017-03-03 17:26:10 -05001324 /* get config memsize register */
1325 u32 (*get_config_memsize)(struct amdgpu_device *adev);
Alex Deucher97b2e202015-04-20 16:51:00 -04001326};
1327
1328/*
1329 * IOCTL.
1330 */
1331int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1332 struct drm_file *filp);
1333int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1334 struct drm_file *filp);
1335
1336int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1337 struct drm_file *filp);
1338int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1339 struct drm_file *filp);
1340int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1341 struct drm_file *filp);
1342int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1343 struct drm_file *filp);
1344int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1345 struct drm_file *filp);
1346int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1347 struct drm_file *filp);
1348int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1349int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
Junwei Zhangeef18a82016-11-04 16:16:10 -04001350int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
1351 struct drm_file *filp);
Alex Deucher97b2e202015-04-20 16:51:00 -04001352
1353int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1354 struct drm_file *filp);
1355
1356/* VRAM scratch page for HDP bug, default vram page */
1357struct amdgpu_vram_scratch {
1358 struct amdgpu_bo *robj;
1359 volatile uint32_t *ptr;
1360 u64 gpu_addr;
1361};
1362
1363/*
1364 * ACPI
1365 */
1366struct amdgpu_atif_notification_cfg {
1367 bool enabled;
1368 int command_code;
1369};
1370
1371struct amdgpu_atif_notifications {
1372 bool display_switch;
1373 bool expansion_mode_change;
1374 bool thermal_state;
1375 bool forced_power_state;
1376 bool system_power_state;
1377 bool display_conf_change;
1378 bool px_gfx_switch;
1379 bool brightness_change;
1380 bool dgpu_display_event;
1381};
1382
1383struct amdgpu_atif_functions {
1384 bool system_params;
1385 bool sbios_requests;
1386 bool select_active_disp;
1387 bool lid_state;
1388 bool get_tv_standard;
1389 bool set_tv_standard;
1390 bool get_panel_expansion_mode;
1391 bool set_panel_expansion_mode;
1392 bool temperature_change;
1393 bool graphics_device_types;
1394};
1395
1396struct amdgpu_atif {
1397 struct amdgpu_atif_notifications notifications;
1398 struct amdgpu_atif_functions functions;
1399 struct amdgpu_atif_notification_cfg notification_cfg;
1400 struct amdgpu_encoder *encoder_for_bl;
1401};
1402
1403struct amdgpu_atcs_functions {
1404 bool get_ext_state;
1405 bool pcie_perf_req;
1406 bool pcie_dev_rdy;
1407 bool pcie_bus_width;
1408};
1409
1410struct amdgpu_atcs {
1411 struct amdgpu_atcs_functions functions;
1412};
1413
Alex Deucher97b2e202015-04-20 16:51:00 -04001414/*
Chunming Zhoud03846a2015-07-28 14:20:03 -04001415 * CGS
1416 */
Dave Airlie110e6f22016-04-12 13:25:48 +10001417struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1418void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
Maruthi Bayyavarapua8fe58c2015-09-22 17:05:20 -04001419
Maruthi Bayyavarapua8fe58c2015-09-22 17:05:20 -04001420/*
Alex Deucher97b2e202015-04-20 16:51:00 -04001421 * Core structure, functions and helpers.
1422 */
1423typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1424typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1425
1426typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1427typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1428
1429struct amdgpu_device {
1430 struct device *dev;
1431 struct drm_device *ddev;
1432 struct pci_dev *pdev;
Alex Deucher97b2e202015-04-20 16:51:00 -04001433
Maruthi Bayyavarapua8fe58c2015-09-22 17:05:20 -04001434#ifdef CONFIG_DRM_AMD_ACP
1435 struct amdgpu_acp acp;
1436#endif
1437
Alex Deucher97b2e202015-04-20 16:51:00 -04001438 /* ASIC */
Jammy Zhou2f7d10b2015-07-22 11:29:01 +08001439 enum amd_asic_type asic_type;
Alex Deucher97b2e202015-04-20 16:51:00 -04001440 uint32_t family;
1441 uint32_t rev_id;
1442 uint32_t external_rev_id;
1443 unsigned long flags;
1444 int usec_timeout;
1445 const struct amdgpu_asic_funcs *asic_funcs;
1446 bool shutdown;
Alex Deucher97b2e202015-04-20 16:51:00 -04001447 bool need_dma32;
1448 bool accel_working;
Christian Königedf600d2016-05-03 15:54:54 +02001449 struct work_struct reset_work;
Alex Deucher97b2e202015-04-20 16:51:00 -04001450 struct notifier_block acpi_nb;
1451 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1452 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
Christian Königedf600d2016-05-03 15:54:54 +02001453 unsigned debugfs_count;
Alex Deucher97b2e202015-04-20 16:51:00 -04001454#if defined(CONFIG_DEBUG_FS)
Tom St Denisadcec282016-04-15 13:08:44 -04001455 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
Alex Deucher97b2e202015-04-20 16:51:00 -04001456#endif
1457 struct amdgpu_atif atif;
1458 struct amdgpu_atcs atcs;
1459 struct mutex srbm_mutex;
1460 /* GRBM index mutex. Protects concurrent access to GRBM index */
1461 struct mutex grbm_idx_mutex;
1462 struct dev_pm_domain vga_pm_domain;
1463 bool have_disp_power_ref;
1464
1465 /* BIOS */
Alex Deucher0cdd5002017-02-13 16:01:58 -05001466 bool is_atom_fw;
Alex Deucher97b2e202015-04-20 16:51:00 -04001467 uint8_t *bios;
Evan Quana9f5db92016-12-07 09:56:46 +08001468 uint32_t bios_size;
Alex Deucher97b2e202015-04-20 16:51:00 -04001469 struct amdgpu_bo *stollen_vga_memory;
Alex Deuchera5bde2f2016-09-23 16:23:41 -04001470 uint32_t bios_scratch_reg_offset;
Alex Deucher97b2e202015-04-20 16:51:00 -04001471 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
1472
1473 /* Register/doorbell mmio */
1474 resource_size_t rmmio_base;
1475 resource_size_t rmmio_size;
1476 void __iomem *rmmio;
1477 /* protects concurrent MM_INDEX/DATA based register access */
1478 spinlock_t mmio_idx_lock;
1479 /* protects concurrent SMC based register access */
1480 spinlock_t smc_idx_lock;
1481 amdgpu_rreg_t smc_rreg;
1482 amdgpu_wreg_t smc_wreg;
1483 /* protects concurrent PCIE register access */
1484 spinlock_t pcie_idx_lock;
1485 amdgpu_rreg_t pcie_rreg;
1486 amdgpu_wreg_t pcie_wreg;
Huang Rui36b9a952016-08-31 13:23:25 +08001487 amdgpu_rreg_t pciep_rreg;
1488 amdgpu_wreg_t pciep_wreg;
Alex Deucher97b2e202015-04-20 16:51:00 -04001489 /* protects concurrent UVD register access */
1490 spinlock_t uvd_ctx_idx_lock;
1491 amdgpu_rreg_t uvd_ctx_rreg;
1492 amdgpu_wreg_t uvd_ctx_wreg;
1493 /* protects concurrent DIDT register access */
1494 spinlock_t didt_idx_lock;
1495 amdgpu_rreg_t didt_rreg;
1496 amdgpu_wreg_t didt_wreg;
Rex Zhuccdbb202016-06-08 12:47:41 +08001497 /* protects concurrent gc_cac register access */
1498 spinlock_t gc_cac_idx_lock;
1499 amdgpu_rreg_t gc_cac_rreg;
1500 amdgpu_wreg_t gc_cac_wreg;
Alex Deucher97b2e202015-04-20 16:51:00 -04001501 /* protects concurrent ENDPOINT (audio) register access */
1502 spinlock_t audio_endpt_idx_lock;
1503 amdgpu_block_rreg_t audio_endpt_rreg;
1504 amdgpu_block_wreg_t audio_endpt_wreg;
1505 void __iomem *rio_mem;
1506 resource_size_t rio_mem_size;
1507 struct amdgpu_doorbell doorbell;
1508
1509 /* clock/pll info */
1510 struct amdgpu_clock clock;
1511
1512 /* MC */
1513 struct amdgpu_mc mc;
1514 struct amdgpu_gart gart;
1515 struct amdgpu_dummy_page dummy_page;
1516 struct amdgpu_vm_manager vm_manager;
Alex Xiee60f8db2017-03-09 11:36:26 -05001517 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
Alex Deucher97b2e202015-04-20 16:51:00 -04001518
1519 /* memory management */
1520 struct amdgpu_mman mman;
Alex Deucher97b2e202015-04-20 16:51:00 -04001521 struct amdgpu_vram_scratch vram_scratch;
1522 struct amdgpu_wb wb;
1523 atomic64_t vram_usage;
1524 atomic64_t vram_vis_usage;
1525 atomic64_t gtt_usage;
1526 atomic64_t num_bytes_moved;
Christian Königdbd5ed62016-06-21 16:28:14 +02001527 atomic64_t num_evictions;
Marek Olšákd94aed52015-05-05 21:13:49 +02001528 atomic_t gpu_reset_counter;
Alex Deucher97b2e202015-04-20 16:51:00 -04001529
Marek Olšák95844d22016-08-17 23:49:27 +02001530 /* data for buffer migration throttling */
1531 struct {
1532 spinlock_t lock;
1533 s64 last_update_us;
1534 s64 accum_us; /* accumulated microseconds */
1535 u32 log2_max_MBps;
1536 } mm_stats;
1537
Alex Deucher97b2e202015-04-20 16:51:00 -04001538 /* display */
Emily Deng9accf2f2016-08-10 16:01:25 +08001539 bool enable_virtual_display;
Alex Deucher97b2e202015-04-20 16:51:00 -04001540 struct amdgpu_mode_info mode_info;
1541 struct work_struct hotplug_work;
1542 struct amdgpu_irq_src crtc_irq;
1543 struct amdgpu_irq_src pageflip_irq;
1544 struct amdgpu_irq_src hpd_irq;
1545
1546 /* rings */
Christian König76bf0db2016-06-01 15:10:02 +02001547 u64 fence_context;
Alex Deucher97b2e202015-04-20 16:51:00 -04001548 unsigned num_rings;
1549 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
1550 bool ib_pool_ready;
1551 struct amdgpu_sa_manager ring_tmp_bo;
1552
1553 /* interrupts */
1554 struct amdgpu_irq irq;
1555
Alex Deucher1f7371b2015-12-02 17:46:21 -05001556 /* powerplay */
1557 struct amd_powerplay powerplay;
Jammy Zhoue61710c2015-11-10 18:31:08 -05001558 bool pp_enabled;
Eric Huangf3898ea2015-12-11 16:24:34 -05001559 bool pp_force_state_enabled;
Alex Deucher1f7371b2015-12-02 17:46:21 -05001560
Alex Deucher97b2e202015-04-20 16:51:00 -04001561 /* dpm */
1562 struct amdgpu_pm pm;
1563 u32 cg_flags;
1564 u32 pg_flags;
1565
1566 /* amdgpu smumgr */
1567 struct amdgpu_smumgr smu;
1568
1569 /* gfx */
1570 struct amdgpu_gfx gfx;
1571
1572 /* sdma */
Alex Deucherc113ea12015-10-08 16:30:37 -04001573 struct amdgpu_sdma sdma;
Alex Deucher97b2e202015-04-20 16:51:00 -04001574
1575 /* uvd */
Alex Deucher97b2e202015-04-20 16:51:00 -04001576 struct amdgpu_uvd uvd;
1577
1578 /* vce */
1579 struct amdgpu_vce vce;
1580
1581 /* firmwares */
1582 struct amdgpu_firmware firmware;
1583
Huang Rui0e5ca0d2017-03-03 18:37:23 -05001584 /* PSP */
1585 struct psp_context psp;
1586
Alex Deucher97b2e202015-04-20 16:51:00 -04001587 /* GDS */
1588 struct amdgpu_gds gds;
1589
Alex Deuchera1255102016-10-13 17:41:13 -04001590 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
Alex Deucher97b2e202015-04-20 16:51:00 -04001591 int num_ip_blocks;
Alex Deucher97b2e202015-04-20 16:51:00 -04001592 struct mutex mn_lock;
1593 DECLARE_HASHTABLE(mn_hash, 7);
1594
1595 /* tracking pinned memory */
1596 u64 vram_pin_size;
Chunming Zhoue131b912016-04-05 10:48:48 +08001597 u64 invisible_pin_size;
Alex Deucher97b2e202015-04-20 16:51:00 -04001598 u64 gart_pin_size;
Oded Gabbay130e0372015-06-12 21:35:14 +03001599
1600 /* amdkfd interface */
1601 struct kfd_dev *kfd;
Chunming Zhou23ca0e42015-07-06 13:42:58 +08001602
Xiangliang Yu5a5099c2017-01-09 18:06:57 -05001603 struct amdgpu_virt virt;
Chunming Zhou0c4e7fa2016-08-17 11:41:30 +08001604
1605 /* link all shadow bo */
1606 struct list_head shadow_list;
1607 struct mutex shadow_list_lock;
Chunming Zhou5c1354b2016-08-30 16:13:10 +08001608 /* link all gtt */
1609 spinlock_t gtt_list_lock;
1610 struct list_head gtt_list;
1611
Jim Quc836fec2017-02-10 15:59:59 +08001612 /* record hw reset is performed */
1613 bool has_hw_reset;
1614
Alex Deucher97b2e202015-04-20 16:51:00 -04001615};
1616
Christian Königa7d64de2016-09-15 14:58:48 +02001617static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
1618{
1619 return container_of(bdev, struct amdgpu_device, mman.bdev);
1620}
1621
Alex Deucher97b2e202015-04-20 16:51:00 -04001622bool amdgpu_device_is_px(struct drm_device *dev);
1623int amdgpu_device_init(struct amdgpu_device *adev,
1624 struct drm_device *ddev,
1625 struct pci_dev *pdev,
1626 uint32_t flags);
1627void amdgpu_device_fini(struct amdgpu_device *adev);
1628int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
1629
1630uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
Monk Liu15d72fd2017-01-25 15:07:40 +08001631 uint32_t acc_flags);
Alex Deucher97b2e202015-04-20 16:51:00 -04001632void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
Monk Liu15d72fd2017-01-25 15:07:40 +08001633 uint32_t acc_flags);
Alex Deucher97b2e202015-04-20 16:51:00 -04001634u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
1635void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
1636
1637u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
1638void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
Ken Wang832be402016-03-18 15:23:08 +08001639u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index);
1640void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v);
Alex Deucher97b2e202015-04-20 16:51:00 -04001641
1642/*
Alex Deucher97b2e202015-04-20 16:51:00 -04001643 * Registers read & write functions.
1644 */
Monk Liu15d72fd2017-01-25 15:07:40 +08001645
1646#define AMDGPU_REGS_IDX (1<<0)
1647#define AMDGPU_REGS_NO_KIQ (1<<1)
1648
1649#define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1650#define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1651
1652#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0)
1653#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX)
1654#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0))
1655#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0)
1656#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX)
Alex Deucher97b2e202015-04-20 16:51:00 -04001657#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1658#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1659#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1660#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
Huang Rui36b9a952016-08-31 13:23:25 +08001661#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1662#define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
Alex Deucher97b2e202015-04-20 16:51:00 -04001663#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1664#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1665#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1666#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1667#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1668#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
Rex Zhuccdbb202016-06-08 12:47:41 +08001669#define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1670#define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
Alex Deucher97b2e202015-04-20 16:51:00 -04001671#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1672#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1673#define WREG32_P(reg, val, mask) \
1674 do { \
1675 uint32_t tmp_ = RREG32(reg); \
1676 tmp_ &= (mask); \
1677 tmp_ |= ((val) & ~(mask)); \
1678 WREG32(reg, tmp_); \
1679 } while (0)
1680#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1681#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1682#define WREG32_PLL_P(reg, val, mask) \
1683 do { \
1684 uint32_t tmp_ = RREG32_PLL(reg); \
1685 tmp_ &= (mask); \
1686 tmp_ |= ((val) & ~(mask)); \
1687 WREG32_PLL(reg, tmp_); \
1688 } while (0)
1689#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
1690#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
1691#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
1692
1693#define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
1694#define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
Ken Wang832be402016-03-18 15:23:08 +08001695#define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index))
1696#define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v))
Alex Deucher97b2e202015-04-20 16:51:00 -04001697
1698#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1699#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1700
1701#define REG_SET_FIELD(orig_val, reg, field, field_val) \
1702 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1703 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1704
1705#define REG_GET_FIELD(value, reg, field) \
1706 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
1707
Tom St Denis61cb8ce2016-08-09 10:13:21 -04001708#define WREG32_FIELD(reg, field, val) \
1709 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1710
Tom St Denisccaf3572017-04-04 09:14:13 -04001711#define WREG32_FIELD_OFFSET(reg, offset, field, val) \
1712 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1713
Alex Deucher97b2e202015-04-20 16:51:00 -04001714/*
1715 * BIOS helpers.
1716 */
1717#define RBIOS8(i) (adev->bios[i])
1718#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1719#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1720
1721/*
1722 * RING helpers.
1723 */
1724static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
1725{
1726 if (ring->count_dw <= 0)
Jammy Zhou86c2b792015-05-13 22:52:42 +08001727 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
Ken Wang536fbf92016-03-12 09:32:30 +08001728 ring->ring[ring->wptr++ & ring->buf_mask] = v;
Alex Deucher97b2e202015-04-20 16:51:00 -04001729 ring->wptr &= ring->ptr_mask;
1730 ring->count_dw--;
Alex Deucher97b2e202015-04-20 16:51:00 -04001731}
1732
Monk Liu0a8e1472017-01-17 10:52:33 +08001733static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring, void *src, int count_dw)
1734{
1735 unsigned occupied, chunk1, chunk2;
1736 void *dst;
1737
Nikola Pajkovsky5b9c58f2017-05-04 12:39:50 -04001738 if (unlikely(ring->count_dw < count_dw)) {
Monk Liu0a8e1472017-01-17 10:52:33 +08001739 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
Nikola Pajkovsky5b9c58f2017-05-04 12:39:50 -04001740 return;
Monk Liu0a8e1472017-01-17 10:52:33 +08001741 }
Nikola Pajkovsky5b9c58f2017-05-04 12:39:50 -04001742
1743 occupied = ring->wptr & ring->buf_mask;
1744 dst = (void *)&ring->ring[occupied];
1745 chunk1 = ring->buf_mask + 1 - occupied;
1746 chunk1 = (chunk1 >= count_dw) ? count_dw: chunk1;
1747 chunk2 = count_dw - chunk1;
1748 chunk1 <<= 2;
1749 chunk2 <<= 2;
1750
1751 if (chunk1)
1752 memcpy(dst, src, chunk1);
1753
1754 if (chunk2) {
1755 src += chunk1;
1756 dst = (void *)ring->ring;
1757 memcpy(dst, src, chunk2);
1758 }
1759
1760 ring->wptr += count_dw;
1761 ring->wptr &= ring->ptr_mask;
1762 ring->count_dw -= count_dw;
Monk Liu0a8e1472017-01-17 10:52:33 +08001763}
1764
Alex Deucherc113ea12015-10-08 16:30:37 -04001765static inline struct amdgpu_sdma_instance *
1766amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
Jammy Zhou4b2f7e22015-09-01 12:56:17 +08001767{
1768 struct amdgpu_device *adev = ring->adev;
1769 int i;
1770
Alex Deucherc113ea12015-10-08 16:30:37 -04001771 for (i = 0; i < adev->sdma.num_instances; i++)
1772 if (&adev->sdma.instance[i].ring == ring)
Jammy Zhou4b2f7e22015-09-01 12:56:17 +08001773 break;
1774
1775 if (i < AMDGPU_MAX_SDMA_INSTANCES)
Alex Deucherc113ea12015-10-08 16:30:37 -04001776 return &adev->sdma.instance[i];
Jammy Zhou4b2f7e22015-09-01 12:56:17 +08001777 else
1778 return NULL;
1779}
1780
Alex Deucher97b2e202015-04-20 16:51:00 -04001781/*
1782 * ASICs macro.
1783 */
1784#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
1785#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
Alex Deucher97b2e202015-04-20 16:51:00 -04001786#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1787#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1788#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -04001789#define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1790#define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1791#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
Alex Deucher97b2e202015-04-20 16:51:00 -04001792#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
Alex Deucher7946b872015-11-24 10:14:28 -05001793#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
Alex Deucher97b2e202015-04-20 16:51:00 -04001794#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
Alex Deucherbbf282d2017-03-03 17:26:10 -05001795#define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
Alex Deucher97b2e202015-04-20 16:51:00 -04001796#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
1797#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
1798#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
Christian Königde9ea7b2016-08-12 11:33:30 +02001799#define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
Alex Deucher97b2e202015-04-20 16:51:00 -04001800#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
Alex Xie54635452017-02-14 12:22:57 -05001801#define amdgpu_vm_get_pte_flags(adev, flags) (adev)->gart.gart_funcs->get_vm_pte_flags((adev),(flags))
Alex Deucher97b2e202015-04-20 16:51:00 -04001802#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
1803#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
Christian Königbbec97a2016-07-05 21:07:17 +02001804#define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t))
Alex Deucher97b2e202015-04-20 16:51:00 -04001805#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
1806#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
1807#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
Christian Königd88bf582016-05-06 17:50:03 +02001808#define amdgpu_ring_emit_ib(r, ib, vm_id, c) (r)->funcs->emit_ib((r), (ib), (vm_id), (c))
Christian Königb8c7b392016-03-01 15:42:52 +01001809#define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
Alex Deucher97b2e202015-04-20 16:51:00 -04001810#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
Chunming Zhou890ee232015-06-01 14:35:03 +08001811#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
Alex Deucher97b2e202015-04-20 16:51:00 -04001812#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
Christian Königd2edb072015-05-11 14:10:34 +02001813#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
Chunming Zhou11afbde2016-03-03 11:38:48 +08001814#define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r))
Monk Liuc2167a62016-08-26 14:12:37 +08001815#define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
Monk Liu753ad492016-08-26 13:28:28 +08001816#define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
Xiangliang Yub6091c12017-01-10 12:53:52 +08001817#define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d))
1818#define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
Monk Liu3b4d68e2017-05-01 18:09:22 +08001819#define amdgpu_ring_emit_tmz(r, b) (r)->funcs->emit_tmz((r), (b))
Christian König9e5d53092016-01-31 12:20:55 +01001820#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
Monk Liu03ccf482016-01-14 19:07:38 +08001821#define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
1822#define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
Alex Deucher97b2e202015-04-20 16:51:00 -04001823#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
1824#define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
1825#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
1826#define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
1827#define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
1828#define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
Alex Deucher97b2e202015-04-20 16:51:00 -04001829#define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
1830#define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
1831#define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
1832#define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
1833#define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
1834#define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
Alex Deuchercb9e59d2016-05-05 16:03:57 -04001835#define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async))
Alex Deucher97b2e202015-04-20 16:51:00 -04001836#define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
1837#define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
1838#define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
1839#define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
1840#define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
Chunming Zhouc7ae72c2015-08-25 17:23:45 +08001841#define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
Chunming Zhou6e7a3842015-08-27 13:46:09 +08001842#define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
Alex Deucherb95e31f2016-07-07 15:01:42 -04001843#define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
Tom St Denis9559ef52016-06-28 10:26:48 -04001844#define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
Alex Deucher97b2e202015-04-20 16:51:00 -04001845#define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
Huang Rui0e5ca0d2017-03-03 18:37:23 -05001846#define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i))
Alex Deucher97b2e202015-04-20 16:51:00 -04001847
1848/* Common functions */
1849int amdgpu_gpu_reset(struct amdgpu_device *adev);
Chunming Zhou3ad81f12016-08-05 17:30:17 +08001850bool amdgpu_need_backup(struct amdgpu_device *adev);
Alex Deucher97b2e202015-04-20 16:51:00 -04001851void amdgpu_pci_config_reset(struct amdgpu_device *adev);
Jim Quc836fec2017-02-10 15:59:59 +08001852bool amdgpu_need_post(struct amdgpu_device *adev);
Alex Deucher97b2e202015-04-20 16:51:00 -04001853void amdgpu_update_display_priority(struct amdgpu_device *adev);
Chunming Zhoud5fc5e82015-07-21 16:52:10 +08001854
Alex Deucher97b2e202015-04-20 16:51:00 -04001855int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data);
1856int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
1857 u32 ip_instance, u32 ring,
1858 struct amdgpu_ring **out_ring);
Samuel Pitoisetfad06122017-02-09 11:33:37 +01001859void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes);
Christian König765e7fb2016-09-15 15:06:50 +02001860void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain);
Alex Deucher97b2e202015-04-20 16:51:00 -04001861bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
Christian König2f568db2016-02-23 12:36:59 +01001862int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages);
Alex Deucher97b2e202015-04-20 16:51:00 -04001863int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
1864 uint32_t flags);
1865bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
Christian Königcc325d12016-02-08 11:08:35 +01001866struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
Christian Königd7006962016-02-08 10:57:22 +01001867bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1868 unsigned long end);
Christian König2f568db2016-02-23 12:36:59 +01001869bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
1870 int *last_invalidated);
Alex Deucher97b2e202015-04-20 16:51:00 -04001871bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
Chunming Zhou6b777602016-09-21 16:19:19 +08001872uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
Alex Deucher97b2e202015-04-20 16:51:00 -04001873 struct ttm_mem_reg *mem);
1874void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
1875void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
1876void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
Baoyou Xie9f31a0b2016-09-15 21:43:26 +08001877int amdgpu_ttm_init(struct amdgpu_device *adev);
1878void amdgpu_ttm_fini(struct amdgpu_device *adev);
Alex Deucher97b2e202015-04-20 16:51:00 -04001879void amdgpu_program_register_sequence(struct amdgpu_device *adev,
1880 const u32 *registers,
1881 const u32 array_size);
1882
1883bool amdgpu_device_is_px(struct drm_device *dev);
1884/* atpx handler */
1885#if defined(CONFIG_VGA_SWITCHEROO)
1886void amdgpu_register_atpx_handler(void);
1887void amdgpu_unregister_atpx_handler(void);
Alex Deuchera78fe132016-06-01 13:08:21 -04001888bool amdgpu_has_atpx_dgpu_power_cntl(void);
Alex Deucher2f5af822016-06-02 09:04:01 -04001889bool amdgpu_is_atpx_hybrid(void);
Alex Deucherefc83cf2016-09-14 14:01:41 -04001890bool amdgpu_atpx_dgpu_req_power_for_displays(void);
Alex Xie714f88e2017-04-05 11:07:13 -04001891bool amdgpu_has_atpx(void);
Alex Deucher97b2e202015-04-20 16:51:00 -04001892#else
1893static inline void amdgpu_register_atpx_handler(void) {}
1894static inline void amdgpu_unregister_atpx_handler(void) {}
Alex Deuchera78fe132016-06-01 13:08:21 -04001895static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
Alex Deucher2f5af822016-06-02 09:04:01 -04001896static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
Alex Deucherefc83cf2016-09-14 14:01:41 -04001897static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
Alex Xie714f88e2017-04-05 11:07:13 -04001898static inline bool amdgpu_has_atpx(void) { return false; }
Alex Deucher97b2e202015-04-20 16:51:00 -04001899#endif
1900
1901/*
1902 * KMS
1903 */
1904extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
Nils Wallméniusf498d9e2016-04-10 16:29:59 +02001905extern const int amdgpu_max_kms_ioctl;
Alex Deucher97b2e202015-04-20 16:51:00 -04001906
1907int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
Gabriel Krisman Bertazi11b3c202017-01-06 15:57:31 -02001908void amdgpu_driver_unload_kms(struct drm_device *dev);
Alex Deucher97b2e202015-04-20 16:51:00 -04001909void amdgpu_driver_lastclose_kms(struct drm_device *dev);
1910int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1911void amdgpu_driver_postclose_kms(struct drm_device *dev,
1912 struct drm_file *file_priv);
Alex Deucherfaefba92016-12-06 10:38:29 -05001913int amdgpu_suspend(struct amdgpu_device *adev);
Alex Deucher810ddc32016-08-23 13:25:49 -04001914int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon);
1915int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon);
Thierry Reding88e72712015-09-24 18:35:31 +02001916u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
1917int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
1918void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
Alex Deucher97b2e202015-04-20 16:51:00 -04001919long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
1920 unsigned long arg);
1921
1922/*
Alex Deucher97b2e202015-04-20 16:51:00 -04001923 * functions used by amdgpu_encoder.c
1924 */
1925struct amdgpu_afmt_acr {
1926 u32 clock;
1927
1928 int n_32khz;
1929 int cts_32khz;
1930
1931 int n_44_1khz;
1932 int cts_44_1khz;
1933
1934 int n_48khz;
1935 int cts_48khz;
1936
1937};
1938
1939struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1940
1941/* amdgpu_acpi.c */
1942#if defined(CONFIG_ACPI)
1943int amdgpu_acpi_init(struct amdgpu_device *adev);
1944void amdgpu_acpi_fini(struct amdgpu_device *adev);
1945bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1946int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1947 u8 perf_req, bool advertise);
1948int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
1949#else
1950static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
1951static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
1952#endif
1953
1954struct amdgpu_bo_va_mapping *
1955amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1956 uint64_t addr, struct amdgpu_bo **bo);
Christian Königc855e252016-09-05 17:00:57 +02001957int amdgpu_cs_sysvm_access_required(struct amdgpu_cs_parser *parser);
Alex Deucher97b2e202015-04-20 16:51:00 -04001958
1959#include "amdgpu_object.h"
Alex Deucher97b2e202015-04-20 16:51:00 -04001960#endif