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Hisashi Nakamura0d0771ab2013-09-04 12:45:57 +09001/*
2 * Device Tree Source for the r8a7791 SoC
3 *
4 * Copyright (C) 2013 Renesas Electronics Corporation
5 * Copyright (C) 2013 Renesas Solutions Corp.
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
Laurent Pinchart59e79892013-12-11 15:05:16 +010012#include <dt-bindings/clock/r8a7791-clock.h>
Laurent Pinchart5f75e732013-11-19 03:18:25 +010013#include <dt-bindings/interrupt-controller/arm-gic.h>
14#include <dt-bindings/interrupt-controller/irq.h>
15
Hisashi Nakamura0d0771ab2013-09-04 12:45:57 +090016/ {
17 compatible = "renesas,r8a7791";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
21
22 cpus {
23 #address-cells = <1>;
24 #size-cells = <0>;
25
26 cpu0: cpu@0 {
27 device_type = "cpu";
28 compatible = "arm,cortex-a15";
29 reg = <0>;
30 clock-frequency = <1300000000>;
31 };
Magnus Damm15ab4262013-10-01 17:13:07 +090032
33 cpu1: cpu@1 {
34 device_type = "cpu";
35 compatible = "arm,cortex-a15";
36 reg = <1>;
37 clock-frequency = <1300000000>;
38 };
Hisashi Nakamura0d0771ab2013-09-04 12:45:57 +090039 };
40
41 gic: interrupt-controller@f1001000 {
42 compatible = "arm,cortex-a15-gic";
43 #interrupt-cells = <3>;
44 #address-cells = <0>;
45 interrupt-controller;
46 reg = <0 0xf1001000 0 0x1000>,
47 <0 0xf1002000 0 0x1000>,
48 <0 0xf1004000 0 0x2000>,
49 <0 0xf1006000 0 0x2000>;
Laurent Pinchart5f75e732013-11-19 03:18:25 +010050 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
Hisashi Nakamura0d0771ab2013-09-04 12:45:57 +090051 };
Magnus Dammd77db732013-10-01 17:12:29 +090052
Magnus Damm89fbba12013-11-21 14:22:00 +090053 gpio0: gpio@e6050000 {
Magnus Dammab87e3f2013-10-08 12:39:30 +090054 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
Magnus Damm89fbba12013-11-21 14:22:00 +090055 reg = <0 0xe6050000 0 0x50>;
Magnus Dammab87e3f2013-10-08 12:39:30 +090056 interrupt-parent = <&gic>;
Laurent Pinchart5f75e732013-11-19 03:18:25 +010057 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
Magnus Dammab87e3f2013-10-08 12:39:30 +090058 #gpio-cells = <2>;
59 gpio-controller;
60 gpio-ranges = <&pfc 0 0 32>;
61 #interrupt-cells = <2>;
62 interrupt-controller;
63 };
64
Magnus Damm89fbba12013-11-21 14:22:00 +090065 gpio1: gpio@e6051000 {
Magnus Dammab87e3f2013-10-08 12:39:30 +090066 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
Magnus Damm89fbba12013-11-21 14:22:00 +090067 reg = <0 0xe6051000 0 0x50>;
Magnus Dammab87e3f2013-10-08 12:39:30 +090068 interrupt-parent = <&gic>;
Laurent Pinchart5f75e732013-11-19 03:18:25 +010069 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
Magnus Dammab87e3f2013-10-08 12:39:30 +090070 #gpio-cells = <2>;
71 gpio-controller;
72 gpio-ranges = <&pfc 0 32 32>;
73 #interrupt-cells = <2>;
74 interrupt-controller;
75 };
76
Magnus Damm89fbba12013-11-21 14:22:00 +090077 gpio2: gpio@e6052000 {
Magnus Dammab87e3f2013-10-08 12:39:30 +090078 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
Magnus Damm89fbba12013-11-21 14:22:00 +090079 reg = <0 0xe6052000 0 0x50>;
Magnus Dammab87e3f2013-10-08 12:39:30 +090080 interrupt-parent = <&gic>;
Laurent Pinchart5f75e732013-11-19 03:18:25 +010081 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
Magnus Dammab87e3f2013-10-08 12:39:30 +090082 #gpio-cells = <2>;
83 gpio-controller;
84 gpio-ranges = <&pfc 0 64 32>;
85 #interrupt-cells = <2>;
86 interrupt-controller;
87 };
88
Magnus Damm89fbba12013-11-21 14:22:00 +090089 gpio3: gpio@e6053000 {
Magnus Dammab87e3f2013-10-08 12:39:30 +090090 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
Magnus Damm89fbba12013-11-21 14:22:00 +090091 reg = <0 0xe6053000 0 0x50>;
Magnus Dammab87e3f2013-10-08 12:39:30 +090092 interrupt-parent = <&gic>;
Laurent Pinchart5f75e732013-11-19 03:18:25 +010093 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
Magnus Dammab87e3f2013-10-08 12:39:30 +090094 #gpio-cells = <2>;
95 gpio-controller;
96 gpio-ranges = <&pfc 0 96 32>;
97 #interrupt-cells = <2>;
98 interrupt-controller;
99 };
100
Magnus Damm89fbba12013-11-21 14:22:00 +0900101 gpio4: gpio@e6054000 {
Magnus Dammab87e3f2013-10-08 12:39:30 +0900102 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
Magnus Damm89fbba12013-11-21 14:22:00 +0900103 reg = <0 0xe6054000 0 0x50>;
Magnus Dammab87e3f2013-10-08 12:39:30 +0900104 interrupt-parent = <&gic>;
Laurent Pinchart5f75e732013-11-19 03:18:25 +0100105 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
Magnus Dammab87e3f2013-10-08 12:39:30 +0900106 #gpio-cells = <2>;
107 gpio-controller;
108 gpio-ranges = <&pfc 0 128 32>;
109 #interrupt-cells = <2>;
110 interrupt-controller;
111 };
112
Magnus Damm89fbba12013-11-21 14:22:00 +0900113 gpio5: gpio@e6055000 {
Magnus Dammab87e3f2013-10-08 12:39:30 +0900114 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
Magnus Damm89fbba12013-11-21 14:22:00 +0900115 reg = <0 0xe6055000 0 0x50>;
Magnus Dammab87e3f2013-10-08 12:39:30 +0900116 interrupt-parent = <&gic>;
Laurent Pinchart5f75e732013-11-19 03:18:25 +0100117 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
Magnus Dammab87e3f2013-10-08 12:39:30 +0900118 #gpio-cells = <2>;
119 gpio-controller;
120 gpio-ranges = <&pfc 0 160 32>;
121 #interrupt-cells = <2>;
122 interrupt-controller;
123 };
124
Magnus Damm89fbba12013-11-21 14:22:00 +0900125 gpio6: gpio@e6055400 {
Magnus Dammab87e3f2013-10-08 12:39:30 +0900126 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
Magnus Damm89fbba12013-11-21 14:22:00 +0900127 reg = <0 0xe6055400 0 0x50>;
Magnus Dammab87e3f2013-10-08 12:39:30 +0900128 interrupt-parent = <&gic>;
Laurent Pinchart5f75e732013-11-19 03:18:25 +0100129 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
Magnus Dammab87e3f2013-10-08 12:39:30 +0900130 #gpio-cells = <2>;
131 gpio-controller;
132 gpio-ranges = <&pfc 0 192 32>;
133 #interrupt-cells = <2>;
134 interrupt-controller;
135 };
136
Magnus Damm89fbba12013-11-21 14:22:00 +0900137 gpio7: gpio@e6055800 {
Magnus Dammab87e3f2013-10-08 12:39:30 +0900138 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
Magnus Damm89fbba12013-11-21 14:22:00 +0900139 reg = <0 0xe6055800 0 0x50>;
Magnus Dammab87e3f2013-10-08 12:39:30 +0900140 interrupt-parent = <&gic>;
Laurent Pinchart5f75e732013-11-19 03:18:25 +0100141 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
Magnus Dammab87e3f2013-10-08 12:39:30 +0900142 #gpio-cells = <2>;
143 gpio-controller;
144 gpio-ranges = <&pfc 0 224 26>;
145 #interrupt-cells = <2>;
146 interrupt-controller;
147 };
148
Magnus Dammd103f4d2013-11-20 16:59:48 +0900149 thermal@e61f0000 {
150 compatible = "renesas,thermal-r8a7791", "renesas,rcar-thermal";
151 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
152 interrupt-parent = <&gic>;
153 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
Geert Uytterhoeven563bc8e2014-01-07 19:57:13 +0100154 clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;
Magnus Dammd103f4d2013-11-20 16:59:48 +0900155 };
156
Magnus Damm03586ac2013-10-01 17:12:38 +0900157 timer {
158 compatible = "arm,armv7-timer";
Laurent Pinchart5f75e732013-11-19 03:18:25 +0100159 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
160 <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
161 <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
162 <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
Magnus Damm03586ac2013-10-01 17:12:38 +0900163 };
164
Magnus Dammd77db732013-10-01 17:12:29 +0900165 irqc0: interrupt-controller@e61c0000 {
Magnus Damm26041b02013-11-20 13:18:05 +0900166 compatible = "renesas,irqc-r8a7791", "renesas,irqc";
Magnus Dammd77db732013-10-01 17:12:29 +0900167 #interrupt-cells = <2>;
168 interrupt-controller;
169 reg = <0 0xe61c0000 0 0x200>;
170 interrupt-parent = <&gic>;
Laurent Pinchart5f75e732013-11-19 03:18:25 +0100171 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
172 <0 1 IRQ_TYPE_LEVEL_HIGH>,
173 <0 2 IRQ_TYPE_LEVEL_HIGH>,
174 <0 3 IRQ_TYPE_LEVEL_HIGH>,
175 <0 12 IRQ_TYPE_LEVEL_HIGH>,
176 <0 13 IRQ_TYPE_LEVEL_HIGH>,
177 <0 14 IRQ_TYPE_LEVEL_HIGH>,
178 <0 15 IRQ_TYPE_LEVEL_HIGH>,
179 <0 16 IRQ_TYPE_LEVEL_HIGH>,
180 <0 17 IRQ_TYPE_LEVEL_HIGH>;
Magnus Dammd77db732013-10-01 17:12:29 +0900181 };
Magnus Damm55146922013-10-08 12:39:01 +0900182
183 pfc: pfc@e6060000 {
184 compatible = "renesas,pfc-r8a7791";
185 reg = <0 0xe6060000 0 0x250>;
186 #gpio-range-cells = <3>;
187 };
Laurent Pinchart59e79892013-12-11 15:05:16 +0100188
Laurent Pinchart9640cf22013-12-11 14:14:22 +0100189 scifa0: serial@e6c40000 {
190 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
191 reg = <0 0xe6c40000 0 64>;
192 interrupt-parent = <&gic>;
193 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
194 clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>;
195 clock-names = "sci_ick";
196 status = "disabled";
197 };
198
199 scifa1: serial@e6c50000 {
200 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
201 interrupt-parent = <&gic>;
202 reg = <0 0xe6c50000 0 64>;
203 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
204 clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>;
205 clock-names = "sci_ick";
206 status = "disabled";
207 };
208
209 scifa2: serial@e6c60000 {
210 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
211 interrupt-parent = <&gic>;
212 reg = <0 0xe6c60000 0 64>;
213 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
214 clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>;
215 clock-names = "sci_ick";
216 status = "disabled";
217 };
218
219 scifa3: serial@e6c70000 {
220 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
221 interrupt-parent = <&gic>;
222 reg = <0 0xe6c70000 0 64>;
223 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
224 clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>;
225 clock-names = "sci_ick";
226 status = "disabled";
227 };
228
229 scifa4: serial@e6c78000 {
230 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
231 interrupt-parent = <&gic>;
232 reg = <0 0xe6c78000 0 64>;
233 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
234 clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>;
235 clock-names = "sci_ick";
236 status = "disabled";
237 };
238
239 scifa5: serial@e6c80000 {
240 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
241 interrupt-parent = <&gic>;
242 reg = <0 0xe6c80000 0 64>;
243 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
244 clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>;
245 clock-names = "sci_ick";
246 status = "disabled";
247 };
248
249 scifb0: serial@e6c20000 {
250 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
251 interrupt-parent = <&gic>;
252 reg = <0 0xe6c20000 0 64>;
253 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
254 clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>;
255 clock-names = "sci_ick";
256 status = "disabled";
257 };
258
259 scifb1: serial@e6c30000 {
260 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
261 interrupt-parent = <&gic>;
262 reg = <0 0xe6c30000 0 64>;
263 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
264 clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>;
265 clock-names = "sci_ick";
266 status = "disabled";
267 };
268
269 scifb2: serial@e6ce0000 {
270 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
271 interrupt-parent = <&gic>;
272 reg = <0 0xe6ce0000 0 64>;
273 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
274 clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>;
275 clock-names = "sci_ick";
276 status = "disabled";
277 };
278
279 scif0: serial@e6e60000 {
280 compatible = "renesas,scif-r8a7791", "renesas,scif";
281 interrupt-parent = <&gic>;
282 reg = <0 0xe6e60000 0 64>;
283 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
284 clocks = <&mstp7_clks R8A7791_CLK_SCIF0>;
285 clock-names = "sci_ick";
286 status = "disabled";
287 };
288
289 scif1: serial@e6e68000 {
290 compatible = "renesas,scif-r8a7791", "renesas,scif";
291 interrupt-parent = <&gic>;
292 reg = <0 0xe6e68000 0 64>;
293 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
294 clocks = <&mstp7_clks R8A7791_CLK_SCIF1>;
295 clock-names = "sci_ick";
296 status = "disabled";
297 };
298
299 scif2: serial@e6e58000 {
300 compatible = "renesas,scif-r8a7791", "renesas,scif";
301 interrupt-parent = <&gic>;
302 reg = <0 0xe6e58000 0 64>;
303 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&mstp7_clks R8A7791_CLK_SCIF2>;
305 clock-names = "sci_ick";
306 status = "disabled";
307 };
308
309 scif3: serial@e6ea8000 {
310 compatible = "renesas,scif-r8a7791", "renesas,scif";
311 interrupt-parent = <&gic>;
312 reg = <0 0xe6ea8000 0 64>;
313 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
314 clocks = <&mstp7_clks R8A7791_CLK_SCIF3>;
315 clock-names = "sci_ick";
316 status = "disabled";
317 };
318
319 scif4: serial@e6ee0000 {
320 compatible = "renesas,scif-r8a7791", "renesas,scif";
321 interrupt-parent = <&gic>;
322 reg = <0 0xe6ee0000 0 64>;
323 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
324 clocks = <&mstp7_clks R8A7791_CLK_SCIF4>;
325 clock-names = "sci_ick";
326 status = "disabled";
327 };
328
329 scif5: serial@e6ee8000 {
330 compatible = "renesas,scif-r8a7791", "renesas,scif";
331 interrupt-parent = <&gic>;
332 reg = <0 0xe6ee8000 0 64>;
333 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
334 clocks = <&mstp7_clks R8A7791_CLK_SCIF5>;
335 clock-names = "sci_ick";
336 status = "disabled";
337 };
338
339 hscif0: serial@e62c0000 {
340 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
341 interrupt-parent = <&gic>;
342 reg = <0 0xe62c0000 0 96>;
343 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
344 clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>;
345 clock-names = "sci_ick";
346 status = "disabled";
347 };
348
349 hscif1: serial@e62c8000 {
350 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
351 interrupt-parent = <&gic>;
352 reg = <0 0xe62c8000 0 96>;
353 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
354 clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>;
355 clock-names = "sci_ick";
356 status = "disabled";
357 };
358
359 hscif2: serial@e62d0000 {
360 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
361 interrupt-parent = <&gic>;
362 reg = <0 0xe62d0000 0 96>;
363 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
364 clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>;
365 clock-names = "sci_ick";
366 status = "disabled";
367 };
368
Laurent Pinchart59e79892013-12-11 15:05:16 +0100369 clocks {
370 #address-cells = <2>;
371 #size-cells = <2>;
372 ranges;
373
374 /* External root clock */
375 extal_clk: extal_clk {
376 compatible = "fixed-clock";
377 #clock-cells = <0>;
378 /* This value must be overriden by the board. */
379 clock-frequency = <0>;
380 clock-output-names = "extal";
381 };
382
383 /* Special CPG clocks */
384 cpg_clocks: cpg_clocks@e6150000 {
385 compatible = "renesas,r8a7791-cpg-clocks",
386 "renesas,rcar-gen2-cpg-clocks";
387 reg = <0 0xe6150000 0 0x1000>;
388 clocks = <&extal_clk>;
389 #clock-cells = <1>;
390 clock-output-names = "main", "pll0", "pll1", "pll3",
391 "lb", "qspi", "sdh", "sd0", "z";
392 };
393
394 /* Variable factor clocks */
395 sd1_clk: sd2_clk@e6150078 {
396 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
397 reg = <0 0xe6150078 0 4>;
398 clocks = <&pll1_div2_clk>;
399 #clock-cells = <0>;
400 clock-output-names = "sd1";
401 };
402 sd2_clk: sd3_clk@e615007c {
403 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
404 reg = <0 0xe615007c 0 4>;
405 clocks = <&pll1_div2_clk>;
406 #clock-cells = <0>;
407 clock-output-names = "sd2";
408 };
409 mmc0_clk: mmc0_clk@e6150240 {
410 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
411 reg = <0 0xe6150240 0 4>;
412 clocks = <&pll1_div2_clk>;
413 #clock-cells = <0>;
414 clock-output-names = "mmc0";
415 };
416 ssp_clk: ssp_clk@e6150248 {
417 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
418 reg = <0 0xe6150248 0 4>;
419 clocks = <&pll1_div2_clk>;
420 #clock-cells = <0>;
421 clock-output-names = "ssp";
422 };
423 ssprs_clk: ssprs_clk@e615024c {
424 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
425 reg = <0 0xe615024c 0 4>;
426 clocks = <&pll1_div2_clk>;
427 #clock-cells = <0>;
428 clock-output-names = "ssprs";
429 };
430
431 /* Fixed factor clocks */
432 pll1_div2_clk: pll1_div2_clk {
433 compatible = "fixed-factor-clock";
434 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
435 #clock-cells = <0>;
436 clock-div = <2>;
437 clock-mult = <1>;
438 clock-output-names = "pll1_div2";
439 };
440 zg_clk: zg_clk {
441 compatible = "fixed-factor-clock";
442 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
443 #clock-cells = <0>;
444 clock-div = <3>;
445 clock-mult = <1>;
446 clock-output-names = "zg";
447 };
448 zx_clk: zx_clk {
449 compatible = "fixed-factor-clock";
450 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
451 #clock-cells = <0>;
452 clock-div = <3>;
453 clock-mult = <1>;
454 clock-output-names = "zx";
455 };
456 zs_clk: zs_clk {
457 compatible = "fixed-factor-clock";
458 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
459 #clock-cells = <0>;
460 clock-div = <6>;
461 clock-mult = <1>;
462 clock-output-names = "zs";
463 };
464 hp_clk: hp_clk {
465 compatible = "fixed-factor-clock";
466 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
467 #clock-cells = <0>;
468 clock-div = <12>;
469 clock-mult = <1>;
470 clock-output-names = "hp";
471 };
472 i_clk: i_clk {
473 compatible = "fixed-factor-clock";
474 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
475 #clock-cells = <0>;
476 clock-div = <2>;
477 clock-mult = <1>;
478 clock-output-names = "i";
479 };
480 b_clk: b_clk {
481 compatible = "fixed-factor-clock";
482 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
483 #clock-cells = <0>;
484 clock-div = <12>;
485 clock-mult = <1>;
486 clock-output-names = "b";
487 };
488 p_clk: p_clk {
489 compatible = "fixed-factor-clock";
490 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
491 #clock-cells = <0>;
492 clock-div = <24>;
493 clock-mult = <1>;
494 clock-output-names = "p";
495 };
496 cl_clk: cl_clk {
497 compatible = "fixed-factor-clock";
498 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
499 #clock-cells = <0>;
500 clock-div = <48>;
501 clock-mult = <1>;
502 clock-output-names = "cl";
503 };
504 m2_clk: m2_clk {
505 compatible = "fixed-factor-clock";
506 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
507 #clock-cells = <0>;
508 clock-div = <8>;
509 clock-mult = <1>;
510 clock-output-names = "m2";
511 };
512 imp_clk: imp_clk {
513 compatible = "fixed-factor-clock";
514 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
515 #clock-cells = <0>;
516 clock-div = <4>;
517 clock-mult = <1>;
518 clock-output-names = "imp";
519 };
520 rclk_clk: rclk_clk {
521 compatible = "fixed-factor-clock";
522 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
523 #clock-cells = <0>;
524 clock-div = <(48 * 1024)>;
525 clock-mult = <1>;
526 clock-output-names = "rclk";
527 };
528 oscclk_clk: oscclk_clk {
529 compatible = "fixed-factor-clock";
530 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
531 #clock-cells = <0>;
532 clock-div = <(12 * 1024)>;
533 clock-mult = <1>;
534 clock-output-names = "oscclk";
535 };
536 zb3_clk: zb3_clk {
537 compatible = "fixed-factor-clock";
538 clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
539 #clock-cells = <0>;
540 clock-div = <4>;
541 clock-mult = <1>;
542 clock-output-names = "zb3";
543 };
544 zb3d2_clk: zb3d2_clk {
545 compatible = "fixed-factor-clock";
546 clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
547 #clock-cells = <0>;
548 clock-div = <8>;
549 clock-mult = <1>;
550 clock-output-names = "zb3d2";
551 };
552 ddr_clk: ddr_clk {
553 compatible = "fixed-factor-clock";
554 clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
555 #clock-cells = <0>;
556 clock-div = <8>;
557 clock-mult = <1>;
558 clock-output-names = "ddr";
559 };
560 mp_clk: mp_clk {
561 compatible = "fixed-factor-clock";
562 clocks = <&pll1_div2_clk>;
563 #clock-cells = <0>;
564 clock-div = <15>;
565 clock-mult = <1>;
566 clock-output-names = "mp";
567 };
568 cp_clk: cp_clk {
569 compatible = "fixed-factor-clock";
570 clocks = <&extal_clk>;
571 #clock-cells = <0>;
572 clock-div = <2>;
573 clock-mult = <1>;
574 clock-output-names = "cp";
575 };
576
577 /* Gate clocks */
Laurent Pinchartcded80f2013-12-19 16:51:02 +0100578 mstp0_clks: mstp0_clks@e6150130 {
579 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
580 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
581 clocks = <&mp_clk>;
582 #clock-cells = <1>;
583 renesas,clock-indices = <R8A7791_CLK_MSIOF0>;
584 clock-output-names = "msiof0";
585 };
Laurent Pinchart59e79892013-12-11 15:05:16 +0100586 mstp1_clks: mstp1_clks@e6150134 {
587 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
588 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
589 clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
590 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
591 #clock-cells = <1>;
592 renesas,clock-indices = <
593 R8A7791_CLK_TMU1 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2
594 R8A7791_CLK_CMT0 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1
595 R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_SY
596 >;
597 clock-output-names =
598 "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
599 "vsp1-du0", "vsp1-sy";
600 };
601 mstp2_clks: mstp2_clks@e6150138 {
602 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
603 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
604 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
Laurent Pinchartcded80f2013-12-19 16:51:02 +0100605 <&mp_clk>, <&mp_clk>, <&mp_clk>;
Laurent Pinchart59e79892013-12-11 15:05:16 +0100606 #clock-cells = <1>;
607 renesas,clock-indices = <
608 R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0
Laurent Pinchartcded80f2013-12-19 16:51:02 +0100609 R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1
610 R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2
Laurent Pinchart59e79892013-12-11 15:05:16 +0100611 >;
612 clock-output-names =
Laurent Pinchartcded80f2013-12-19 16:51:02 +0100613 "scifa2", "scifa1", "scifa0", "misof2", "scifb0",
614 "scifb1", "msiof1", "scifb2";
Laurent Pinchart59e79892013-12-11 15:05:16 +0100615 };
616 mstp3_clks: mstp3_clks@e615013c {
617 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
618 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
619 clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>,
620 <&cpg_clocks R8A7791_CLK_SD0>, <&mmc0_clk>, <&rclk_clk>;
621 #clock-cells = <1>;
622 renesas,clock-indices = <
623 R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1
624 R8A7791_CLK_SDHI0 R8A7791_CLK_MMCIF0 R8A7791_CLK_CMT1
625 >;
626 clock-output-names =
627 "tpu0", "sdhi2", "sdhi1", "sdhi0", "mmcif0", "cmt1";
628 };
629 mstp5_clks: mstp5_clks@e6150144 {
630 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
631 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
632 clocks = <&extal_clk>, <&p_clk>;
633 #clock-cells = <1>;
634 renesas,clock-indices = <R8A7791_CLK_THERMAL R8A7791_CLK_PWM>;
635 clock-output-names = "thermal", "pwm";
636 };
637 mstp7_clks: mstp7_clks@e615014c {
638 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
639 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
640 clocks = <&mp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
641 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
642 <&zx_clk>, <&zx_clk>, <&zx_clk>;
643 #clock-cells = <1>;
644 renesas,clock-indices = <
645 R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5
646 R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0
647 R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1
648 R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0
649 R8A7791_CLK_LVDS0
650 >;
651 clock-output-names =
652 "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0",
653 "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0";
654 };
655 mstp8_clks: mstp8_clks@e6150990 {
656 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
657 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
Laurent Pinchart65f05c32014-01-07 09:22:56 +0100658 clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>, <&zs_clk>,
659 <&zs_clk>;
Laurent Pinchart59e79892013-12-11 15:05:16 +0100660 #clock-cells = <1>;
Laurent Pinchart09c98342014-01-07 09:22:54 +0100661 renesas,clock-indices = <
662 R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0
Laurent Pinchart65f05c32014-01-07 09:22:56 +0100663 R8A7791_CLK_ETHER R8A7791_CLK_SATA1 R8A7791_CLK_SATA0
Laurent Pinchart09c98342014-01-07 09:22:54 +0100664 >;
Laurent Pinchart65f05c32014-01-07 09:22:56 +0100665 clock-output-names =
666 "vin2", "vin1", "vin0", "ether", "sata1", "sata0";
Laurent Pinchart59e79892013-12-11 15:05:16 +0100667 };
668 mstp9_clks: mstp9_clks@e6150994 {
669 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
670 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
Laurent Pinchartec71f552013-12-19 16:51:04 +0100671 clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>,
672 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
673 <&p_clk>;
Laurent Pinchart59e79892013-12-11 15:05:16 +0100674 #clock-cells = <1>;
675 renesas,clock-indices = <
Laurent Pinchartec71f552013-12-19 16:51:04 +0100676 R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD
677 R8A7791_CLK_I2C4 R8A7791_CLK_I2C4 R8A7791_CLK_I2C3
678 R8A7791_CLK_I2C2 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0
Laurent Pinchart59e79892013-12-11 15:05:16 +0100679 >;
680 clock-output-names =
Laurent Pinchartec71f552013-12-19 16:51:04 +0100681 "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c4", "i2c3",
682 "i2c2", "i2c1", "i2c0";
Laurent Pinchart59e79892013-12-11 15:05:16 +0100683 };
684 mstp11_clks: mstp11_clks@e615099c {
685 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
686 reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
687 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
688 #clock-cells = <1>;
689 renesas,clock-indices = <
690 R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5
691 >;
692 clock-output-names = "scifa3", "scifa4", "scifa5";
693 };
694 };
Hisashi Nakamura0d0771ab2013-09-04 12:45:57 +0900695};