| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | #ifndef _ASM_SH_HD64465_ |
| 2 | #define _ASM_SH_HD64465_ 1 |
| 3 | /* |
| 4 | * $Id: hd64465.h,v 1.3 2003/05/04 19:30:15 lethal Exp $ |
| 5 | * |
| 6 | * Hitachi HD64465 companion chip support |
| 7 | * |
| 8 | * by Greg Banks <gbanks@pocketpenguins.com> |
| 9 | * (c) 2000 PocketPenguins Inc. |
| 10 | * |
| 11 | * Derived from <asm/hd64461.h> which bore the message: |
| 12 | * Copyright (C) 2000 YAEGASHI Takeshi |
| 13 | */ |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14 | #include <asm/io.h> |
| 15 | #include <asm/irq.h> |
| 16 | |
| 17 | /* |
| 18 | * Note that registers are defined here as virtual port numbers, |
| 19 | * which have no meaning except to get translated by hd64465_isa_port2addr() |
| 20 | * to an address in the range 0xb0000000-0xb3ffffff. Note that |
| 21 | * this translation happens to consist of adding the lower 16 bits |
| 22 | * of the virtual port number to 0xb0000000. Note also that the manual |
| 23 | * shows addresses as absolute physical addresses starting at 0x10000000, |
| 24 | * so e.g. the NIRR register is listed as 0x15000 here, 0x10005000 in the |
| 25 | * manual, and accessed using address 0xb0005000 - Greg. |
| 26 | */ |
| 27 | |
| 28 | /* System registers */ |
| 29 | #define HD64465_REG_SRR 0x1000c /* System Revision Register */ |
| 30 | #define HD64465_REG_SDID 0x10010 /* System Device ID Reg */ |
| 31 | #define HD64465_SDID 0x8122 /* 64465 device ID */ |
| 32 | |
| 33 | /* Power Management registers */ |
| 34 | #define HD64465_REG_SMSCR 0x10000 /* System Module Standby Control Reg */ |
| 35 | #define HD64465_SMSCR_PS2ST 0x4000 /* PS/2 Standby */ |
| 36 | #define HD64465_SMSCR_ADCST 0x1000 /* ADC Standby */ |
| 37 | #define HD64465_SMSCR_UARTST 0x0800 /* UART Standby */ |
| 38 | #define HD64465_SMSCR_SCDIST 0x0200 /* Serial Codec Standby */ |
| 39 | #define HD64465_SMSCR_PPST 0x0100 /* Parallel Port Standby */ |
| 40 | #define HD64465_SMSCR_PC0ST 0x0040 /* PCMCIA0 Standby */ |
| 41 | #define HD64465_SMSCR_PC1ST 0x0020 /* PCMCIA1 Standby */ |
| 42 | #define HD64465_SMSCR_AFEST 0x0010 /* AFE Standby */ |
| 43 | #define HD64465_SMSCR_TM0ST 0x0008 /* Timer0 Standby */ |
| 44 | #define HD64465_SMSCR_TM1ST 0x0004 /* Timer1 Standby */ |
| 45 | #define HD64465_SMSCR_IRDAST 0x0002 /* IRDA Standby */ |
| 46 | #define HD64465_SMSCR_KBCST 0x0001 /* Keyboard Controller Standby */ |
| 47 | |
| 48 | /* Interrupt Controller registers */ |
| 49 | #define HD64465_REG_NIRR 0x15000 /* Interrupt Request Register */ |
| 50 | #define HD64465_REG_NIMR 0x15002 /* Interrupt Mask Register */ |
| 51 | #define HD64465_REG_NITR 0x15004 /* Interrupt Trigger Mode Register */ |
| 52 | |
| 53 | /* Timer registers */ |
| 54 | #define HD64465_REG_TCVR1 0x16000 /* Timer 1 constant value register */ |
| 55 | #define HD64465_REG_TCVR0 0x16002 /* Timer 0 constant value register */ |
| 56 | #define HD64465_REG_TRVR1 0x16004 /* Timer 1 read value register */ |
| 57 | #define HD64465_REG_TRVR0 0x16006 /* Timer 0 read value register */ |
| 58 | #define HD64465_REG_TCR1 0x16008 /* Timer 1 control register */ |
| 59 | #define HD64465_REG_TCR0 0x1600A /* Timer 0 control register */ |
| 60 | #define HD64465_TCR_EADT 0x10 /* Enable ADTRIG# signal */ |
| 61 | #define HD64465_TCR_ETMO 0x08 /* Enable TMO signal */ |
| 62 | #define HD64465_TCR_PST_MASK 0x06 /* Clock Prescale */ |
| 63 | #define HD64465_TCR_PST_1 0x06 /* 1:1 */ |
| 64 | #define HD64465_TCR_PST_4 0x04 /* 1:4 */ |
| 65 | #define HD64465_TCR_PST_8 0x02 /* 1:8 */ |
| 66 | #define HD64465_TCR_PST_16 0x00 /* 1:16 */ |
| 67 | #define HD64465_TCR_TSTP 0x01 /* Start/Stop timer */ |
| 68 | #define HD64465_REG_TIRR 0x1600C /* Timer interrupt request register */ |
| 69 | #define HD64465_REG_TIDR 0x1600E /* Timer interrupt disable register */ |
| 70 | #define HD64465_REG_PWM1CS 0x16010 /* PWM 1 clock scale register */ |
| 71 | #define HD64465_REG_PWM1LPC 0x16012 /* PWM 1 low pulse width counter register */ |
| 72 | #define HD64465_REG_PWM1HPC 0x16014 /* PWM 1 high pulse width counter register */ |
| 73 | #define HD64465_REG_PWM0CS 0x16018 /* PWM 0 clock scale register */ |
| 74 | #define HD64465_REG_PWM0LPC 0x1601A /* PWM 0 low pulse width counter register */ |
| 75 | #define HD64465_REG_PWM0HPC 0x1601C /* PWM 0 high pulse width counter register */ |
| 76 | |
| 77 | /* Analog/Digital Converter registers */ |
| 78 | #define HD64465_REG_ADDRA 0x1E000 /* A/D data register A */ |
| 79 | #define HD64465_REG_ADDRB 0x1E002 /* A/D data register B */ |
| 80 | #define HD64465_REG_ADDRC 0x1E004 /* A/D data register C */ |
| 81 | #define HD64465_REG_ADDRD 0x1E006 /* A/D data register D */ |
| 82 | #define HD64465_REG_ADCSR 0x1E008 /* A/D control/status register */ |
| 83 | #define HD64465_ADCSR_ADF 0x80 /* A/D End Flag */ |
| 84 | #define HD64465_ADCSR_ADST 0x40 /* A/D Start Flag */ |
| 85 | #define HD64465_ADCSR_ADIS 0x20 /* A/D Interrupt Status */ |
| 86 | #define HD64465_ADCSR_TRGE 0x10 /* A/D Trigger Enable */ |
| 87 | #define HD64465_ADCSR_ADIE 0x08 /* A/D Interrupt Enable */ |
| 88 | #define HD64465_ADCSR_SCAN 0x04 /* A/D Scan Mode */ |
| 89 | #define HD64465_ADCSR_CH_MASK 0x03 /* A/D Channel */ |
| 90 | #define HD64465_REG_ADCALCR 0x1E00A /* A/D calibration sample control */ |
| 91 | #define HD64465_REG_ADCAL 0x1E00C /* A/D calibration data register */ |
| 92 | |
| 93 | |
| 94 | /* General Purpose I/O ports registers */ |
| 95 | #define HD64465_REG_GPACR 0x14000 /* Port A Control Register */ |
| 96 | #define HD64465_REG_GPBCR 0x14002 /* Port B Control Register */ |
| 97 | #define HD64465_REG_GPCCR 0x14004 /* Port C Control Register */ |
| 98 | #define HD64465_REG_GPDCR 0x14006 /* Port D Control Register */ |
| 99 | #define HD64465_REG_GPECR 0x14008 /* Port E Control Register */ |
| 100 | #define HD64465_REG_GPADR 0x14010 /* Port A Data Register */ |
| 101 | #define HD64465_REG_GPBDR 0x14012 /* Port B Data Register */ |
| 102 | #define HD64465_REG_GPCDR 0x14014 /* Port C Data Register */ |
| 103 | #define HD64465_REG_GPDDR 0x14016 /* Port D Data Register */ |
| 104 | #define HD64465_REG_GPEDR 0x14018 /* Port E Data Register */ |
| 105 | #define HD64465_REG_GPAICR 0x14020 /* Port A Interrupt Control Register */ |
| 106 | #define HD64465_REG_GPBICR 0x14022 /* Port B Interrupt Control Register */ |
| 107 | #define HD64465_REG_GPCICR 0x14024 /* Port C Interrupt Control Register */ |
| 108 | #define HD64465_REG_GPDICR 0x14026 /* Port D Interrupt Control Register */ |
| 109 | #define HD64465_REG_GPEICR 0x14028 /* Port E Interrupt Control Register */ |
| 110 | #define HD64465_REG_GPAISR 0x14040 /* Port A Interrupt Status Register */ |
| 111 | #define HD64465_REG_GPBISR 0x14042 /* Port B Interrupt Status Register */ |
| 112 | #define HD64465_REG_GPCISR 0x14044 /* Port C Interrupt Status Register */ |
| 113 | #define HD64465_REG_GPDISR 0x14046 /* Port D Interrupt Status Register */ |
| 114 | #define HD64465_REG_GPEISR 0x14048 /* Port E Interrupt Status Register */ |
| 115 | |
| 116 | /* PCMCIA bridge interface */ |
| 117 | #define HD64465_REG_PCC0ISR 0x12000 /* socket 0 interface status */ |
| 118 | #define HD64465_PCCISR_PREADY 0x80 /* mem card ready / io card IREQ */ |
| 119 | #define HD64465_PCCISR_PIREQ 0x80 |
| 120 | #define HD64465_PCCISR_PMWP 0x40 /* mem card write-protected */ |
| 121 | #define HD64465_PCCISR_PVS2 0x20 /* voltage select pin 2 */ |
| 122 | #define HD64465_PCCISR_PVS1 0x10 /* voltage select pin 1 */ |
| 123 | #define HD64465_PCCISR_PCD_MASK 0x0c /* card detect */ |
| 124 | #define HD64465_PCCISR_PBVD_MASK 0x03 /* battery voltage */ |
| 125 | #define HD64465_PCCISR_PBVD_BATGOOD 0x03 /* battery good */ |
| 126 | #define HD64465_PCCISR_PBVD_BATWARN 0x01 /* battery low warning */ |
| 127 | #define HD64465_PCCISR_PBVD_BATDEAD1 0x02 /* battery dead */ |
| 128 | #define HD64465_PCCISR_PBVD_BATDEAD2 0x00 /* battery dead */ |
| 129 | #define HD64465_REG_PCC0GCR 0x12002 /* socket 0 general control */ |
| 130 | #define HD64465_PCCGCR_PDRV 0x80 /* output drive */ |
| 131 | #define HD64465_PCCGCR_PCCR 0x40 /* PC card reset */ |
| 132 | #define HD64465_PCCGCR_PCCT 0x20 /* PC card type, 1=IO&mem, 0=mem */ |
| 133 | #define HD64465_PCCGCR_PVCC0 0x10 /* voltage control pin VCC0SEL0 */ |
| 134 | #define HD64465_PCCGCR_PMMOD 0x08 /* memory mode */ |
| 135 | #define HD64465_PCCGCR_PPA25 0x04 /* pin A25 */ |
| 136 | #define HD64465_PCCGCR_PPA24 0x02 /* pin A24 */ |
| 137 | #define HD64465_PCCGCR_PREG 0x01 /* ping PCC0REG# */ |
| 138 | #define HD64465_REG_PCC0CSCR 0x12004 /* socket 0 card status change */ |
| 139 | #define HD64465_PCCCSCR_PSCDI 0x80 /* sw card detect intr */ |
| 140 | #define HD64465_PCCCSCR_PSWSEL 0x40 /* power select */ |
| 141 | #define HD64465_PCCCSCR_PIREQ 0x20 /* IREQ intr req */ |
| 142 | #define HD64465_PCCCSCR_PSC 0x10 /* STSCHG (status change) pin */ |
| 143 | #define HD64465_PCCCSCR_PCDC 0x08 /* CD (card detect) change */ |
| 144 | #define HD64465_PCCCSCR_PRC 0x04 /* ready change */ |
| 145 | #define HD64465_PCCCSCR_PBW 0x02 /* battery warning change */ |
| 146 | #define HD64465_PCCCSCR_PBD 0x01 /* battery dead change */ |
| 147 | #define HD64465_REG_PCC0CSCIER 0x12006 /* socket 0 card status change interrupt enable */ |
| 148 | #define HD64465_PCCCSCIER_PCRE 0x80 /* change reset enable */ |
| 149 | #define HD64465_PCCCSCIER_PIREQE_MASK 0x60 /* IREQ enable */ |
| 150 | #define HD64465_PCCCSCIER_PIREQE_DISABLED 0x00 /* IREQ disabled */ |
| 151 | #define HD64465_PCCCSCIER_PIREQE_LEVEL 0x20 /* IREQ level-triggered */ |
| 152 | #define HD64465_PCCCSCIER_PIREQE_FALLING 0x40 /* IREQ falling-edge-trig */ |
| 153 | #define HD64465_PCCCSCIER_PIREQE_RISING 0x60 /* IREQ rising-edge-trig */ |
| 154 | #define HD64465_PCCCSCIER_PSCE 0x10 /* status change enable */ |
| 155 | #define HD64465_PCCCSCIER_PCDE 0x08 /* card detect change enable */ |
| 156 | #define HD64465_PCCCSCIER_PRE 0x04 /* ready change enable */ |
| 157 | #define HD64465_PCCCSCIER_PBWE 0x02 /* battery warn change enable */ |
| 158 | #define HD64465_PCCCSCIER_PBDE 0x01 /* battery dead change enable*/ |
| 159 | #define HD64465_REG_PCC0SCR 0x12008 /* socket 0 software control */ |
| 160 | #define HD64465_PCCSCR_SHDN 0x10 /* TPS2206 SHutDowN pin */ |
| 161 | #define HD64465_PCCSCR_SWP 0x01 /* write protect */ |
| 162 | #define HD64465_REG_PCCPSR 0x1200A /* serial power switch control */ |
| 163 | #define HD64465_REG_PCC1ISR 0x12010 /* socket 1 interface status */ |
| 164 | #define HD64465_REG_PCC1GCR 0x12012 /* socket 1 general control */ |
| 165 | #define HD64465_REG_PCC1CSCR 0x12014 /* socket 1 card status change */ |
| 166 | #define HD64465_REG_PCC1CSCIER 0x12016 /* socket 1 card status change interrupt enable */ |
| 167 | #define HD64465_REG_PCC1SCR 0x12018 /* socket 1 software control */ |
| 168 | |
| 169 | |
| 170 | /* PS/2 Keyboard and mouse controller -- *not* register compatible */ |
| 171 | #define HD64465_REG_KBCSR 0x1dc00 /* Keyboard Control/Status reg */ |
| 172 | #define HD64465_KBCSR_KBCIE 0x8000 /* KBCK Input Enable */ |
| 173 | #define HD64465_KBCSR_KBCOE 0x4000 /* KBCK Output Enable */ |
| 174 | #define HD64465_KBCSR_KBDOE 0x2000 /* KB DATA Output Enable */ |
| 175 | #define HD64465_KBCSR_KBCD 0x1000 /* KBCK Driven */ |
| 176 | #define HD64465_KBCSR_KBDD 0x0800 /* KB DATA Driven */ |
| 177 | #define HD64465_KBCSR_KBCS 0x0400 /* KBCK pin Status */ |
| 178 | #define HD64465_KBCSR_KBDS 0x0200 /* KB DATA pin Status */ |
| 179 | #define HD64465_KBCSR_KBDP 0x0100 /* KB DATA Parity bit */ |
| 180 | #define HD64465_KBCSR_KBD_MASK 0x00ff /* KD DATA shift reg */ |
| 181 | #define HD64465_REG_KBISR 0x1dc04 /* Keyboard Interrupt Status reg */ |
| 182 | #define HD64465_KBISR_KBRDF 0x0001 /* KB Received Data Full */ |
| 183 | #define HD64465_REG_MSCSR 0x1dc10 /* Mouse Control/Status reg */ |
| 184 | #define HD64465_REG_MSISR 0x1dc14 /* Mouse Interrupt Status reg */ |
| 185 | |
| 186 | |
| 187 | /* |
| 188 | * Logical address at which the HD64465 is mapped. Note that this |
| 189 | * should always be in the P2 segment (uncached and untranslated). |
| 190 | */ |
| 191 | #ifndef CONFIG_HD64465_IOBASE |
| 192 | #define CONFIG_HD64465_IOBASE 0xb0000000 |
| 193 | #endif |
| 194 | /* |
| 195 | * The HD64465 multiplexes all its modules' interrupts onto |
| 196 | * this single interrupt. |
| 197 | */ |
| 198 | #ifndef CONFIG_HD64465_IRQ |
| 199 | #define CONFIG_HD64465_IRQ 5 |
| 200 | #endif |
| 201 | |
| 202 | |
| 203 | #define _HD64465_IO_MASK 0xf8000000 |
| 204 | #define is_hd64465_addr(addr) \ |
| 205 | ((addr & _HD64465_IO_MASK) == (CONFIG_HD64465_IOBASE & _HD64465_IO_MASK)) |
| 206 | |
| 207 | /* |
| 208 | * A range of 16 virtual interrupts generated by |
| 209 | * demuxing the HD64465 muxed interrupt. |
| 210 | */ |
| 211 | #define HD64465_IRQ_BASE OFFCHIP_IRQ_BASE |
| 212 | #define HD64465_IRQ_NUM 16 |
| 213 | #define HD64465_IRQ_ADC (HD64465_IRQ_BASE+0) |
| 214 | #define HD64465_IRQ_USB (HD64465_IRQ_BASE+1) |
| 215 | #define HD64465_IRQ_SCDI (HD64465_IRQ_BASE+2) |
| 216 | #define HD64465_IRQ_PARALLEL (HD64465_IRQ_BASE+3) |
| 217 | /* bit 4 is reserved */ |
| 218 | #define HD64465_IRQ_UART (HD64465_IRQ_BASE+5) |
| 219 | #define HD64465_IRQ_IRDA (HD64465_IRQ_BASE+6) |
| 220 | #define HD64465_IRQ_PS2MOUSE (HD64465_IRQ_BASE+7) |
| 221 | #define HD64465_IRQ_KBC (HD64465_IRQ_BASE+8) |
| 222 | #define HD64465_IRQ_TIMER1 (HD64465_IRQ_BASE+9) |
| 223 | #define HD64465_IRQ_TIMER0 (HD64465_IRQ_BASE+10) |
| 224 | #define HD64465_IRQ_GPIO (HD64465_IRQ_BASE+11) |
| 225 | #define HD64465_IRQ_AFE (HD64465_IRQ_BASE+12) |
| 226 | #define HD64465_IRQ_PCMCIA1 (HD64465_IRQ_BASE+13) |
| 227 | #define HD64465_IRQ_PCMCIA0 (HD64465_IRQ_BASE+14) |
| 228 | #define HD64465_IRQ_PS2KBD (HD64465_IRQ_BASE+15) |
| 229 | |
| 230 | /* Constants for PCMCIA mappings */ |
| 231 | #define HD64465_PCC_WINDOW 0x01000000 |
| 232 | |
| 233 | #define HD64465_PCC0_BASE 0xb8000000 /* area 6 */ |
| 234 | #define HD64465_PCC0_ATTR (HD64465_PCC0_BASE) |
| 235 | #define HD64465_PCC0_COMM (HD64465_PCC0_BASE+HD64465_PCC_WINDOW) |
| 236 | #define HD64465_PCC0_IO (HD64465_PCC0_BASE+2*HD64465_PCC_WINDOW) |
| 237 | |
| 238 | #define HD64465_PCC1_BASE 0xb4000000 /* area 5 */ |
| 239 | #define HD64465_PCC1_ATTR (HD64465_PCC1_BASE) |
| 240 | #define HD64465_PCC1_COMM (HD64465_PCC1_BASE+HD64465_PCC_WINDOW) |
| 241 | #define HD64465_PCC1_IO (HD64465_PCC1_BASE+2*HD64465_PCC_WINDOW) |
| 242 | |
| 243 | /* |
| 244 | * Base of USB controller interface (as memory) |
| 245 | */ |
| 246 | #define HD64465_USB_BASE (CONFIG_HD64465_IOBASE+0xb000) |
| 247 | #define HD64465_USB_LEN 0x1000 |
| 248 | /* |
| 249 | * Base of embedded SRAM, used for USB controller. |
| 250 | */ |
| 251 | #define HD64465_SRAM_BASE (CONFIG_HD64465_IOBASE+0x9000) |
| 252 | #define HD64465_SRAM_LEN 0x1000 |
| 253 | |
| 254 | |
| 255 | |
| 256 | #endif /* _ASM_SH_HD64465_ */ |