Ben Dooks | c6184e2 | 2007-02-17 00:52:37 +0100 | [diff] [blame] | 1 | /* linux/arch/arm/mach-s3c2410/mach-qt2410.c |
| 2 | * |
| 3 | * Copyright (C) 2006 by OpenMoko, Inc. |
| 4 | * Author: Harald Welte <laforge@openmoko.org> |
| 5 | * All rights reserved. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; either version 2 of |
| 10 | * the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 20 | * MA 02111-1307 USA |
| 21 | * |
| 22 | */ |
| 23 | |
| 24 | #include <linux/kernel.h> |
| 25 | #include <linux/types.h> |
| 26 | #include <linux/interrupt.h> |
| 27 | #include <linux/list.h> |
| 28 | #include <linux/timer.h> |
| 29 | #include <linux/init.h> |
Ben Dooks | 333a42e | 2007-05-20 11:55:53 +0100 | [diff] [blame] | 30 | #include <linux/sysdev.h> |
Ben Dooks | c6184e2 | 2007-02-17 00:52:37 +0100 | [diff] [blame] | 31 | #include <linux/platform_device.h> |
| 32 | #include <linux/serial_core.h> |
Ben Dooks | c6184e2 | 2007-02-17 00:52:37 +0100 | [diff] [blame] | 33 | #include <linux/spi/spi.h> |
| 34 | #include <linux/spi/spi_bitbang.h> |
| 35 | |
| 36 | #include <linux/mtd/mtd.h> |
| 37 | #include <linux/mtd/nand.h> |
| 38 | #include <linux/mtd/nand_ecc.h> |
| 39 | #include <linux/mtd/partitions.h> |
| 40 | |
| 41 | #include <asm/mach/arch.h> |
| 42 | #include <asm/mach/map.h> |
| 43 | #include <asm/mach/irq.h> |
| 44 | |
| 45 | #include <asm/hardware.h> |
| 46 | #include <asm/io.h> |
| 47 | #include <asm/irq.h> |
| 48 | #include <asm/mach-types.h> |
| 49 | |
| 50 | #include <asm/arch/regs-gpio.h> |
| 51 | #include <asm/arch/leds-gpio.h> |
Ben Dooks | 531b617 | 2007-07-22 16:05:25 +0100 | [diff] [blame] | 52 | #include <asm/plat-s3c/regs-serial.h> |
Ben Dooks | c6184e2 | 2007-02-17 00:52:37 +0100 | [diff] [blame] | 53 | #include <asm/arch/fb.h> |
Ben Dooks | 531b617 | 2007-07-22 16:05:25 +0100 | [diff] [blame] | 54 | #include <asm/plat-s3c/nand.h> |
Ben Dooks | 06cfa55 | 2007-07-22 16:23:02 +0100 | [diff] [blame] | 55 | #include <asm/plat-s3c24xx/udc.h> |
Ben Dooks | c6184e2 | 2007-02-17 00:52:37 +0100 | [diff] [blame] | 56 | #include <asm/arch/spi.h> |
| 57 | #include <asm/arch/spi-gpio.h> |
| 58 | |
| 59 | #include <asm/plat-s3c24xx/common-smdk.h> |
| 60 | #include <asm/plat-s3c24xx/devs.h> |
| 61 | #include <asm/plat-s3c24xx/cpu.h> |
| 62 | #include <asm/plat-s3c24xx/pm.h> |
| 63 | |
| 64 | static struct map_desc qt2410_iodesc[] __initdata = { |
| 65 | { 0xe0000000, __phys_to_pfn(S3C2410_CS3+0x01000000), SZ_1M, MT_DEVICE } |
| 66 | }; |
| 67 | |
| 68 | #define UCON S3C2410_UCON_DEFAULT |
| 69 | #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB |
| 70 | #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE |
| 71 | |
| 72 | static struct s3c2410_uartcfg smdk2410_uartcfgs[] = { |
| 73 | [0] = { |
| 74 | .hwport = 0, |
| 75 | .flags = 0, |
| 76 | .ucon = UCON, |
| 77 | .ulcon = ULCON, |
| 78 | .ufcon = UFCON, |
| 79 | }, |
| 80 | [1] = { |
| 81 | .hwport = 1, |
| 82 | .flags = 0, |
| 83 | .ucon = UCON, |
| 84 | .ulcon = ULCON, |
| 85 | .ufcon = UFCON, |
| 86 | }, |
| 87 | [2] = { |
| 88 | .hwport = 2, |
| 89 | .flags = 0, |
| 90 | .ucon = UCON, |
| 91 | .ulcon = ULCON, |
| 92 | .ufcon = UFCON, |
| 93 | } |
| 94 | }; |
| 95 | |
| 96 | /* LCD driver info */ |
| 97 | |
Krzysztof Helt | 09fe75f | 2007-10-16 01:28:56 -0700 | [diff] [blame] | 98 | static struct s3c2410fb_display qt2410_lcd_cfg[] __initdata = { |
| 99 | { |
| 100 | /* Configuration for 640x480 SHARP LQ080V3DG01 */ |
Krzysztof Helt | f28ef57 | 2007-10-16 01:28:58 -0700 | [diff] [blame] | 101 | .lcdcon1 = S3C2410_LCDCON1_TFT16BPP | |
| 102 | S3C2410_LCDCON1_TFT | |
| 103 | S3C2410_LCDCON1_CLKVAL(0x01), /* HCLK/4 */ |
Ben Dooks | c6184e2 | 2007-02-17 00:52:37 +0100 | [diff] [blame] | 104 | |
Krzysztof Helt | f28ef57 | 2007-10-16 01:28:58 -0700 | [diff] [blame] | 105 | .lcdcon5 = S3C2410_LCDCON5_FRM565 | |
| 106 | S3C2410_LCDCON5_INVVLINE | |
| 107 | S3C2410_LCDCON5_INVVFRAME | |
| 108 | S3C2410_LCDCON5_PWREN | |
| 109 | S3C2410_LCDCON5_HWSWP, |
Krzysztof Helt | 09fe75f | 2007-10-16 01:28:56 -0700 | [diff] [blame] | 110 | |
Krzysztof Helt | 1f41153 | 2007-10-16 01:28:57 -0700 | [diff] [blame] | 111 | .type = S3C2410_LCDCON1_TFT, |
Krzysztof Helt | 09fe75f | 2007-10-16 01:28:56 -0700 | [diff] [blame] | 112 | .width = 640, |
| 113 | .height = 480, |
| 114 | |
Krzysztof Helt | 6981669 | 2007-10-16 01:29:06 -0700 | [diff] [blame^] | 115 | .pixclock = 40000, /* HCLK/4 */ |
Krzysztof Helt | 09fe75f | 2007-10-16 01:28:56 -0700 | [diff] [blame] | 116 | .xres = 640, |
| 117 | .yres = 480, |
| 118 | .bpp = 16, |
Krzysztof Helt | 1f41153 | 2007-10-16 01:28:57 -0700 | [diff] [blame] | 119 | .left_margin = 44, |
| 120 | .right_margin = 116, |
Krzysztof Helt | 93d11f5 | 2007-10-16 01:29:00 -0700 | [diff] [blame] | 121 | .hsync_len = 96, |
Krzysztof Helt | 5f20f69 | 2007-10-16 01:28:59 -0700 | [diff] [blame] | 122 | .upper_margin = 19, |
| 123 | .lower_margin = 11, |
Krzysztof Helt | 93d11f5 | 2007-10-16 01:29:00 -0700 | [diff] [blame] | 124 | .vsync_len = 15, |
Ben Dooks | c6184e2 | 2007-02-17 00:52:37 +0100 | [diff] [blame] | 125 | }, |
Krzysztof Helt | 09fe75f | 2007-10-16 01:28:56 -0700 | [diff] [blame] | 126 | { |
| 127 | /* Configuration for 480x640 toppoly TD028TTEC1 */ |
Krzysztof Helt | f28ef57 | 2007-10-16 01:28:58 -0700 | [diff] [blame] | 128 | .lcdcon1 = S3C2410_LCDCON1_TFT16BPP | |
| 129 | S3C2410_LCDCON1_TFT | |
| 130 | S3C2410_LCDCON1_CLKVAL(0x01), /* HCLK/4 */ |
Ben Dooks | c6184e2 | 2007-02-17 00:52:37 +0100 | [diff] [blame] | 131 | |
Krzysztof Helt | f28ef57 | 2007-10-16 01:28:58 -0700 | [diff] [blame] | 132 | .lcdcon5 = S3C2410_LCDCON5_FRM565 | |
| 133 | S3C2410_LCDCON5_INVVLINE | |
| 134 | S3C2410_LCDCON5_INVVFRAME | |
| 135 | S3C2410_LCDCON5_PWREN | |
| 136 | S3C2410_LCDCON5_HWSWP, |
Krzysztof Helt | 09fe75f | 2007-10-16 01:28:56 -0700 | [diff] [blame] | 137 | |
Krzysztof Helt | 1f41153 | 2007-10-16 01:28:57 -0700 | [diff] [blame] | 138 | .type = S3C2410_LCDCON1_TFT, |
Krzysztof Helt | 09fe75f | 2007-10-16 01:28:56 -0700 | [diff] [blame] | 139 | .width = 480, |
| 140 | .height = 640, |
Krzysztof Helt | 6981669 | 2007-10-16 01:29:06 -0700 | [diff] [blame^] | 141 | .pixclock = 40000, /* HCLK/4 */ |
Krzysztof Helt | 09fe75f | 2007-10-16 01:28:56 -0700 | [diff] [blame] | 142 | .xres = 480, |
| 143 | .yres = 640, |
| 144 | .bpp = 16, |
Krzysztof Helt | 1f41153 | 2007-10-16 01:28:57 -0700 | [diff] [blame] | 145 | .left_margin = 8, |
| 146 | .right_margin = 24, |
Krzysztof Helt | 93d11f5 | 2007-10-16 01:29:00 -0700 | [diff] [blame] | 147 | .hsync_len = 8, |
Krzysztof Helt | 5f20f69 | 2007-10-16 01:28:59 -0700 | [diff] [blame] | 148 | .upper_margin = 2, |
| 149 | .lower_margin = 4, |
Krzysztof Helt | 93d11f5 | 2007-10-16 01:29:00 -0700 | [diff] [blame] | 150 | .vsync_len = 2, |
Ben Dooks | c6184e2 | 2007-02-17 00:52:37 +0100 | [diff] [blame] | 151 | }, |
Krzysztof Helt | 09fe75f | 2007-10-16 01:28:56 -0700 | [diff] [blame] | 152 | { |
| 153 | /* Config for 240x320 LCD */ |
Krzysztof Helt | f28ef57 | 2007-10-16 01:28:58 -0700 | [diff] [blame] | 154 | .lcdcon1 = S3C2410_LCDCON1_TFT16BPP | |
| 155 | S3C2410_LCDCON1_TFT | |
| 156 | S3C2410_LCDCON1_CLKVAL(0x04), |
Ben Dooks | c6184e2 | 2007-02-17 00:52:37 +0100 | [diff] [blame] | 157 | |
Krzysztof Helt | f28ef57 | 2007-10-16 01:28:58 -0700 | [diff] [blame] | 158 | .lcdcon5 = S3C2410_LCDCON5_FRM565 | |
| 159 | S3C2410_LCDCON5_INVVLINE | |
| 160 | S3C2410_LCDCON5_INVVFRAME | |
| 161 | S3C2410_LCDCON5_PWREN | |
| 162 | S3C2410_LCDCON5_HWSWP, |
Krzysztof Helt | 09fe75f | 2007-10-16 01:28:56 -0700 | [diff] [blame] | 163 | |
Krzysztof Helt | 1f41153 | 2007-10-16 01:28:57 -0700 | [diff] [blame] | 164 | .type = S3C2410_LCDCON1_TFT, |
Krzysztof Helt | 09fe75f | 2007-10-16 01:28:56 -0700 | [diff] [blame] | 165 | .width = 240, |
| 166 | .height = 320, |
Krzysztof Helt | 6981669 | 2007-10-16 01:29:06 -0700 | [diff] [blame^] | 167 | .pixclock = 100000, /* HCLK/10 */ |
Krzysztof Helt | 09fe75f | 2007-10-16 01:28:56 -0700 | [diff] [blame] | 168 | .xres = 240, |
| 169 | .yres = 320, |
| 170 | .bpp = 16, |
Krzysztof Helt | 1f41153 | 2007-10-16 01:28:57 -0700 | [diff] [blame] | 171 | .left_margin = 13, |
| 172 | .right_margin = 8, |
Krzysztof Helt | 93d11f5 | 2007-10-16 01:29:00 -0700 | [diff] [blame] | 173 | .hsync_len = 4, |
Krzysztof Helt | 5f20f69 | 2007-10-16 01:28:59 -0700 | [diff] [blame] | 174 | .upper_margin = 2, |
| 175 | .lower_margin = 7, |
Krzysztof Helt | 93d11f5 | 2007-10-16 01:29:00 -0700 | [diff] [blame] | 176 | .vsync_len = 4, |
Ben Dooks | c6184e2 | 2007-02-17 00:52:37 +0100 | [diff] [blame] | 177 | }, |
| 178 | }; |
| 179 | |
Ben Dooks | c6184e2 | 2007-02-17 00:52:37 +0100 | [diff] [blame] | 180 | |
Krzysztof Helt | 09fe75f | 2007-10-16 01:28:56 -0700 | [diff] [blame] | 181 | static struct s3c2410fb_mach_info qt2410_fb_info __initdata = { |
| 182 | .displays = qt2410_lcd_cfg, |
| 183 | .num_displays = ARRAY_SIZE(qt2410_lcd_cfg), |
| 184 | .default_display = 0, |
Ben Dooks | c6184e2 | 2007-02-17 00:52:37 +0100 | [diff] [blame] | 185 | |
| 186 | .lpcsel = ((0xCE6) & ~7) | 1<<4, |
Ben Dooks | c6184e2 | 2007-02-17 00:52:37 +0100 | [diff] [blame] | 187 | }; |
| 188 | |
| 189 | /* CS8900 */ |
| 190 | |
| 191 | static struct resource qt2410_cs89x0_resources[] = { |
| 192 | [0] = { |
| 193 | .start = 0x19000000, |
| 194 | .end = 0x19000000 + 16, |
| 195 | .flags = IORESOURCE_MEM, |
| 196 | }, |
| 197 | [1] = { |
| 198 | .start = IRQ_EINT9, |
| 199 | .end = IRQ_EINT9, |
| 200 | .flags = IORESOURCE_IRQ, |
| 201 | }, |
| 202 | }; |
| 203 | |
| 204 | static struct platform_device qt2410_cs89x0 = { |
| 205 | .name = "cirrus-cs89x0", |
| 206 | .num_resources = ARRAY_SIZE(qt2410_cs89x0_resources), |
| 207 | .resource = qt2410_cs89x0_resources, |
| 208 | }; |
| 209 | |
| 210 | /* LED */ |
| 211 | |
| 212 | static struct s3c24xx_led_platdata qt2410_pdata_led = { |
| 213 | .gpio = S3C2410_GPB0, |
| 214 | .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, |
| 215 | .name = "led", |
| 216 | .def_trigger = "timer", |
| 217 | }; |
| 218 | |
| 219 | static struct platform_device qt2410_led = { |
| 220 | .name = "s3c24xx_led", |
| 221 | .id = 0, |
| 222 | .dev = { |
| 223 | .platform_data = &qt2410_pdata_led, |
| 224 | }, |
| 225 | }; |
| 226 | |
| 227 | /* SPI */ |
| 228 | |
| 229 | static void spi_gpio_cs(struct s3c2410_spigpio_info *spi, int cs) |
| 230 | { |
| 231 | switch (cs) { |
| 232 | case BITBANG_CS_ACTIVE: |
| 233 | s3c2410_gpio_setpin(S3C2410_GPB5, 0); |
| 234 | break; |
| 235 | case BITBANG_CS_INACTIVE: |
| 236 | s3c2410_gpio_setpin(S3C2410_GPB5, 1); |
| 237 | break; |
| 238 | } |
| 239 | } |
| 240 | |
| 241 | static struct s3c2410_spigpio_info spi_gpio_cfg = { |
| 242 | .pin_clk = S3C2410_GPG7, |
| 243 | .pin_mosi = S3C2410_GPG6, |
| 244 | .pin_miso = S3C2410_GPG5, |
| 245 | .chip_select = &spi_gpio_cs, |
| 246 | }; |
| 247 | |
| 248 | |
| 249 | static struct platform_device qt2410_spi = { |
| 250 | .name = "s3c24xx-spi-gpio", |
| 251 | .id = 1, |
| 252 | .dev = { |
| 253 | .platform_data = &spi_gpio_cfg, |
| 254 | }, |
| 255 | }; |
| 256 | |
| 257 | /* Board devices */ |
| 258 | |
| 259 | static struct platform_device *qt2410_devices[] __initdata = { |
| 260 | &s3c_device_usb, |
| 261 | &s3c_device_lcd, |
| 262 | &s3c_device_wdt, |
| 263 | &s3c_device_i2c, |
| 264 | &s3c_device_iis, |
| 265 | &s3c_device_sdi, |
| 266 | &s3c_device_usbgadget, |
| 267 | &qt2410_spi, |
| 268 | &qt2410_cs89x0, |
| 269 | &qt2410_led, |
| 270 | }; |
| 271 | |
Ben Dooks | c6184e2 | 2007-02-17 00:52:37 +0100 | [diff] [blame] | 272 | static struct mtd_partition qt2410_nand_part[] = { |
| 273 | [0] = { |
| 274 | .name = "U-Boot", |
| 275 | .size = 0x30000, |
| 276 | .offset = 0, |
| 277 | }, |
| 278 | [1] = { |
| 279 | .name = "U-Boot environment", |
| 280 | .offset = 0x30000, |
| 281 | .size = 0x4000, |
| 282 | }, |
| 283 | [2] = { |
| 284 | .name = "kernel", |
| 285 | .offset = 0x34000, |
| 286 | .size = SZ_2M, |
| 287 | }, |
| 288 | [3] = { |
| 289 | .name = "initrd", |
| 290 | .offset = 0x234000, |
| 291 | .size = SZ_4M, |
| 292 | }, |
| 293 | [4] = { |
| 294 | .name = "jffs2", |
| 295 | .offset = 0x634000, |
| 296 | .size = 0x39cc000, |
| 297 | }, |
| 298 | }; |
| 299 | |
| 300 | static struct s3c2410_nand_set qt2410_nand_sets[] = { |
| 301 | [0] = { |
| 302 | .name = "NAND", |
| 303 | .nr_chips = 1, |
| 304 | .nr_partitions = ARRAY_SIZE(qt2410_nand_part), |
| 305 | .partitions = qt2410_nand_part, |
| 306 | }, |
| 307 | }; |
| 308 | |
| 309 | /* choose a set of timings which should suit most 512Mbit |
| 310 | * chips and beyond. |
| 311 | */ |
| 312 | |
| 313 | static struct s3c2410_platform_nand qt2410_nand_info = { |
| 314 | .tacls = 20, |
| 315 | .twrph0 = 60, |
| 316 | .twrph1 = 20, |
| 317 | .nr_sets = ARRAY_SIZE(qt2410_nand_sets), |
| 318 | .sets = qt2410_nand_sets, |
| 319 | }; |
| 320 | |
| 321 | /* UDC */ |
| 322 | |
| 323 | static struct s3c2410_udc_mach_info qt2410_udc_cfg = { |
| 324 | }; |
| 325 | |
| 326 | static char tft_type = 's'; |
| 327 | |
| 328 | static int __init qt2410_tft_setup(char *str) |
| 329 | { |
| 330 | tft_type = str[0]; |
| 331 | return 1; |
| 332 | } |
| 333 | |
| 334 | __setup("tft=", qt2410_tft_setup); |
| 335 | |
| 336 | static void __init qt2410_map_io(void) |
| 337 | { |
| 338 | s3c24xx_init_io(qt2410_iodesc, ARRAY_SIZE(qt2410_iodesc)); |
| 339 | s3c24xx_init_clocks(12*1000*1000); |
| 340 | s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs)); |
Ben Dooks | c6184e2 | 2007-02-17 00:52:37 +0100 | [diff] [blame] | 341 | } |
| 342 | |
| 343 | static void __init qt2410_machine_init(void) |
| 344 | { |
| 345 | s3c_device_nand.dev.platform_data = &qt2410_nand_info; |
| 346 | |
| 347 | switch (tft_type) { |
| 348 | case 'p': /* production */ |
Krzysztof Helt | 09fe75f | 2007-10-16 01:28:56 -0700 | [diff] [blame] | 349 | qt2410_fb_info.default_display = 1; |
Ben Dooks | c6184e2 | 2007-02-17 00:52:37 +0100 | [diff] [blame] | 350 | break; |
| 351 | case 'b': /* big */ |
Krzysztof Helt | 09fe75f | 2007-10-16 01:28:56 -0700 | [diff] [blame] | 352 | qt2410_fb_info.default_display = 0; |
Ben Dooks | c6184e2 | 2007-02-17 00:52:37 +0100 | [diff] [blame] | 353 | break; |
| 354 | case 's': /* small */ |
| 355 | default: |
Krzysztof Helt | 09fe75f | 2007-10-16 01:28:56 -0700 | [diff] [blame] | 356 | qt2410_fb_info.default_display = 2; |
Ben Dooks | c6184e2 | 2007-02-17 00:52:37 +0100 | [diff] [blame] | 357 | break; |
| 358 | } |
Krzysztof Helt | 09fe75f | 2007-10-16 01:28:56 -0700 | [diff] [blame] | 359 | s3c24xx_fb_set_platdata(&qt2410_fb_info); |
Ben Dooks | c6184e2 | 2007-02-17 00:52:37 +0100 | [diff] [blame] | 360 | |
| 361 | s3c2410_gpio_cfgpin(S3C2410_GPB0, S3C2410_GPIO_OUTPUT); |
| 362 | s3c2410_gpio_setpin(S3C2410_GPB0, 1); |
| 363 | |
| 364 | s3c24xx_udc_set_platdata(&qt2410_udc_cfg); |
| 365 | |
| 366 | s3c2410_gpio_cfgpin(S3C2410_GPB5, S3C2410_GPIO_OUTPUT); |
| 367 | |
Ben Dooks | 57e5171 | 2007-04-20 11:19:16 +0100 | [diff] [blame] | 368 | platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices)); |
Ben Dooks | c6184e2 | 2007-02-17 00:52:37 +0100 | [diff] [blame] | 369 | s3c2410_pm_init(); |
| 370 | } |
| 371 | |
| 372 | MACHINE_START(QT2410, "QT2410") |
| 373 | .phys_io = S3C2410_PA_UART, |
| 374 | .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, |
| 375 | .boot_params = S3C2410_SDRAM_PA + 0x100, |
| 376 | .map_io = qt2410_map_io, |
| 377 | .init_irq = s3c24xx_init_irq, |
| 378 | .init_machine = qt2410_machine_init, |
| 379 | .timer = &s3c24xx_timer, |
| 380 | MACHINE_END |
| 381 | |
| 382 | |