blob: ede908bca7d5fdf33c6364c3433b2ece785d249b [file] [log] [blame]
Shawn Guo69c31b72011-09-06 14:59:40 +08001/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#include <linux/linkage.h>
14#include <linux/init.h>
15#include <asm/hardware/cache-l2x0.h>
16
17 .section ".text.head", "ax"
18 __CPUINIT
19
20/*
21 * The secondary kernel init calls v7_flush_dcache_all before it enables
22 * the L1; however, the L1 comes out of reset in an undefined state, so
23 * the clean + invalidate performed by v7_flush_dcache_all causes a bunch
24 * of cache lines with uninitialized data and uninitialized tags to get
25 * written out to memory, which does really unpleasant things to the main
26 * processor. We fix this by performing an invalidate, rather than a
27 * clean + invalidate, before jumping into the kernel.
28 *
29 * This funciton is cloned from arch/arm/mach-tegra/headsmp.S, and needs
30 * to be called for both secondary cores startup and primary core resume
31 * procedures. Ideally, it should be moved into arch/arm/mm/cache-v7.S.
32 */
33ENTRY(v7_invalidate_l1)
34 mov r0, #0
35 mcr p15, 2, r0, c0, c0, 0
36 mrc p15, 1, r0, c0, c0, 0
37
38 ldr r1, =0x7fff
39 and r2, r1, r0, lsr #13
40
41 ldr r1, =0x3ff
42
43 and r3, r1, r0, lsr #3 @ NumWays - 1
44 add r2, r2, #1 @ NumSets
45
46 and r0, r0, #0x7
47 add r0, r0, #4 @ SetShift
48
49 clz r1, r3 @ WayShift
50 add r4, r3, #1 @ NumWays
511: sub r2, r2, #1 @ NumSets--
52 mov r3, r4 @ Temp = NumWays
532: subs r3, r3, #1 @ Temp--
54 mov r5, r3, lsl r1
55 mov r6, r2, lsl r0
56 orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
57 mcr p15, 0, r5, c7, c6, 2
58 bgt 2b
59 cmp r2, #0
60 bgt 1b
61 dsb
62 isb
63 mov pc, lr
64ENDPROC(v7_invalidate_l1)
65
66#ifdef CONFIG_SMP
67ENTRY(v7_secondary_startup)
68 bl v7_invalidate_l1
69 b secondary_startup
70ENDPROC(v7_secondary_startup)
71#endif