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Sunil Goutham4863dea2015-05-26 19:20:15 -07001/*
2 * Copyright (C) 2015 Cavium, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
7 */
8
9#ifndef NIC_H
10#define NIC_H
11
12#include <linux/netdevice.h>
13#include <linux/interrupt.h>
Robert Richterd768b672015-06-02 11:00:18 -070014#include <linux/pci.h>
Sunil Goutham4863dea2015-05-26 19:20:15 -070015#include "thunder_bgx.h"
16
17/* PCI device IDs */
18#define PCI_DEVICE_ID_THUNDER_NIC_PF 0xA01E
19#define PCI_DEVICE_ID_THUNDER_PASS1_NIC_VF 0x0011
20#define PCI_DEVICE_ID_THUNDER_NIC_VF 0xA034
21#define PCI_DEVICE_ID_THUNDER_BGX 0xA026
22
23/* PCI BAR nos */
24#define PCI_CFG_REG_BAR_NUM 0
25#define PCI_MSIX_REG_BAR_NUM 4
26
27/* NIC SRIOV VF count */
28#define MAX_NUM_VFS_SUPPORTED 128
29#define DEFAULT_NUM_VF_ENABLED 8
30
31#define NIC_TNS_BYPASS_MODE 0
32#define NIC_TNS_MODE 1
33
34/* NIC priv flags */
35#define NIC_SRIOV_ENABLED BIT(0)
36
37/* Min/Max packet size */
38#define NIC_HW_MIN_FRS 64
39#define NIC_HW_MAX_FRS 9200 /* 9216 max packet including FCS */
40
41/* Max pkinds */
42#define NIC_MAX_PKIND 16
43
44/* Rx Channels */
45/* Receive channel configuration in TNS bypass mode
46 * Below is configuration in TNS bypass mode
47 * BGX0-LMAC0-CHAN0 - VNIC CHAN0
48 * BGX0-LMAC1-CHAN0 - VNIC CHAN16
49 * ...
50 * BGX1-LMAC0-CHAN0 - VNIC CHAN128
51 * ...
52 * BGX1-LMAC3-CHAN0 - VNIC CHAN174
53 */
54#define NIC_INTF_COUNT 2 /* Interfaces btw VNIC and TNS/BGX */
55#define NIC_CHANS_PER_INF 128
56#define NIC_MAX_CHANS (NIC_INTF_COUNT * NIC_CHANS_PER_INF)
57#define NIC_CPI_COUNT 2048 /* No of channel parse indices */
58
59/* TNS bypass mode: 1-1 mapping between VNIC and BGX:LMAC */
60#define NIC_MAX_BGX MAX_BGX_PER_CN88XX
61#define NIC_CPI_PER_BGX (NIC_CPI_COUNT / NIC_MAX_BGX)
62#define NIC_MAX_CPI_PER_LMAC 64 /* Max when CPI_ALG is IP diffserv */
63#define NIC_RSSI_PER_BGX (NIC_RSSI_COUNT / NIC_MAX_BGX)
64
65/* Tx scheduling */
66#define NIC_MAX_TL4 1024
67#define NIC_MAX_TL4_SHAPERS 256 /* 1 shaper for 4 TL4s */
68#define NIC_MAX_TL3 256
69#define NIC_MAX_TL3_SHAPERS 64 /* 1 shaper for 4 TL3s */
70#define NIC_MAX_TL2 64
71#define NIC_MAX_TL2_SHAPERS 2 /* 1 shaper for 32 TL2s */
72#define NIC_MAX_TL1 2
73
74/* TNS bypass mode */
75#define NIC_TL2_PER_BGX 32
76#define NIC_TL4_PER_BGX (NIC_MAX_TL4 / NIC_MAX_BGX)
77#define NIC_TL4_PER_LMAC (NIC_MAX_TL4 / NIC_CHANS_PER_INF)
78
79/* NIC VF Interrupts */
80#define NICVF_INTR_CQ 0
81#define NICVF_INTR_SQ 1
82#define NICVF_INTR_RBDR 2
83#define NICVF_INTR_PKT_DROP 3
84#define NICVF_INTR_TCP_TIMER 4
85#define NICVF_INTR_MBOX 5
86#define NICVF_INTR_QS_ERR 6
87
88#define NICVF_INTR_CQ_SHIFT 0
89#define NICVF_INTR_SQ_SHIFT 8
90#define NICVF_INTR_RBDR_SHIFT 16
91#define NICVF_INTR_PKT_DROP_SHIFT 20
92#define NICVF_INTR_TCP_TIMER_SHIFT 21
93#define NICVF_INTR_MBOX_SHIFT 22
94#define NICVF_INTR_QS_ERR_SHIFT 23
95
96#define NICVF_INTR_CQ_MASK (0xFF << NICVF_INTR_CQ_SHIFT)
97#define NICVF_INTR_SQ_MASK (0xFF << NICVF_INTR_SQ_SHIFT)
98#define NICVF_INTR_RBDR_MASK (0x03 << NICVF_INTR_RBDR_SHIFT)
99#define NICVF_INTR_PKT_DROP_MASK BIT(NICVF_INTR_PKT_DROP_SHIFT)
100#define NICVF_INTR_TCP_TIMER_MASK BIT(NICVF_INTR_TCP_TIMER_SHIFT)
101#define NICVF_INTR_MBOX_MASK BIT(NICVF_INTR_MBOX_SHIFT)
102#define NICVF_INTR_QS_ERR_MASK BIT(NICVF_INTR_QS_ERR_SHIFT)
103
104/* MSI-X interrupts */
105#define NIC_PF_MSIX_VECTORS 10
106#define NIC_VF_MSIX_VECTORS 20
107
108#define NIC_PF_INTR_ID_ECC0_SBE 0
109#define NIC_PF_INTR_ID_ECC0_DBE 1
110#define NIC_PF_INTR_ID_ECC1_SBE 2
111#define NIC_PF_INTR_ID_ECC1_DBE 3
112#define NIC_PF_INTR_ID_ECC2_SBE 4
113#define NIC_PF_INTR_ID_ECC2_DBE 5
114#define NIC_PF_INTR_ID_ECC3_SBE 6
115#define NIC_PF_INTR_ID_ECC3_DBE 7
116#define NIC_PF_INTR_ID_MBOX0 8
117#define NIC_PF_INTR_ID_MBOX1 9
118
Sunil Goutham4c0b6eaf2016-02-24 16:40:50 +0530119/* Minimum FIFO level before all packets for the CQ are dropped
120 *
121 * This value ensures that once a packet has been "accepted"
122 * for reception it will not get dropped due to non-availability
123 * of CQ descriptor. An errata in HW mandates this value to be
124 * atleast 0x100.
125 */
126#define NICPF_CQM_MIN_DROP_LEVEL 0x100
127
Sunil Goutham4863dea2015-05-26 19:20:15 -0700128/* Global timer for CQ timer thresh interrupts
129 * Calculated for SCLK of 700Mhz
130 * value written should be a 1/16th of what is expected
131 *
Sunil Goutham006394a2015-12-02 15:36:15 +0530132 * 1 tick per 0.025usec
Sunil Goutham4863dea2015-05-26 19:20:15 -0700133 */
Sunil Goutham006394a2015-12-02 15:36:15 +0530134#define NICPF_CLK_PER_INT_TICK 1
Sunil Goutham4863dea2015-05-26 19:20:15 -0700135
Sunil Goutham3d7a8aa2015-07-29 16:49:43 +0300136/* Time to wait before we decide that a SQ is stuck.
137 *
138 * Since both pkt rx and tx notifications are done with same CQ,
139 * when packets are being received at very high rate (eg: L2 forwarding)
140 * then freeing transmitted skbs will be delayed and watchdog
141 * will kick in, resetting interface. Hence keeping this value high.
142 */
143#define NICVF_TX_TIMEOUT (50 * HZ)
144
Sunil Goutham4863dea2015-05-26 19:20:15 -0700145struct nicvf_cq_poll {
Sunil Goutham39ad6ee2015-08-30 12:29:14 +0300146 struct nicvf *nicvf;
Sunil Goutham4863dea2015-05-26 19:20:15 -0700147 u8 cq_idx; /* Completion queue index */
148 struct napi_struct napi;
149};
150
151#define NIC_RSSI_COUNT 4096 /* Total no of RSS indices */
152#define NIC_MAX_RSS_HASH_BITS 8
153#define NIC_MAX_RSS_IDR_TBL_SIZE (1 << NIC_MAX_RSS_HASH_BITS)
154#define RSS_HASH_KEY_SIZE 5 /* 320 bit key */
155
156struct nicvf_rss_info {
157 bool enable;
158#define RSS_L2_EXTENDED_HASH_ENA BIT(0)
159#define RSS_IP_HASH_ENA BIT(1)
160#define RSS_TCP_HASH_ENA BIT(2)
161#define RSS_TCP_SYN_DIS BIT(3)
162#define RSS_UDP_HASH_ENA BIT(4)
163#define RSS_L4_EXTENDED_HASH_ENA BIT(5)
164#define RSS_ROCE_ENA BIT(6)
165#define RSS_L3_BI_DIRECTION_ENA BIT(7)
166#define RSS_L4_BI_DIRECTION_ENA BIT(8)
167 u64 cfg;
168 u8 hash_bits;
169 u16 rss_size;
170 u8 ind_tbl[NIC_MAX_RSS_IDR_TBL_SIZE];
171 u64 key[RSS_HASH_KEY_SIZE];
172} ____cacheline_aligned_in_smp;
173
174enum rx_stats_reg_offset {
175 RX_OCTS = 0x0,
176 RX_UCAST = 0x1,
177 RX_BCAST = 0x2,
178 RX_MCAST = 0x3,
179 RX_RED = 0x4,
180 RX_RED_OCTS = 0x5,
181 RX_ORUN = 0x6,
182 RX_ORUN_OCTS = 0x7,
183 RX_FCS = 0x8,
184 RX_L2ERR = 0x9,
185 RX_DRP_BCAST = 0xa,
186 RX_DRP_MCAST = 0xb,
187 RX_DRP_L3BCAST = 0xc,
188 RX_DRP_L3MCAST = 0xd,
189 RX_STATS_ENUM_LAST,
190};
191
192enum tx_stats_reg_offset {
193 TX_OCTS = 0x0,
194 TX_UCAST = 0x1,
195 TX_BCAST = 0x2,
196 TX_MCAST = 0x3,
197 TX_DROP = 0x4,
198 TX_STATS_ENUM_LAST,
199};
200
201struct nicvf_hw_stats {
Sunil Gouthama2dc5de2015-08-30 12:29:10 +0300202 u64 rx_bytes;
203 u64 rx_ucast_frames;
204 u64 rx_bcast_frames;
205 u64 rx_mcast_frames;
Sunil Goutham4863dea2015-05-26 19:20:15 -0700206 u64 rx_fcs_errors;
207 u64 rx_l2_errors;
208 u64 rx_drop_red;
209 u64 rx_drop_red_bytes;
210 u64 rx_drop_overrun;
211 u64 rx_drop_overrun_bytes;
212 u64 rx_drop_bcast;
213 u64 rx_drop_mcast;
214 u64 rx_drop_l3_bcast;
215 u64 rx_drop_l3_mcast;
Sunil Gouthama2dc5de2015-08-30 12:29:10 +0300216 u64 rx_bgx_truncated_pkts;
217 u64 rx_jabber_errs;
218 u64 rx_fcs_errs;
219 u64 rx_bgx_errs;
220 u64 rx_prel2_errs;
221 u64 rx_l2_hdr_malformed;
222 u64 rx_oversize;
223 u64 rx_undersize;
224 u64 rx_l2_len_mismatch;
225 u64 rx_l2_pclp;
226 u64 rx_ip_ver_errs;
227 u64 rx_ip_csum_errs;
228 u64 rx_ip_hdr_malformed;
229 u64 rx_ip_payload_malformed;
230 u64 rx_ip_ttl_errs;
231 u64 rx_l3_pclp;
232 u64 rx_l4_malformed;
233 u64 rx_l4_csum_errs;
234 u64 rx_udp_len_errs;
235 u64 rx_l4_port_errs;
236 u64 rx_tcp_flag_errs;
237 u64 rx_tcp_offset_errs;
238 u64 rx_l4_pclp;
239 u64 rx_truncated_pkts;
240
Sunil Goutham4863dea2015-05-26 19:20:15 -0700241 u64 tx_bytes_ok;
242 u64 tx_ucast_frames_ok;
243 u64 tx_bcast_frames_ok;
244 u64 tx_mcast_frames_ok;
245 u64 tx_drops;
246};
247
248struct nicvf_drv_stats {
249 /* Rx */
250 u64 rx_frames_ok;
251 u64 rx_frames_64;
252 u64 rx_frames_127;
253 u64 rx_frames_255;
254 u64 rx_frames_511;
255 u64 rx_frames_1023;
256 u64 rx_frames_1518;
257 u64 rx_frames_jumbo;
258 u64 rx_drops;
Sunil Gouthama2dc5de2015-08-30 12:29:10 +0300259
Thanneeru Srinivasulua05d4842016-02-11 21:50:21 +0530260 u64 rcv_buffer_alloc_failures;
261
Sunil Goutham4863dea2015-05-26 19:20:15 -0700262 /* Tx */
263 u64 tx_frames_ok;
264 u64 tx_drops;
Sunil Goutham4863dea2015-05-26 19:20:15 -0700265 u64 tx_tso;
Thanneeru Srinivasulua05d4842016-02-11 21:50:21 +0530266 u64 tx_timeout;
Sunil Goutham74840b82015-07-29 16:49:42 +0300267 u64 txq_stop;
268 u64 txq_wake;
Sunil Goutham4863dea2015-05-26 19:20:15 -0700269};
270
271struct nicvf {
Sunil Goutham92dc8762015-08-30 12:29:15 +0300272 struct nicvf *pnicvf;
Sunil Goutham4863dea2015-05-26 19:20:15 -0700273 struct net_device *netdev;
274 struct pci_dev *pdev;
275 u8 vf_id;
276 u8 node;
Sunil Goutham92dc8762015-08-30 12:29:15 +0300277 u8 tns_mode:1;
278 u8 sqs_mode:1;
Sunil Gouthamd77a2382015-08-30 12:29:16 +0300279 u8 loopback_supported:1;
Sunil Goutham40fb5f82015-12-10 13:25:19 +0530280 bool hw_tso;
Sunil Goutham4863dea2015-05-26 19:20:15 -0700281 u16 mtu;
282 struct queue_set *qs;
Sunil Goutham92dc8762015-08-30 12:29:15 +0300283#define MAX_SQS_PER_VF_SINGLE_NODE 5
284#define MAX_SQS_PER_VF 11
285 u8 sqs_id;
286 u8 sqs_count; /* Secondary Qset count */
287 struct nicvf *snicvf[MAX_SQS_PER_VF];
288 u8 rx_queues;
289 u8 tx_queues;
290 u8 max_queues;
Sunil Goutham4863dea2015-05-26 19:20:15 -0700291 void __iomem *reg_base;
292 bool link_up;
293 u8 duplex;
294 u32 speed;
295 struct page *rb_page;
296 u32 rb_page_offset;
297 bool rb_alloc_fail;
298 bool rb_work_scheduled;
299 struct delayed_work rbdr_work;
300 struct tasklet_struct rbdr_task;
301 struct tasklet_struct qs_err_task;
302 struct tasklet_struct cq_task;
303 struct nicvf_cq_poll *napi[8];
304 struct nicvf_rss_info rss_info;
305 u8 cpi_alg;
306 /* Interrupt coalescing settings */
307 u32 cq_coalesce_usecs;
308
309 u32 msg_enable;
Sunil Gouthama2dc5de2015-08-30 12:29:10 +0300310 struct nicvf_hw_stats hw_stats;
Sunil Goutham4863dea2015-05-26 19:20:15 -0700311 struct nicvf_drv_stats drv_stats;
312 struct bgx_stats bgx_stats;
313 struct work_struct reset_task;
314
315 /* MSI-X */
316 bool msix_enabled;
317 u8 num_vec;
318 struct msix_entry msix_entries[NIC_VF_MSIX_VECTORS];
319 char irq_name[NIC_VF_MSIX_VECTORS][20];
320 bool irq_allocated[NIC_VF_MSIX_VECTORS];
Sunil Gouthamfb4b7d92016-02-11 21:50:23 +0530321 cpumask_var_t affinity_mask[NIC_VF_MSIX_VECTORS];
Sunil Goutham4863dea2015-05-26 19:20:15 -0700322
Sunil Goutham6051cba2015-08-30 12:29:11 +0300323 /* VF <-> PF mailbox communication */
Sunil Goutham4863dea2015-05-26 19:20:15 -0700324 bool pf_acked;
325 bool pf_nacked;
Pavel Fedinbd049a92015-06-23 17:51:06 +0300326 bool set_mac_pending;
Sunil Goutham4863dea2015-05-26 19:20:15 -0700327} ____cacheline_aligned_in_smp;
328
329/* PF <--> VF Mailbox communication
330 * Eight 64bit registers are shared between PF and VF.
331 * Separate set for each VF.
332 * Writing '1' into last register mbx7 means end of message.
333 */
334
335/* PF <--> VF mailbox communication */
336#define NIC_PF_VF_MAILBOX_SIZE 2
337#define NIC_MBOX_MSG_TIMEOUT 2000 /* ms */
338
339/* Mailbox message types */
340#define NIC_MBOX_MSG_READY 0x01 /* Is PF ready to rcv msgs */
341#define NIC_MBOX_MSG_ACK 0x02 /* ACK the message received */
342#define NIC_MBOX_MSG_NACK 0x03 /* NACK the message received */
343#define NIC_MBOX_MSG_QS_CFG 0x04 /* Configure Qset */
344#define NIC_MBOX_MSG_RQ_CFG 0x05 /* Configure receive queue */
345#define NIC_MBOX_MSG_SQ_CFG 0x06 /* Configure Send queue */
346#define NIC_MBOX_MSG_RQ_DROP_CFG 0x07 /* Configure receive queue */
347#define NIC_MBOX_MSG_SET_MAC 0x08 /* Add MAC ID to DMAC filter */
348#define NIC_MBOX_MSG_SET_MAX_FRS 0x09 /* Set max frame size */
349#define NIC_MBOX_MSG_CPI_CFG 0x0A /* Config CPI, RSSI */
350#define NIC_MBOX_MSG_RSS_SIZE 0x0B /* Get RSS indir_tbl size */
351#define NIC_MBOX_MSG_RSS_CFG 0x0C /* Config RSS table */
352#define NIC_MBOX_MSG_RSS_CFG_CONT 0x0D /* RSS config continuation */
353#define NIC_MBOX_MSG_RQ_BP_CFG 0x0E /* RQ backpressure config */
354#define NIC_MBOX_MSG_RQ_SW_SYNC 0x0F /* Flush inflight pkts to RQ */
355#define NIC_MBOX_MSG_BGX_STATS 0x10 /* Get stats from BGX */
356#define NIC_MBOX_MSG_BGX_LINK_CHANGE 0x11 /* BGX:LMAC link status */
Sunil Goutham92dc8762015-08-30 12:29:15 +0300357#define NIC_MBOX_MSG_ALLOC_SQS 0x12 /* Allocate secondary Qset */
358#define NIC_MBOX_MSG_NICVF_PTR 0x13 /* Send nicvf ptr to PF */
359#define NIC_MBOX_MSG_PNICVF_PTR 0x14 /* Get primary qset nicvf ptr */
360#define NIC_MBOX_MSG_SNICVF_PTR 0x15 /* Send sqet nicvf ptr to PVF */
Sunil Gouthamd77a2382015-08-30 12:29:16 +0300361#define NIC_MBOX_MSG_LOOPBACK 0x16 /* Set interface in loopback */
Sunil Goutham92dc8762015-08-30 12:29:15 +0300362#define NIC_MBOX_MSG_CFG_DONE 0xF0 /* VF configuration done */
363#define NIC_MBOX_MSG_SHUTDOWN 0xF1 /* VF is being shutdown */
Sunil Goutham4863dea2015-05-26 19:20:15 -0700364
365struct nic_cfg_msg {
366 u8 msg;
367 u8 vf_id;
Sunil Goutham4863dea2015-05-26 19:20:15 -0700368 u8 node_id;
Sunil Goutham92dc8762015-08-30 12:29:15 +0300369 u8 tns_mode:1;
370 u8 sqs_mode:1;
Sunil Gouthamd77a2382015-08-30 12:29:16 +0300371 u8 loopback_supported:1;
Aleksey Makarove610cb32015-06-02 11:00:21 -0700372 u8 mac_addr[ETH_ALEN];
Sunil Goutham4863dea2015-05-26 19:20:15 -0700373};
374
375/* Qset configuration */
376struct qs_cfg_msg {
377 u8 msg;
378 u8 num;
Sunil Goutham92dc8762015-08-30 12:29:15 +0300379 u8 sqs_count;
Sunil Goutham4863dea2015-05-26 19:20:15 -0700380 u64 cfg;
381};
382
383/* Receive queue configuration */
384struct rq_cfg_msg {
385 u8 msg;
386 u8 qs_num;
387 u8 rq_num;
388 u64 cfg;
389};
390
391/* Send queue configuration */
392struct sq_cfg_msg {
393 u8 msg;
394 u8 qs_num;
395 u8 sq_num;
Sunil Goutham92dc8762015-08-30 12:29:15 +0300396 bool sqs_mode;
Sunil Goutham4863dea2015-05-26 19:20:15 -0700397 u64 cfg;
398};
399
400/* Set VF's MAC address */
401struct set_mac_msg {
402 u8 msg;
403 u8 vf_id;
Aleksey Makarove610cb32015-06-02 11:00:21 -0700404 u8 mac_addr[ETH_ALEN];
Sunil Goutham4863dea2015-05-26 19:20:15 -0700405};
406
407/* Set Maximum frame size */
408struct set_frs_msg {
409 u8 msg;
410 u8 vf_id;
411 u16 max_frs;
412};
413
414/* Set CPI algorithm type */
415struct cpi_cfg_msg {
416 u8 msg;
417 u8 vf_id;
418 u8 rq_cnt;
419 u8 cpi_alg;
420};
421
422/* Get RSS table size */
423struct rss_sz_msg {
424 u8 msg;
425 u8 vf_id;
426 u16 ind_tbl_size;
427};
428
429/* Set RSS configuration */
430struct rss_cfg_msg {
431 u8 msg;
432 u8 vf_id;
433 u8 hash_bits;
434 u8 tbl_len;
435 u8 tbl_offset;
436#define RSS_IND_TBL_LEN_PER_MBX_MSG 8
437 u8 ind_tbl[RSS_IND_TBL_LEN_PER_MBX_MSG];
438};
439
440struct bgx_stats_msg {
441 u8 msg;
442 u8 vf_id;
443 u8 rx;
444 u8 idx;
445 u64 stats;
446};
447
448/* Physical interface link status */
449struct bgx_link_status {
450 u8 msg;
451 u8 link_up;
452 u8 duplex;
453 u32 speed;
454};
455
Sunil Goutham92dc8762015-08-30 12:29:15 +0300456/* Get Extra Qset IDs */
457struct sqs_alloc {
458 u8 msg;
459 u8 vf_id;
460 u8 qs_count;
461};
462
463struct nicvf_ptr {
464 u8 msg;
465 u8 vf_id;
466 bool sqs_mode;
467 u8 sqs_id;
468 u64 nicvf;
469};
470
Sunil Gouthamd77a2382015-08-30 12:29:16 +0300471/* Set interface in loopback mode */
472struct set_loopback {
473 u8 msg;
474 u8 vf_id;
475 bool enable;
476};
477
Sunil Goutham4863dea2015-05-26 19:20:15 -0700478/* 128 bit shared memory between PF and each VF */
479union nic_mbx {
480 struct { u8 msg; } msg;
481 struct nic_cfg_msg nic_cfg;
482 struct qs_cfg_msg qs;
483 struct rq_cfg_msg rq;
484 struct sq_cfg_msg sq;
485 struct set_mac_msg mac;
486 struct set_frs_msg frs;
487 struct cpi_cfg_msg cpi_cfg;
488 struct rss_sz_msg rss_size;
489 struct rss_cfg_msg rss_cfg;
490 struct bgx_stats_msg bgx_stats;
491 struct bgx_link_status link_status;
Sunil Goutham92dc8762015-08-30 12:29:15 +0300492 struct sqs_alloc sqs_alloc;
493 struct nicvf_ptr nicvf;
Sunil Gouthamd77a2382015-08-30 12:29:16 +0300494 struct set_loopback lbk;
Sunil Goutham4863dea2015-05-26 19:20:15 -0700495};
496
Robert Richterd768b672015-06-02 11:00:18 -0700497#define NIC_NODE_ID_MASK 0x03
498#define NIC_NODE_ID_SHIFT 44
499
500static inline int nic_get_node_id(struct pci_dev *pdev)
501{
502 u64 addr = pci_resource_start(pdev, PCI_CFG_REG_BAR_NUM);
503 return ((addr >> NIC_NODE_ID_SHIFT) & NIC_NODE_ID_MASK);
504}
505
Sunil Goutham40fb5f82015-12-10 13:25:19 +0530506static inline bool pass1_silicon(struct pci_dev *pdev)
507{
508 return pdev->revision < 8;
509}
510
Sunil Goutham4863dea2015-05-26 19:20:15 -0700511int nicvf_set_real_num_queues(struct net_device *netdev,
512 int tx_queues, int rx_queues);
513int nicvf_open(struct net_device *netdev);
514int nicvf_stop(struct net_device *netdev);
515int nicvf_send_msg_to_pf(struct nicvf *vf, union nic_mbx *mbx);
Sunil Goutham4863dea2015-05-26 19:20:15 -0700516void nicvf_config_rss(struct nicvf *nic);
517void nicvf_set_rss_key(struct nicvf *nic);
Sunil Goutham4863dea2015-05-26 19:20:15 -0700518void nicvf_set_ethtool_ops(struct net_device *netdev);
519void nicvf_update_stats(struct nicvf *nic);
520void nicvf_update_lmac_stats(struct nicvf *nic);
521
522#endif /* NIC_H */