blob: a4615fcc3d001f6a0efba58ddfc5b5573ad91069 [file] [log] [blame]
eric miaofe69af02008-02-14 15:48:23 +08001/*
2 * drivers/mtd/nand/pxa3xx_nand.c
3 *
4 * Copyright © 2005 Intel Corporation
5 * Copyright © 2006 Marvell International Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
Ezequiel Garciade484a32013-11-07 12:17:10 -030010 *
11 * See Documentation/mtd/nand/pxa3xx-nand.txt for more details.
eric miaofe69af02008-02-14 15:48:23 +080012 */
13
Haojian Zhuanga88bdbb2009-09-11 19:33:58 +080014#include <linux/kernel.h>
eric miaofe69af02008-02-14 15:48:23 +080015#include <linux/module.h>
16#include <linux/interrupt.h>
17#include <linux/platform_device.h>
18#include <linux/dma-mapping.h>
19#include <linux/delay.h>
20#include <linux/clk.h>
21#include <linux/mtd/mtd.h>
22#include <linux/mtd/nand.h>
23#include <linux/mtd/partitions.h>
David Woodhousea1c06ee2008-04-22 20:39:43 +010024#include <linux/io.h>
25#include <linux/irq.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090026#include <linux/slab.h>
Daniel Mack1e7ba632012-07-22 19:51:02 +020027#include <linux/of.h>
28#include <linux/of_device.h>
Ezequiel Garcia776f2652013-11-14 18:25:28 -030029#include <linux/of_mtd.h>
eric miaofe69af02008-02-14 15:48:23 +080030
Ezequiel Garciaf4db2e32013-08-12 14:14:56 -030031#if defined(CONFIG_ARCH_PXA) || defined(CONFIG_ARCH_MMP)
32#define ARCH_HAS_DMA
33#endif
34
35#ifdef ARCH_HAS_DMA
Eric Miaoafb5b5c2008-12-01 11:43:08 +080036#include <mach/dma.h>
Ezequiel Garciaf4db2e32013-08-12 14:14:56 -030037#endif
38
Arnd Bergmann293b2da2012-08-24 15:16:48 +020039#include <linux/platform_data/mtd-nand-pxa3xx.h>
eric miaofe69af02008-02-14 15:48:23 +080040
Nicholas Mc Guiree5860c12015-02-01 11:55:37 -050041#define CHIP_DELAY_TIMEOUT msecs_to_jiffies(200)
42#define NAND_STOP_DELAY msecs_to_jiffies(40)
Lei Wen4eb2da82011-02-28 10:32:13 +080043#define PAGE_CHUNK_SIZE (2048)
eric miaofe69af02008-02-14 15:48:23 +080044
Ezequiel Garcia62e8b852013-10-04 15:30:38 -030045/*
46 * Define a buffer size for the initial command that detects the flash device:
47 * STATUS, READID and PARAM. The largest of these is the PARAM command,
48 * needing 256 bytes.
49 */
50#define INIT_BUFFER_SIZE 256
51
eric miaofe69af02008-02-14 15:48:23 +080052/* registers and bit definitions */
53#define NDCR (0x00) /* Control register */
54#define NDTR0CS0 (0x04) /* Timing Parameter 0 for CS0 */
55#define NDTR1CS0 (0x0C) /* Timing Parameter 1 for CS0 */
56#define NDSR (0x14) /* Status Register */
57#define NDPCR (0x18) /* Page Count Register */
58#define NDBDR0 (0x1C) /* Bad Block Register 0 */
59#define NDBDR1 (0x20) /* Bad Block Register 1 */
Ezequiel Garcia43bcfd22013-11-14 18:25:29 -030060#define NDECCCTRL (0x28) /* ECC control */
eric miaofe69af02008-02-14 15:48:23 +080061#define NDDB (0x40) /* Data Buffer */
62#define NDCB0 (0x48) /* Command Buffer0 */
63#define NDCB1 (0x4C) /* Command Buffer1 */
64#define NDCB2 (0x50) /* Command Buffer2 */
65
66#define NDCR_SPARE_EN (0x1 << 31)
67#define NDCR_ECC_EN (0x1 << 30)
68#define NDCR_DMA_EN (0x1 << 29)
69#define NDCR_ND_RUN (0x1 << 28)
70#define NDCR_DWIDTH_C (0x1 << 27)
71#define NDCR_DWIDTH_M (0x1 << 26)
72#define NDCR_PAGE_SZ (0x1 << 24)
73#define NDCR_NCSX (0x1 << 23)
74#define NDCR_ND_MODE (0x3 << 21)
75#define NDCR_NAND_MODE (0x0)
76#define NDCR_CLR_PG_CNT (0x1 << 20)
Lei Wenf8155a42011-02-28 10:32:11 +080077#define NDCR_STOP_ON_UNCOR (0x1 << 19)
eric miaofe69af02008-02-14 15:48:23 +080078#define NDCR_RD_ID_CNT_MASK (0x7 << 16)
79#define NDCR_RD_ID_CNT(x) (((x) << 16) & NDCR_RD_ID_CNT_MASK)
80
81#define NDCR_RA_START (0x1 << 15)
82#define NDCR_PG_PER_BLK (0x1 << 14)
83#define NDCR_ND_ARB_EN (0x1 << 12)
Lei Wenf8155a42011-02-28 10:32:11 +080084#define NDCR_INT_MASK (0xFFF)
eric miaofe69af02008-02-14 15:48:23 +080085
86#define NDSR_MASK (0xfff)
Ezequiel Garcia87f53362013-11-14 18:25:39 -030087#define NDSR_ERR_CNT_OFF (16)
88#define NDSR_ERR_CNT_MASK (0x1f)
89#define NDSR_ERR_CNT(sr) ((sr >> NDSR_ERR_CNT_OFF) & NDSR_ERR_CNT_MASK)
Lei Wenf8155a42011-02-28 10:32:11 +080090#define NDSR_RDY (0x1 << 12)
91#define NDSR_FLASH_RDY (0x1 << 11)
eric miaofe69af02008-02-14 15:48:23 +080092#define NDSR_CS0_PAGED (0x1 << 10)
93#define NDSR_CS1_PAGED (0x1 << 9)
94#define NDSR_CS0_CMDD (0x1 << 8)
95#define NDSR_CS1_CMDD (0x1 << 7)
96#define NDSR_CS0_BBD (0x1 << 6)
97#define NDSR_CS1_BBD (0x1 << 5)
Ezequiel Garcia87f53362013-11-14 18:25:39 -030098#define NDSR_UNCORERR (0x1 << 4)
99#define NDSR_CORERR (0x1 << 3)
eric miaofe69af02008-02-14 15:48:23 +0800100#define NDSR_WRDREQ (0x1 << 2)
101#define NDSR_RDDREQ (0x1 << 1)
102#define NDSR_WRCMDREQ (0x1)
103
Ezequiel Garcia41a63432013-08-12 14:14:51 -0300104#define NDCB0_LEN_OVRD (0x1 << 28)
Lei Wen4eb2da82011-02-28 10:32:13 +0800105#define NDCB0_ST_ROW_EN (0x1 << 26)
eric miaofe69af02008-02-14 15:48:23 +0800106#define NDCB0_AUTO_RS (0x1 << 25)
107#define NDCB0_CSEL (0x1 << 24)
Ezequiel Garcia70ed8522013-11-14 18:25:37 -0300108#define NDCB0_EXT_CMD_TYPE_MASK (0x7 << 29)
109#define NDCB0_EXT_CMD_TYPE(x) (((x) << 29) & NDCB0_EXT_CMD_TYPE_MASK)
eric miaofe69af02008-02-14 15:48:23 +0800110#define NDCB0_CMD_TYPE_MASK (0x7 << 21)
111#define NDCB0_CMD_TYPE(x) (((x) << 21) & NDCB0_CMD_TYPE_MASK)
112#define NDCB0_NC (0x1 << 20)
113#define NDCB0_DBC (0x1 << 19)
114#define NDCB0_ADDR_CYC_MASK (0x7 << 16)
115#define NDCB0_ADDR_CYC(x) (((x) << 16) & NDCB0_ADDR_CYC_MASK)
116#define NDCB0_CMD2_MASK (0xff << 8)
117#define NDCB0_CMD1_MASK (0xff)
118#define NDCB0_ADDR_CYC_SHIFT (16)
119
Ezequiel Garcia70ed8522013-11-14 18:25:37 -0300120#define EXT_CMD_TYPE_DISPATCH 6 /* Command dispatch */
121#define EXT_CMD_TYPE_NAKED_RW 5 /* Naked read or Naked write */
122#define EXT_CMD_TYPE_READ 4 /* Read */
123#define EXT_CMD_TYPE_DISP_WR 4 /* Command dispatch with write */
124#define EXT_CMD_TYPE_FINAL 3 /* Final command */
125#define EXT_CMD_TYPE_LAST_RW 1 /* Last naked read/write */
126#define EXT_CMD_TYPE_MONO 0 /* Monolithic read/write */
127
eric miaofe69af02008-02-14 15:48:23 +0800128/* macros for registers read/write */
129#define nand_writel(info, off, val) \
Thomas Petazzonib7e460622014-05-22 14:56:52 +0200130 writel_relaxed((val), (info)->mmio_base + (off))
eric miaofe69af02008-02-14 15:48:23 +0800131
132#define nand_readl(info, off) \
Thomas Petazzonib7e460622014-05-22 14:56:52 +0200133 readl_relaxed((info)->mmio_base + (off))
eric miaofe69af02008-02-14 15:48:23 +0800134
135/* error code and state */
136enum {
137 ERR_NONE = 0,
138 ERR_DMABUSERR = -1,
139 ERR_SENDCMD = -2,
Ezequiel Garcia87f53362013-11-14 18:25:39 -0300140 ERR_UNCORERR = -3,
eric miaofe69af02008-02-14 15:48:23 +0800141 ERR_BBERR = -4,
Ezequiel Garcia87f53362013-11-14 18:25:39 -0300142 ERR_CORERR = -5,
eric miaofe69af02008-02-14 15:48:23 +0800143};
144
145enum {
Lei Wenf8155a42011-02-28 10:32:11 +0800146 STATE_IDLE = 0,
Lei Wend4568822011-07-14 20:44:32 -0700147 STATE_PREPARED,
eric miaofe69af02008-02-14 15:48:23 +0800148 STATE_CMD_HANDLE,
149 STATE_DMA_READING,
150 STATE_DMA_WRITING,
151 STATE_DMA_DONE,
152 STATE_PIO_READING,
153 STATE_PIO_WRITING,
Lei Wenf8155a42011-02-28 10:32:11 +0800154 STATE_CMD_DONE,
155 STATE_READY,
eric miaofe69af02008-02-14 15:48:23 +0800156};
157
Ezequiel Garciac0f3b862013-08-10 16:34:52 -0300158enum pxa3xx_nand_variant {
159 PXA3XX_NAND_VARIANT_PXA,
160 PXA3XX_NAND_VARIANT_ARMADA370,
161};
162
Lei Wend4568822011-07-14 20:44:32 -0700163struct pxa3xx_nand_host {
164 struct nand_chip chip;
Lei Wend4568822011-07-14 20:44:32 -0700165 struct mtd_info *mtd;
166 void *info_data;
eric miaofe69af02008-02-14 15:48:23 +0800167
Lei Wend4568822011-07-14 20:44:32 -0700168 /* page size of attached chip */
Lei Wend4568822011-07-14 20:44:32 -0700169 int use_ecc;
Lei Wenf3c8cfc2011-07-14 20:44:33 -0700170 int cs;
Lei Wend4568822011-07-14 20:44:32 -0700171
172 /* calculated from pxa3xx_nand_flash data */
173 unsigned int col_addr_cycles;
174 unsigned int row_addr_cycles;
175 size_t read_id_bytes;
176
Lei Wend4568822011-07-14 20:44:32 -0700177};
178
179struct pxa3xx_nand_info {
Lei Wen401e67e2011-02-28 10:32:14 +0800180 struct nand_hw_control controller;
eric miaofe69af02008-02-14 15:48:23 +0800181 struct platform_device *pdev;
eric miaofe69af02008-02-14 15:48:23 +0800182
183 struct clk *clk;
184 void __iomem *mmio_base;
Haojian Zhuang8638fac2009-09-10 14:11:44 +0800185 unsigned long mmio_phys;
Ezequiel Garcia55d9fd62013-11-14 18:25:26 -0300186 struct completion cmd_complete, dev_ready;
eric miaofe69af02008-02-14 15:48:23 +0800187
188 unsigned int buf_start;
189 unsigned int buf_count;
Ezequiel Garcia62e8b852013-10-04 15:30:38 -0300190 unsigned int buf_size;
Ezequiel Garciafa543be2013-11-14 18:25:36 -0300191 unsigned int data_buff_pos;
192 unsigned int oob_buff_pos;
eric miaofe69af02008-02-14 15:48:23 +0800193
194 /* DMA information */
195 int drcmr_dat;
196 int drcmr_cmd;
197
198 unsigned char *data_buff;
Lei Wen18c81b12010-08-17 17:25:57 +0800199 unsigned char *oob_buff;
eric miaofe69af02008-02-14 15:48:23 +0800200 dma_addr_t data_buff_phys;
eric miaofe69af02008-02-14 15:48:23 +0800201 int data_dma_ch;
202 struct pxa_dma_desc *data_desc;
203 dma_addr_t data_desc_addr;
204
Lei Wenf3c8cfc2011-07-14 20:44:33 -0700205 struct pxa3xx_nand_host *host[NUM_CHIP_SELECT];
eric miaofe69af02008-02-14 15:48:23 +0800206 unsigned int state;
207
Ezequiel Garciac0f3b862013-08-10 16:34:52 -0300208 /*
209 * This driver supports NFCv1 (as found in PXA SoC)
210 * and NFCv2 (as found in Armada 370/XP SoC).
211 */
212 enum pxa3xx_nand_variant variant;
213
Lei Wenf3c8cfc2011-07-14 20:44:33 -0700214 int cs;
eric miaofe69af02008-02-14 15:48:23 +0800215 int use_ecc; /* use HW ECC ? */
Ezequiel Garcia43bcfd22013-11-14 18:25:29 -0300216 int ecc_bch; /* using BCH ECC? */
eric miaofe69af02008-02-14 15:48:23 +0800217 int use_dma; /* use DMA ? */
Ezequiel Garcia5bb653e2013-08-12 14:14:49 -0300218 int use_spare; /* use spare ? */
Ezequiel Garcia55d9fd62013-11-14 18:25:26 -0300219 int need_wait;
eric miaofe69af02008-02-14 15:48:23 +0800220
Ezequiel Garcia2128b082013-11-07 12:17:16 -0300221 unsigned int data_size; /* data to be read from FIFO */
Ezequiel Garcia70ed8522013-11-14 18:25:37 -0300222 unsigned int chunk_size; /* split commands chunk size */
Lei Wend4568822011-07-14 20:44:32 -0700223 unsigned int oob_size;
Ezequiel Garcia43bcfd22013-11-14 18:25:29 -0300224 unsigned int spare_size;
225 unsigned int ecc_size;
Ezequiel Garcia87f53362013-11-14 18:25:39 -0300226 unsigned int ecc_err_cnt;
227 unsigned int max_bitflips;
eric miaofe69af02008-02-14 15:48:23 +0800228 int retcode;
eric miaofe69af02008-02-14 15:48:23 +0800229
Ezequiel Garcia48cf7ef2013-08-12 14:14:55 -0300230 /* cached register value */
231 uint32_t reg_ndcr;
232 uint32_t ndtr0cs0;
233 uint32_t ndtr1cs0;
234
eric miaofe69af02008-02-14 15:48:23 +0800235 /* generated NDCBx register values */
236 uint32_t ndcb0;
237 uint32_t ndcb1;
238 uint32_t ndcb2;
Ezequiel Garcia3a1a3442013-08-12 14:14:50 -0300239 uint32_t ndcb3;
eric miaofe69af02008-02-14 15:48:23 +0800240};
241
Rusty Russell90ab5ee2012-01-13 09:32:20 +1030242static bool use_dma = 1;
eric miaofe69af02008-02-14 15:48:23 +0800243module_param(use_dma, bool, 0444);
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300244MODULE_PARM_DESC(use_dma, "enable DMA for data transferring to/from NAND HW");
eric miaofe69af02008-02-14 15:48:23 +0800245
Lei Wenc1f82472010-08-17 13:50:23 +0800246static struct pxa3xx_nand_timing timing[] = {
Lei Wen227a8862010-08-18 18:00:03 +0800247 { 40, 80, 60, 100, 80, 100, 90000, 400, 40, },
248 { 10, 0, 20, 40, 30, 40, 11123, 110, 10, },
249 { 10, 25, 15, 25, 15, 30, 25000, 60, 10, },
250 { 10, 35, 15, 25, 15, 25, 25000, 60, 10, },
eric miaofe69af02008-02-14 15:48:23 +0800251};
252
Lei Wenc1f82472010-08-17 13:50:23 +0800253static struct pxa3xx_nand_flash builtin_flash_types[] = {
Lei Wen4332c112011-03-03 11:27:01 +0800254{ "DEFAULT FLASH", 0, 0, 2048, 8, 8, 0, &timing[0] },
255{ "64MiB 16-bit", 0x46ec, 32, 512, 16, 16, 4096, &timing[1] },
256{ "256MiB 8-bit", 0xdaec, 64, 2048, 8, 8, 2048, &timing[1] },
257{ "4GiB 8-bit", 0xd7ec, 128, 4096, 8, 8, 8192, &timing[1] },
258{ "128MiB 8-bit", 0xa12c, 64, 2048, 8, 8, 1024, &timing[2] },
259{ "128MiB 16-bit", 0xb12c, 64, 2048, 16, 16, 1024, &timing[2] },
260{ "512MiB 8-bit", 0xdc2c, 64, 2048, 8, 8, 4096, &timing[2] },
261{ "512MiB 16-bit", 0xcc2c, 64, 2048, 16, 16, 4096, &timing[2] },
262{ "256MiB 16-bit", 0xba20, 64, 2048, 16, 16, 2048, &timing[3] },
eric miaofe69af02008-02-14 15:48:23 +0800263};
264
Ezequiel Garcia776f2652013-11-14 18:25:28 -0300265static u8 bbt_pattern[] = {'M', 'V', 'B', 'b', 't', '0' };
266static u8 bbt_mirror_pattern[] = {'1', 't', 'b', 'B', 'V', 'M' };
267
268static struct nand_bbt_descr bbt_main_descr = {
269 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
270 | NAND_BBT_2BIT | NAND_BBT_VERSION,
271 .offs = 8,
272 .len = 6,
273 .veroffs = 14,
274 .maxblocks = 8, /* Last 8 blocks in each chip */
275 .pattern = bbt_pattern
276};
277
278static struct nand_bbt_descr bbt_mirror_descr = {
279 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
280 | NAND_BBT_2BIT | NAND_BBT_VERSION,
281 .offs = 8,
282 .len = 6,
283 .veroffs = 14,
284 .maxblocks = 8, /* Last 8 blocks in each chip */
285 .pattern = bbt_mirror_pattern
286};
287
Rodolfo Giometti3db227b2014-01-13 15:35:38 +0100288static struct nand_ecclayout ecc_layout_2KB_bch4bit = {
289 .eccbytes = 32,
290 .eccpos = {
291 32, 33, 34, 35, 36, 37, 38, 39,
292 40, 41, 42, 43, 44, 45, 46, 47,
293 48, 49, 50, 51, 52, 53, 54, 55,
294 56, 57, 58, 59, 60, 61, 62, 63},
295 .oobfree = { {2, 30} }
296};
297
Ezequiel Garcia70ed8522013-11-14 18:25:37 -0300298static struct nand_ecclayout ecc_layout_4KB_bch4bit = {
299 .eccbytes = 64,
300 .eccpos = {
301 32, 33, 34, 35, 36, 37, 38, 39,
302 40, 41, 42, 43, 44, 45, 46, 47,
303 48, 49, 50, 51, 52, 53, 54, 55,
304 56, 57, 58, 59, 60, 61, 62, 63,
305 96, 97, 98, 99, 100, 101, 102, 103,
306 104, 105, 106, 107, 108, 109, 110, 111,
307 112, 113, 114, 115, 116, 117, 118, 119,
308 120, 121, 122, 123, 124, 125, 126, 127},
309 /* Bootrom looks in bytes 0 & 5 for bad blocks */
310 .oobfree = { {6, 26}, { 64, 32} }
311};
312
313static struct nand_ecclayout ecc_layout_4KB_bch8bit = {
314 .eccbytes = 128,
315 .eccpos = {
316 32, 33, 34, 35, 36, 37, 38, 39,
317 40, 41, 42, 43, 44, 45, 46, 47,
318 48, 49, 50, 51, 52, 53, 54, 55,
319 56, 57, 58, 59, 60, 61, 62, 63},
320 .oobfree = { }
321};
322
Lei Wen227a8862010-08-18 18:00:03 +0800323/* Define a default flash type setting serve as flash detecting only */
324#define DEFAULT_FLASH_TYPE (&builtin_flash_types[0])
325
eric miaofe69af02008-02-14 15:48:23 +0800326#define NDTR0_tCH(c) (min((c), 7) << 19)
327#define NDTR0_tCS(c) (min((c), 7) << 16)
328#define NDTR0_tWH(c) (min((c), 7) << 11)
329#define NDTR0_tWP(c) (min((c), 7) << 8)
330#define NDTR0_tRH(c) (min((c), 7) << 3)
331#define NDTR0_tRP(c) (min((c), 7) << 0)
332
333#define NDTR1_tR(c) (min((c), 65535) << 16)
334#define NDTR1_tWHR(c) (min((c), 15) << 4)
335#define NDTR1_tAR(c) (min((c), 15) << 0)
336
337/* convert nano-seconds to nand flash controller clock cycles */
Axel Lin93b352f2010-08-16 16:09:09 +0800338#define ns2cycle(ns, clk) (int)((ns) * (clk / 1000000) / 1000)
eric miaofe69af02008-02-14 15:48:23 +0800339
Jingoo Han17754ad2014-05-07 17:49:13 +0900340static const struct of_device_id pxa3xx_nand_dt_ids[] = {
Ezequiel Garciac7e9c7e2013-11-07 12:17:14 -0300341 {
342 .compatible = "marvell,pxa3xx-nand",
343 .data = (void *)PXA3XX_NAND_VARIANT_PXA,
344 },
Ezequiel Garcia1963ff92013-12-24 12:40:07 -0300345 {
346 .compatible = "marvell,armada370-nand",
347 .data = (void *)PXA3XX_NAND_VARIANT_ARMADA370,
348 },
Ezequiel Garciac7e9c7e2013-11-07 12:17:14 -0300349 {}
350};
351MODULE_DEVICE_TABLE(of, pxa3xx_nand_dt_ids);
352
353static enum pxa3xx_nand_variant
354pxa3xx_nand_get_variant(struct platform_device *pdev)
355{
356 const struct of_device_id *of_id =
357 of_match_device(pxa3xx_nand_dt_ids, &pdev->dev);
358 if (!of_id)
359 return PXA3XX_NAND_VARIANT_PXA;
360 return (enum pxa3xx_nand_variant)of_id->data;
361}
362
Lei Wend4568822011-07-14 20:44:32 -0700363static void pxa3xx_nand_set_timing(struct pxa3xx_nand_host *host,
Enrico Scholz7dad4822008-08-29 12:59:50 +0200364 const struct pxa3xx_nand_timing *t)
eric miaofe69af02008-02-14 15:48:23 +0800365{
Lei Wend4568822011-07-14 20:44:32 -0700366 struct pxa3xx_nand_info *info = host->info_data;
eric miaofe69af02008-02-14 15:48:23 +0800367 unsigned long nand_clk = clk_get_rate(info->clk);
368 uint32_t ndtr0, ndtr1;
369
370 ndtr0 = NDTR0_tCH(ns2cycle(t->tCH, nand_clk)) |
371 NDTR0_tCS(ns2cycle(t->tCS, nand_clk)) |
372 NDTR0_tWH(ns2cycle(t->tWH, nand_clk)) |
373 NDTR0_tWP(ns2cycle(t->tWP, nand_clk)) |
374 NDTR0_tRH(ns2cycle(t->tRH, nand_clk)) |
375 NDTR0_tRP(ns2cycle(t->tRP, nand_clk));
376
377 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) |
378 NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) |
379 NDTR1_tAR(ns2cycle(t->tAR, nand_clk));
380
Ezequiel Garcia48cf7ef2013-08-12 14:14:55 -0300381 info->ndtr0cs0 = ndtr0;
382 info->ndtr1cs0 = ndtr1;
eric miaofe69af02008-02-14 15:48:23 +0800383 nand_writel(info, NDTR0CS0, ndtr0);
384 nand_writel(info, NDTR1CS0, ndtr1);
385}
386
Ezequiel Garcia6a3e4862013-11-07 12:17:18 -0300387/*
388 * Set the data and OOB size, depending on the selected
389 * spare and ECC configuration.
390 * Only applicable to READ0, READOOB and PAGEPROG commands.
391 */
Ezequiel Garciafa543be2013-11-14 18:25:36 -0300392static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info,
393 struct mtd_info *mtd)
eric miaofe69af02008-02-14 15:48:23 +0800394{
Ezequiel Garcia48cf7ef2013-08-12 14:14:55 -0300395 int oob_enable = info->reg_ndcr & NDCR_SPARE_EN;
Lei Wen9d8b1042010-08-17 14:09:30 +0800396
Ezequiel Garciafa543be2013-11-14 18:25:36 -0300397 info->data_size = mtd->writesize;
Ezequiel Garcia43bcfd22013-11-14 18:25:29 -0300398 if (!oob_enable)
Lei Wen9d8b1042010-08-17 14:09:30 +0800399 return;
Lei Wen9d8b1042010-08-17 14:09:30 +0800400
Ezequiel Garcia43bcfd22013-11-14 18:25:29 -0300401 info->oob_size = info->spare_size;
402 if (!info->use_ecc)
403 info->oob_size += info->ecc_size;
Lei Wen18c81b12010-08-17 17:25:57 +0800404}
405
Lei Wenf8155a42011-02-28 10:32:11 +0800406/**
407 * NOTE: it is a must to set ND_RUN firstly, then write
408 * command buffer, otherwise, it does not work.
409 * We enable all the interrupt at the same time, and
410 * let pxa3xx_nand_irq to handle all logic.
411 */
412static void pxa3xx_nand_start(struct pxa3xx_nand_info *info)
413{
414 uint32_t ndcr;
415
Ezequiel Garcia48cf7ef2013-08-12 14:14:55 -0300416 ndcr = info->reg_ndcr;
Ezequiel Garciacd9d1182013-08-12 14:14:48 -0300417
Ezequiel Garcia43bcfd22013-11-14 18:25:29 -0300418 if (info->use_ecc) {
Ezequiel Garciacd9d1182013-08-12 14:14:48 -0300419 ndcr |= NDCR_ECC_EN;
Ezequiel Garcia43bcfd22013-11-14 18:25:29 -0300420 if (info->ecc_bch)
421 nand_writel(info, NDECCCTRL, 0x1);
422 } else {
Ezequiel Garciacd9d1182013-08-12 14:14:48 -0300423 ndcr &= ~NDCR_ECC_EN;
Ezequiel Garcia43bcfd22013-11-14 18:25:29 -0300424 if (info->ecc_bch)
425 nand_writel(info, NDECCCTRL, 0x0);
426 }
Ezequiel Garciacd9d1182013-08-12 14:14:48 -0300427
428 if (info->use_dma)
429 ndcr |= NDCR_DMA_EN;
430 else
431 ndcr &= ~NDCR_DMA_EN;
432
Ezequiel Garcia5bb653e2013-08-12 14:14:49 -0300433 if (info->use_spare)
434 ndcr |= NDCR_SPARE_EN;
435 else
436 ndcr &= ~NDCR_SPARE_EN;
437
Lei Wenf8155a42011-02-28 10:32:11 +0800438 ndcr |= NDCR_ND_RUN;
439
440 /* clear status bits and run */
441 nand_writel(info, NDCR, 0);
442 nand_writel(info, NDSR, NDSR_MASK);
443 nand_writel(info, NDCR, ndcr);
444}
445
446static void pxa3xx_nand_stop(struct pxa3xx_nand_info *info)
447{
448 uint32_t ndcr;
449 int timeout = NAND_STOP_DELAY;
450
451 /* wait RUN bit in NDCR become 0 */
452 ndcr = nand_readl(info, NDCR);
453 while ((ndcr & NDCR_ND_RUN) && (timeout-- > 0)) {
454 ndcr = nand_readl(info, NDCR);
455 udelay(1);
456 }
457
458 if (timeout <= 0) {
459 ndcr &= ~NDCR_ND_RUN;
460 nand_writel(info, NDCR, ndcr);
461 }
462 /* clear status bits */
463 nand_writel(info, NDSR, NDSR_MASK);
464}
465
Ezequiel Garcia57ff88f2013-08-12 14:14:57 -0300466static void __maybe_unused
467enable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
eric miaofe69af02008-02-14 15:48:23 +0800468{
469 uint32_t ndcr;
470
471 ndcr = nand_readl(info, NDCR);
472 nand_writel(info, NDCR, ndcr & ~int_mask);
473}
474
475static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
476{
477 uint32_t ndcr;
478
479 ndcr = nand_readl(info, NDCR);
480 nand_writel(info, NDCR, ndcr | int_mask);
481}
482
Maxime Ripard8dad0382015-02-18 11:32:07 +0100483static void drain_fifo(struct pxa3xx_nand_info *info, void *data, int len)
484{
485 if (info->ecc_bch) {
486 int timeout;
487
488 /*
489 * According to the datasheet, when reading from NDDB
490 * with BCH enabled, after each 32 bytes reads, we
491 * have to make sure that the NDSR.RDDREQ bit is set.
492 *
493 * Drain the FIFO 8 32 bits reads at a time, and skip
494 * the polling on the last read.
495 */
496 while (len > 8) {
497 __raw_readsl(info->mmio_base + NDDB, data, 8);
498
499 for (timeout = 0;
500 !(nand_readl(info, NDSR) & NDSR_RDDREQ);
501 timeout++) {
502 if (timeout >= 5) {
503 dev_err(&info->pdev->dev,
504 "Timeout on RDDREQ while draining the FIFO\n");
505 return;
506 }
507
508 mdelay(1);
509 }
510
511 data += 32;
512 len -= 8;
513 }
514 }
515
516 __raw_readsl(info->mmio_base + NDDB, data, len);
517}
518
Lei Wenf8155a42011-02-28 10:32:11 +0800519static void handle_data_pio(struct pxa3xx_nand_info *info)
eric miaofe69af02008-02-14 15:48:23 +0800520{
Ezequiel Garcia70ed8522013-11-14 18:25:37 -0300521 unsigned int do_bytes = min(info->data_size, info->chunk_size);
Ezequiel Garciafa543be2013-11-14 18:25:36 -0300522
eric miaofe69af02008-02-14 15:48:23 +0800523 switch (info->state) {
524 case STATE_PIO_WRITING:
Ezequiel Garciafa543be2013-11-14 18:25:36 -0300525 __raw_writesl(info->mmio_base + NDDB,
526 info->data_buff + info->data_buff_pos,
527 DIV_ROUND_UP(do_bytes, 4));
528
Lei Wen9d8b1042010-08-17 14:09:30 +0800529 if (info->oob_size > 0)
Ezequiel Garciafa543be2013-11-14 18:25:36 -0300530 __raw_writesl(info->mmio_base + NDDB,
531 info->oob_buff + info->oob_buff_pos,
532 DIV_ROUND_UP(info->oob_size, 4));
eric miaofe69af02008-02-14 15:48:23 +0800533 break;
534 case STATE_PIO_READING:
Maxime Ripard8dad0382015-02-18 11:32:07 +0100535 drain_fifo(info,
536 info->data_buff + info->data_buff_pos,
537 DIV_ROUND_UP(do_bytes, 4));
Ezequiel Garciafa543be2013-11-14 18:25:36 -0300538
Lei Wen9d8b1042010-08-17 14:09:30 +0800539 if (info->oob_size > 0)
Maxime Ripard8dad0382015-02-18 11:32:07 +0100540 drain_fifo(info,
541 info->oob_buff + info->oob_buff_pos,
542 DIV_ROUND_UP(info->oob_size, 4));
eric miaofe69af02008-02-14 15:48:23 +0800543 break;
544 default:
Lei Wenda675b42011-07-14 20:44:31 -0700545 dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__,
eric miaofe69af02008-02-14 15:48:23 +0800546 info->state);
Lei Wenf8155a42011-02-28 10:32:11 +0800547 BUG();
eric miaofe69af02008-02-14 15:48:23 +0800548 }
Ezequiel Garciafa543be2013-11-14 18:25:36 -0300549
550 /* Update buffer pointers for multi-page read/write */
551 info->data_buff_pos += do_bytes;
552 info->oob_buff_pos += info->oob_size;
553 info->data_size -= do_bytes;
eric miaofe69af02008-02-14 15:48:23 +0800554}
555
Ezequiel Garciaf4db2e32013-08-12 14:14:56 -0300556#ifdef ARCH_HAS_DMA
Lei Wenf8155a42011-02-28 10:32:11 +0800557static void start_data_dma(struct pxa3xx_nand_info *info)
eric miaofe69af02008-02-14 15:48:23 +0800558{
559 struct pxa_dma_desc *desc = info->data_desc;
Lei Wen9d8b1042010-08-17 14:09:30 +0800560 int dma_len = ALIGN(info->data_size + info->oob_size, 32);
eric miaofe69af02008-02-14 15:48:23 +0800561
562 desc->ddadr = DDADR_STOP;
563 desc->dcmd = DCMD_ENDIRQEN | DCMD_WIDTH4 | DCMD_BURST32 | dma_len;
564
Lei Wenf8155a42011-02-28 10:32:11 +0800565 switch (info->state) {
566 case STATE_DMA_WRITING:
eric miaofe69af02008-02-14 15:48:23 +0800567 desc->dsadr = info->data_buff_phys;
Haojian Zhuang8638fac2009-09-10 14:11:44 +0800568 desc->dtadr = info->mmio_phys + NDDB;
eric miaofe69af02008-02-14 15:48:23 +0800569 desc->dcmd |= DCMD_INCSRCADDR | DCMD_FLOWTRG;
Lei Wenf8155a42011-02-28 10:32:11 +0800570 break;
571 case STATE_DMA_READING:
eric miaofe69af02008-02-14 15:48:23 +0800572 desc->dtadr = info->data_buff_phys;
Haojian Zhuang8638fac2009-09-10 14:11:44 +0800573 desc->dsadr = info->mmio_phys + NDDB;
eric miaofe69af02008-02-14 15:48:23 +0800574 desc->dcmd |= DCMD_INCTRGADDR | DCMD_FLOWSRC;
Lei Wenf8155a42011-02-28 10:32:11 +0800575 break;
576 default:
Lei Wenda675b42011-07-14 20:44:31 -0700577 dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__,
Lei Wenf8155a42011-02-28 10:32:11 +0800578 info->state);
579 BUG();
eric miaofe69af02008-02-14 15:48:23 +0800580 }
581
582 DRCMR(info->drcmr_dat) = DRCMR_MAPVLD | info->data_dma_ch;
583 DDADR(info->data_dma_ch) = info->data_desc_addr;
584 DCSR(info->data_dma_ch) |= DCSR_RUN;
585}
586
587static void pxa3xx_nand_data_dma_irq(int channel, void *data)
588{
589 struct pxa3xx_nand_info *info = data;
590 uint32_t dcsr;
591
592 dcsr = DCSR(channel);
593 DCSR(channel) = dcsr;
594
595 if (dcsr & DCSR_BUSERR) {
596 info->retcode = ERR_DMABUSERR;
eric miaofe69af02008-02-14 15:48:23 +0800597 }
598
Lei Wenf8155a42011-02-28 10:32:11 +0800599 info->state = STATE_DMA_DONE;
600 enable_int(info, NDCR_INT_MASK);
601 nand_writel(info, NDSR, NDSR_WRDREQ | NDSR_RDDREQ);
eric miaofe69af02008-02-14 15:48:23 +0800602}
Ezequiel Garciaf4db2e32013-08-12 14:14:56 -0300603#else
604static void start_data_dma(struct pxa3xx_nand_info *info)
605{}
606#endif
eric miaofe69af02008-02-14 15:48:23 +0800607
Robert Jarzmik24542252015-02-20 19:36:43 +0100608static irqreturn_t pxa3xx_nand_irq_thread(int irq, void *data)
609{
610 struct pxa3xx_nand_info *info = data;
611
612 handle_data_pio(info);
613
614 info->state = STATE_CMD_DONE;
615 nand_writel(info, NDSR, NDSR_WRDREQ | NDSR_RDDREQ);
616
617 return IRQ_HANDLED;
618}
619
eric miaofe69af02008-02-14 15:48:23 +0800620static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
621{
622 struct pxa3xx_nand_info *info = devid;
Ezequiel Garcia55d9fd62013-11-14 18:25:26 -0300623 unsigned int status, is_completed = 0, is_ready = 0;
Lei Wenf3c8cfc2011-07-14 20:44:33 -0700624 unsigned int ready, cmd_done;
Robert Jarzmik24542252015-02-20 19:36:43 +0100625 irqreturn_t ret = IRQ_HANDLED;
Lei Wenf3c8cfc2011-07-14 20:44:33 -0700626
627 if (info->cs == 0) {
628 ready = NDSR_FLASH_RDY;
629 cmd_done = NDSR_CS0_CMDD;
630 } else {
631 ready = NDSR_RDY;
632 cmd_done = NDSR_CS1_CMDD;
633 }
eric miaofe69af02008-02-14 15:48:23 +0800634
635 status = nand_readl(info, NDSR);
636
Ezequiel Garcia87f53362013-11-14 18:25:39 -0300637 if (status & NDSR_UNCORERR)
638 info->retcode = ERR_UNCORERR;
639 if (status & NDSR_CORERR) {
640 info->retcode = ERR_CORERR;
641 if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 &&
642 info->ecc_bch)
643 info->ecc_err_cnt = NDSR_ERR_CNT(status);
644 else
645 info->ecc_err_cnt = 1;
646
647 /*
648 * Each chunk composing a page is corrected independently,
649 * and we need to store maximum number of corrected bitflips
650 * to return it to the MTD layer in ecc.read_page().
651 */
652 info->max_bitflips = max_t(unsigned int,
653 info->max_bitflips,
654 info->ecc_err_cnt);
655 }
Lei Wenf8155a42011-02-28 10:32:11 +0800656 if (status & (NDSR_RDDREQ | NDSR_WRDREQ)) {
657 /* whether use dma to transfer data */
eric miaofe69af02008-02-14 15:48:23 +0800658 if (info->use_dma) {
Lei Wenf8155a42011-02-28 10:32:11 +0800659 disable_int(info, NDCR_INT_MASK);
660 info->state = (status & NDSR_RDDREQ) ?
661 STATE_DMA_READING : STATE_DMA_WRITING;
662 start_data_dma(info);
663 goto NORMAL_IRQ_EXIT;
eric miaofe69af02008-02-14 15:48:23 +0800664 } else {
Lei Wenf8155a42011-02-28 10:32:11 +0800665 info->state = (status & NDSR_RDDREQ) ?
666 STATE_PIO_READING : STATE_PIO_WRITING;
Robert Jarzmik24542252015-02-20 19:36:43 +0100667 ret = IRQ_WAKE_THREAD;
668 goto NORMAL_IRQ_EXIT;
eric miaofe69af02008-02-14 15:48:23 +0800669 }
Lei Wenf8155a42011-02-28 10:32:11 +0800670 }
Lei Wenf3c8cfc2011-07-14 20:44:33 -0700671 if (status & cmd_done) {
Lei Wenf8155a42011-02-28 10:32:11 +0800672 info->state = STATE_CMD_DONE;
673 is_completed = 1;
674 }
Lei Wenf3c8cfc2011-07-14 20:44:33 -0700675 if (status & ready) {
eric miaofe69af02008-02-14 15:48:23 +0800676 info->state = STATE_READY;
Ezequiel Garcia55d9fd62013-11-14 18:25:26 -0300677 is_ready = 1;
Lei Wen401e67e2011-02-28 10:32:14 +0800678 }
Lei Wenf8155a42011-02-28 10:32:11 +0800679
680 if (status & NDSR_WRCMDREQ) {
681 nand_writel(info, NDSR, NDSR_WRCMDREQ);
682 status &= ~NDSR_WRCMDREQ;
683 info->state = STATE_CMD_HANDLE;
Ezequiel Garcia3a1a3442013-08-12 14:14:50 -0300684
685 /*
686 * Command buffer registers NDCB{0-2} (and optionally NDCB3)
687 * must be loaded by writing directly either 12 or 16
688 * bytes directly to NDCB0, four bytes at a time.
689 *
690 * Direct write access to NDCB1, NDCB2 and NDCB3 is ignored
691 * but each NDCBx register can be read.
692 */
Lei Wenf8155a42011-02-28 10:32:11 +0800693 nand_writel(info, NDCB0, info->ndcb0);
694 nand_writel(info, NDCB0, info->ndcb1);
695 nand_writel(info, NDCB0, info->ndcb2);
Ezequiel Garcia3a1a3442013-08-12 14:14:50 -0300696
697 /* NDCB3 register is available in NFCv2 (Armada 370/XP SoC) */
698 if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)
699 nand_writel(info, NDCB0, info->ndcb3);
eric miaofe69af02008-02-14 15:48:23 +0800700 }
Lei Wenf8155a42011-02-28 10:32:11 +0800701
702 /* clear NDSR to let the controller exit the IRQ */
eric miaofe69af02008-02-14 15:48:23 +0800703 nand_writel(info, NDSR, status);
Lei Wenf8155a42011-02-28 10:32:11 +0800704 if (is_completed)
705 complete(&info->cmd_complete);
Ezequiel Garcia55d9fd62013-11-14 18:25:26 -0300706 if (is_ready)
707 complete(&info->dev_ready);
Lei Wenf8155a42011-02-28 10:32:11 +0800708NORMAL_IRQ_EXIT:
Robert Jarzmik24542252015-02-20 19:36:43 +0100709 return ret;
eric miaofe69af02008-02-14 15:48:23 +0800710}
711
eric miaofe69af02008-02-14 15:48:23 +0800712static inline int is_buf_blank(uint8_t *buf, size_t len)
713{
714 for (; len > 0; len--)
715 if (*buf++ != 0xff)
716 return 0;
717 return 1;
718}
719
Ezequiel Garcia86beeba2013-11-14 18:25:31 -0300720static void set_command_address(struct pxa3xx_nand_info *info,
721 unsigned int page_size, uint16_t column, int page_addr)
722{
723 /* small page addr setting */
724 if (page_size < PAGE_CHUNK_SIZE) {
725 info->ndcb1 = ((page_addr & 0xFFFFFF) << 8)
726 | (column & 0xFF);
727
728 info->ndcb2 = 0;
729 } else {
730 info->ndcb1 = ((page_addr & 0xFFFF) << 16)
731 | (column & 0xFFFF);
732
733 if (page_addr & 0xFF0000)
734 info->ndcb2 = (page_addr & 0xFF0000) >> 16;
735 else
736 info->ndcb2 = 0;
737 }
738}
739
Ezequiel Garciac39ff032013-11-14 18:25:33 -0300740static void prepare_start_command(struct pxa3xx_nand_info *info, int command)
Lei Wen4eb2da82011-02-28 10:32:13 +0800741{
Ezequiel Garcia39f83d12013-11-14 18:25:34 -0300742 struct pxa3xx_nand_host *host = info->host[info->cs];
743 struct mtd_info *mtd = host->mtd;
744
Lei Wen4eb2da82011-02-28 10:32:13 +0800745 /* reset data and oob column point to handle data */
Lei Wen401e67e2011-02-28 10:32:14 +0800746 info->buf_start = 0;
747 info->buf_count = 0;
Lei Wen4eb2da82011-02-28 10:32:13 +0800748 info->oob_size = 0;
Ezequiel Garciafa543be2013-11-14 18:25:36 -0300749 info->data_buff_pos = 0;
750 info->oob_buff_pos = 0;
Lei Wen4eb2da82011-02-28 10:32:13 +0800751 info->use_ecc = 0;
Ezequiel Garcia5bb653e2013-08-12 14:14:49 -0300752 info->use_spare = 1;
Lei Wen4eb2da82011-02-28 10:32:13 +0800753 info->retcode = ERR_NONE;
Ezequiel Garcia87f53362013-11-14 18:25:39 -0300754 info->ecc_err_cnt = 0;
Ezequiel Garciaf0e6a32e2013-11-14 18:25:30 -0300755 info->ndcb3 = 0;
Ezequiel Garciad20d0a62013-12-18 18:44:08 -0300756 info->need_wait = 0;
Lei Wen4eb2da82011-02-28 10:32:13 +0800757
758 switch (command) {
759 case NAND_CMD_READ0:
760 case NAND_CMD_PAGEPROG:
761 info->use_ecc = 1;
762 case NAND_CMD_READOOB:
Ezequiel Garciafa543be2013-11-14 18:25:36 -0300763 pxa3xx_set_datasize(info, mtd);
Lei Wen4eb2da82011-02-28 10:32:13 +0800764 break;
Ezequiel Garcia41a63432013-08-12 14:14:51 -0300765 case NAND_CMD_PARAM:
766 info->use_spare = 0;
767 break;
Lei Wen4eb2da82011-02-28 10:32:13 +0800768 default:
769 info->ndcb1 = 0;
770 info->ndcb2 = 0;
771 break;
772 }
Ezequiel Garcia39f83d12013-11-14 18:25:34 -0300773
774 /*
775 * If we are about to issue a read command, or about to set
776 * the write address, then clean the data buffer.
777 */
778 if (command == NAND_CMD_READ0 ||
779 command == NAND_CMD_READOOB ||
780 command == NAND_CMD_SEQIN) {
781
782 info->buf_count = mtd->writesize + mtd->oobsize;
783 memset(info->data_buff, 0xFF, info->buf_count);
784 }
785
Ezequiel Garciac39ff032013-11-14 18:25:33 -0300786}
787
788static int prepare_set_command(struct pxa3xx_nand_info *info, int command,
Ezequiel Garcia70ed8522013-11-14 18:25:37 -0300789 int ext_cmd_type, uint16_t column, int page_addr)
Ezequiel Garciac39ff032013-11-14 18:25:33 -0300790{
791 int addr_cycle, exec_cmd;
792 struct pxa3xx_nand_host *host;
793 struct mtd_info *mtd;
794
795 host = info->host[info->cs];
796 mtd = host->mtd;
797 addr_cycle = 0;
798 exec_cmd = 1;
799
800 if (info->cs != 0)
801 info->ndcb0 = NDCB0_CSEL;
802 else
803 info->ndcb0 = 0;
804
805 if (command == NAND_CMD_SEQIN)
806 exec_cmd = 0;
Lei Wen4eb2da82011-02-28 10:32:13 +0800807
Lei Wend4568822011-07-14 20:44:32 -0700808 addr_cycle = NDCB0_ADDR_CYC(host->row_addr_cycles
809 + host->col_addr_cycles);
Lei Wen4eb2da82011-02-28 10:32:13 +0800810
811 switch (command) {
812 case NAND_CMD_READOOB:
813 case NAND_CMD_READ0:
Ezequiel Garciaec821352013-08-12 14:14:54 -0300814 info->buf_start = column;
815 info->ndcb0 |= NDCB0_CMD_TYPE(0)
816 | addr_cycle
817 | NAND_CMD_READ0;
Lei Wen4eb2da82011-02-28 10:32:13 +0800818
Ezequiel Garciaec821352013-08-12 14:14:54 -0300819 if (command == NAND_CMD_READOOB)
820 info->buf_start += mtd->writesize;
821
Ezequiel Garcia70ed8522013-11-14 18:25:37 -0300822 /*
823 * Multiple page read needs an 'extended command type' field,
824 * which is either naked-read or last-read according to the
825 * state.
826 */
827 if (mtd->writesize == PAGE_CHUNK_SIZE) {
Ezequiel Garciaec821352013-08-12 14:14:54 -0300828 info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8);
Ezequiel Garcia70ed8522013-11-14 18:25:37 -0300829 } else if (mtd->writesize > PAGE_CHUNK_SIZE) {
830 info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8)
831 | NDCB0_LEN_OVRD
832 | NDCB0_EXT_CMD_TYPE(ext_cmd_type);
833 info->ndcb3 = info->chunk_size +
834 info->oob_size;
835 }
Lei Wen4eb2da82011-02-28 10:32:13 +0800836
Ezequiel Garcia01d99472013-11-14 18:25:32 -0300837 set_command_address(info, mtd->writesize, column, page_addr);
Ezequiel Garcia01d99472013-11-14 18:25:32 -0300838 break;
839
Lei Wen4eb2da82011-02-28 10:32:13 +0800840 case NAND_CMD_SEQIN:
Lei Wen4eb2da82011-02-28 10:32:13 +0800841
Ezequiel Garciae7f9a6a2013-11-14 18:25:35 -0300842 info->buf_start = column;
843 set_command_address(info, mtd->writesize, 0, page_addr);
Ezequiel Garcia535cb572013-11-14 18:25:38 -0300844
845 /*
846 * Multiple page programming needs to execute the initial
847 * SEQIN command that sets the page address.
848 */
849 if (mtd->writesize > PAGE_CHUNK_SIZE) {
850 info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
851 | NDCB0_EXT_CMD_TYPE(ext_cmd_type)
852 | addr_cycle
853 | command;
854 /* No data transfer in this case */
855 info->data_size = 0;
856 exec_cmd = 1;
857 }
Lei Wen4eb2da82011-02-28 10:32:13 +0800858 break;
859
860 case NAND_CMD_PAGEPROG:
861 if (is_buf_blank(info->data_buff,
862 (mtd->writesize + mtd->oobsize))) {
863 exec_cmd = 0;
864 break;
865 }
866
Ezequiel Garcia535cb572013-11-14 18:25:38 -0300867 /* Second command setting for large pages */
868 if (mtd->writesize > PAGE_CHUNK_SIZE) {
869 /*
870 * Multiple page write uses the 'extended command'
871 * field. This can be used to issue a command dispatch
872 * or a naked-write depending on the current stage.
873 */
874 info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
875 | NDCB0_LEN_OVRD
876 | NDCB0_EXT_CMD_TYPE(ext_cmd_type);
877 info->ndcb3 = info->chunk_size +
878 info->oob_size;
879
880 /*
881 * This is the command dispatch that completes a chunked
882 * page program operation.
883 */
884 if (info->data_size == 0) {
885 info->ndcb0 = NDCB0_CMD_TYPE(0x1)
886 | NDCB0_EXT_CMD_TYPE(ext_cmd_type)
887 | command;
888 info->ndcb1 = 0;
889 info->ndcb2 = 0;
890 info->ndcb3 = 0;
891 }
892 } else {
893 info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
894 | NDCB0_AUTO_RS
895 | NDCB0_ST_ROW_EN
896 | NDCB0_DBC
897 | (NAND_CMD_PAGEPROG << 8)
898 | NAND_CMD_SEQIN
899 | addr_cycle;
900 }
Lei Wen4eb2da82011-02-28 10:32:13 +0800901 break;
902
Ezequiel Garciace0268f2013-05-14 08:15:25 -0300903 case NAND_CMD_PARAM:
Ezequiel Garciace0268f2013-05-14 08:15:25 -0300904 info->buf_count = 256;
905 info->ndcb0 |= NDCB0_CMD_TYPE(0)
906 | NDCB0_ADDR_CYC(1)
Ezequiel Garcia41a63432013-08-12 14:14:51 -0300907 | NDCB0_LEN_OVRD
Ezequiel Garciaec821352013-08-12 14:14:54 -0300908 | command;
Ezequiel Garciace0268f2013-05-14 08:15:25 -0300909 info->ndcb1 = (column & 0xFF);
Ezequiel Garcia41a63432013-08-12 14:14:51 -0300910 info->ndcb3 = 256;
Ezequiel Garciace0268f2013-05-14 08:15:25 -0300911 info->data_size = 256;
912 break;
913
Lei Wen4eb2da82011-02-28 10:32:13 +0800914 case NAND_CMD_READID:
Lei Wend4568822011-07-14 20:44:32 -0700915 info->buf_count = host->read_id_bytes;
Lei Wen4eb2da82011-02-28 10:32:13 +0800916 info->ndcb0 |= NDCB0_CMD_TYPE(3)
917 | NDCB0_ADDR_CYC(1)
Ezequiel Garciaec821352013-08-12 14:14:54 -0300918 | command;
Ezequiel Garciad14231f2013-05-14 08:15:24 -0300919 info->ndcb1 = (column & 0xFF);
Lei Wen4eb2da82011-02-28 10:32:13 +0800920
921 info->data_size = 8;
922 break;
923 case NAND_CMD_STATUS:
Lei Wen4eb2da82011-02-28 10:32:13 +0800924 info->buf_count = 1;
925 info->ndcb0 |= NDCB0_CMD_TYPE(4)
926 | NDCB0_ADDR_CYC(1)
Ezequiel Garciaec821352013-08-12 14:14:54 -0300927 | command;
Lei Wen4eb2da82011-02-28 10:32:13 +0800928
929 info->data_size = 8;
930 break;
931
932 case NAND_CMD_ERASE1:
Lei Wen4eb2da82011-02-28 10:32:13 +0800933 info->ndcb0 |= NDCB0_CMD_TYPE(2)
934 | NDCB0_AUTO_RS
935 | NDCB0_ADDR_CYC(3)
936 | NDCB0_DBC
Ezequiel Garciaec821352013-08-12 14:14:54 -0300937 | (NAND_CMD_ERASE2 << 8)
938 | NAND_CMD_ERASE1;
Lei Wen4eb2da82011-02-28 10:32:13 +0800939 info->ndcb1 = page_addr;
940 info->ndcb2 = 0;
941
942 break;
943 case NAND_CMD_RESET:
Lei Wen4eb2da82011-02-28 10:32:13 +0800944 info->ndcb0 |= NDCB0_CMD_TYPE(5)
Ezequiel Garciaec821352013-08-12 14:14:54 -0300945 | command;
Lei Wen4eb2da82011-02-28 10:32:13 +0800946
947 break;
948
949 case NAND_CMD_ERASE2:
950 exec_cmd = 0;
951 break;
952
953 default:
954 exec_cmd = 0;
Lei Wenda675b42011-07-14 20:44:31 -0700955 dev_err(&info->pdev->dev, "non-supported command %x\n",
956 command);
Lei Wen4eb2da82011-02-28 10:32:13 +0800957 break;
958 }
959
960 return exec_cmd;
961}
962
Ezequiel Garcia5cbbdc62013-12-18 18:44:09 -0300963static void nand_cmdfunc(struct mtd_info *mtd, unsigned command,
964 int column, int page_addr)
eric miaofe69af02008-02-14 15:48:23 +0800965{
Lei Wend4568822011-07-14 20:44:32 -0700966 struct pxa3xx_nand_host *host = mtd->priv;
967 struct pxa3xx_nand_info *info = host->info_data;
Nicholas Mc Guiree5860c12015-02-01 11:55:37 -0500968 int exec_cmd;
eric miaofe69af02008-02-14 15:48:23 +0800969
Lei Wen4eb2da82011-02-28 10:32:13 +0800970 /*
971 * if this is a x16 device ,then convert the input
972 * "byte" address into a "word" address appropriate
973 * for indexing a word-oriented device
974 */
Ezequiel Garcia48cf7ef2013-08-12 14:14:55 -0300975 if (info->reg_ndcr & NDCR_DWIDTH_M)
Lei Wen4eb2da82011-02-28 10:32:13 +0800976 column /= 2;
eric miaofe69af02008-02-14 15:48:23 +0800977
Lei Wenf3c8cfc2011-07-14 20:44:33 -0700978 /*
979 * There may be different NAND chip hooked to
980 * different chip select, so check whether
981 * chip select has been changed, if yes, reset the timing
982 */
983 if (info->cs != host->cs) {
984 info->cs = host->cs;
Ezequiel Garcia48cf7ef2013-08-12 14:14:55 -0300985 nand_writel(info, NDTR0CS0, info->ndtr0cs0);
986 nand_writel(info, NDTR1CS0, info->ndtr1cs0);
Lei Wenf3c8cfc2011-07-14 20:44:33 -0700987 }
988
Ezequiel Garciac39ff032013-11-14 18:25:33 -0300989 prepare_start_command(info, command);
990
Lei Wend4568822011-07-14 20:44:32 -0700991 info->state = STATE_PREPARED;
Ezequiel Garcia70ed8522013-11-14 18:25:37 -0300992 exec_cmd = prepare_set_command(info, command, 0, column, page_addr);
993
Lei Wenf8155a42011-02-28 10:32:11 +0800994 if (exec_cmd) {
995 init_completion(&info->cmd_complete);
Ezequiel Garcia55d9fd62013-11-14 18:25:26 -0300996 init_completion(&info->dev_ready);
997 info->need_wait = 1;
Lei Wenf8155a42011-02-28 10:32:11 +0800998 pxa3xx_nand_start(info);
999
Nicholas Mc Guiree5860c12015-02-01 11:55:37 -05001000 if (!wait_for_completion_timeout(&info->cmd_complete,
1001 CHIP_DELAY_TIMEOUT)) {
Lei Wenda675b42011-07-14 20:44:31 -07001002 dev_err(&info->pdev->dev, "Wait time out!!!\n");
Lei Wenf8155a42011-02-28 10:32:11 +08001003 /* Stop State Machine for next command cycle */
1004 pxa3xx_nand_stop(info);
1005 }
eric miaofe69af02008-02-14 15:48:23 +08001006 }
Lei Wend4568822011-07-14 20:44:32 -07001007 info->state = STATE_IDLE;
eric miaofe69af02008-02-14 15:48:23 +08001008}
1009
Ezequiel Garcia5cbbdc62013-12-18 18:44:09 -03001010static void nand_cmdfunc_extended(struct mtd_info *mtd,
1011 const unsigned command,
1012 int column, int page_addr)
Ezequiel Garcia70ed8522013-11-14 18:25:37 -03001013{
1014 struct pxa3xx_nand_host *host = mtd->priv;
1015 struct pxa3xx_nand_info *info = host->info_data;
Nicholas Mc Guiree5860c12015-02-01 11:55:37 -05001016 int exec_cmd, ext_cmd_type;
Ezequiel Garcia70ed8522013-11-14 18:25:37 -03001017
1018 /*
1019 * if this is a x16 device then convert the input
1020 * "byte" address into a "word" address appropriate
1021 * for indexing a word-oriented device
1022 */
1023 if (info->reg_ndcr & NDCR_DWIDTH_M)
1024 column /= 2;
1025
1026 /*
1027 * There may be different NAND chip hooked to
1028 * different chip select, so check whether
1029 * chip select has been changed, if yes, reset the timing
1030 */
1031 if (info->cs != host->cs) {
1032 info->cs = host->cs;
1033 nand_writel(info, NDTR0CS0, info->ndtr0cs0);
1034 nand_writel(info, NDTR1CS0, info->ndtr1cs0);
1035 }
1036
1037 /* Select the extended command for the first command */
1038 switch (command) {
1039 case NAND_CMD_READ0:
1040 case NAND_CMD_READOOB:
1041 ext_cmd_type = EXT_CMD_TYPE_MONO;
1042 break;
Ezequiel Garcia535cb572013-11-14 18:25:38 -03001043 case NAND_CMD_SEQIN:
1044 ext_cmd_type = EXT_CMD_TYPE_DISPATCH;
1045 break;
1046 case NAND_CMD_PAGEPROG:
1047 ext_cmd_type = EXT_CMD_TYPE_NAKED_RW;
1048 break;
Ezequiel Garcia70ed8522013-11-14 18:25:37 -03001049 default:
1050 ext_cmd_type = 0;
Ezequiel Garcia535cb572013-11-14 18:25:38 -03001051 break;
Ezequiel Garcia70ed8522013-11-14 18:25:37 -03001052 }
1053
1054 prepare_start_command(info, command);
1055
1056 /*
1057 * Prepare the "is ready" completion before starting a command
1058 * transaction sequence. If the command is not executed the
1059 * completion will be completed, see below.
1060 *
1061 * We can do that inside the loop because the command variable
1062 * is invariant and thus so is the exec_cmd.
1063 */
1064 info->need_wait = 1;
1065 init_completion(&info->dev_ready);
1066 do {
1067 info->state = STATE_PREPARED;
1068 exec_cmd = prepare_set_command(info, command, ext_cmd_type,
1069 column, page_addr);
1070 if (!exec_cmd) {
1071 info->need_wait = 0;
1072 complete(&info->dev_ready);
1073 break;
1074 }
1075
1076 init_completion(&info->cmd_complete);
1077 pxa3xx_nand_start(info);
1078
Nicholas Mc Guiree5860c12015-02-01 11:55:37 -05001079 if (!wait_for_completion_timeout(&info->cmd_complete,
1080 CHIP_DELAY_TIMEOUT)) {
Ezequiel Garcia70ed8522013-11-14 18:25:37 -03001081 dev_err(&info->pdev->dev, "Wait time out!!!\n");
1082 /* Stop State Machine for next command cycle */
1083 pxa3xx_nand_stop(info);
1084 break;
1085 }
1086
1087 /* Check if the sequence is complete */
Ezequiel Garcia535cb572013-11-14 18:25:38 -03001088 if (info->data_size == 0 && command != NAND_CMD_PAGEPROG)
1089 break;
1090
1091 /*
1092 * After a splitted program command sequence has issued
1093 * the command dispatch, the command sequence is complete.
1094 */
1095 if (info->data_size == 0 &&
1096 command == NAND_CMD_PAGEPROG &&
1097 ext_cmd_type == EXT_CMD_TYPE_DISPATCH)
Ezequiel Garcia70ed8522013-11-14 18:25:37 -03001098 break;
1099
1100 if (command == NAND_CMD_READ0 || command == NAND_CMD_READOOB) {
1101 /* Last read: issue a 'last naked read' */
1102 if (info->data_size == info->chunk_size)
1103 ext_cmd_type = EXT_CMD_TYPE_LAST_RW;
1104 else
1105 ext_cmd_type = EXT_CMD_TYPE_NAKED_RW;
Ezequiel Garcia535cb572013-11-14 18:25:38 -03001106
1107 /*
1108 * If a splitted program command has no more data to transfer,
1109 * the command dispatch must be issued to complete.
1110 */
1111 } else if (command == NAND_CMD_PAGEPROG &&
1112 info->data_size == 0) {
1113 ext_cmd_type = EXT_CMD_TYPE_DISPATCH;
Ezequiel Garcia70ed8522013-11-14 18:25:37 -03001114 }
1115 } while (1);
1116
1117 info->state = STATE_IDLE;
1118}
1119
Josh Wufdbad98d2012-06-25 18:07:45 +08001120static int pxa3xx_nand_write_page_hwecc(struct mtd_info *mtd,
Brian Norris1fbb9382012-05-02 10:14:55 -07001121 struct nand_chip *chip, const uint8_t *buf, int oob_required)
Lei Wenf8155a42011-02-28 10:32:11 +08001122{
1123 chip->write_buf(mtd, buf, mtd->writesize);
1124 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
Josh Wufdbad98d2012-06-25 18:07:45 +08001125
1126 return 0;
Lei Wenf8155a42011-02-28 10:32:11 +08001127}
1128
1129static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd,
Brian Norris1fbb9382012-05-02 10:14:55 -07001130 struct nand_chip *chip, uint8_t *buf, int oob_required,
1131 int page)
Lei Wenf8155a42011-02-28 10:32:11 +08001132{
Lei Wend4568822011-07-14 20:44:32 -07001133 struct pxa3xx_nand_host *host = mtd->priv;
1134 struct pxa3xx_nand_info *info = host->info_data;
Lei Wenf8155a42011-02-28 10:32:11 +08001135
1136 chip->read_buf(mtd, buf, mtd->writesize);
1137 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1138
Ezequiel Garcia87f53362013-11-14 18:25:39 -03001139 if (info->retcode == ERR_CORERR && info->use_ecc) {
1140 mtd->ecc_stats.corrected += info->ecc_err_cnt;
1141
1142 } else if (info->retcode == ERR_UNCORERR) {
Lei Wenf8155a42011-02-28 10:32:11 +08001143 /*
1144 * for blank page (all 0xff), HW will calculate its ECC as
1145 * 0, which is different from the ECC information within
Ezequiel Garcia87f53362013-11-14 18:25:39 -03001146 * OOB, ignore such uncorrectable errors
Lei Wenf8155a42011-02-28 10:32:11 +08001147 */
1148 if (is_buf_blank(buf, mtd->writesize))
Daniel Mack543e32d2011-06-07 03:01:07 -07001149 info->retcode = ERR_NONE;
1150 else
Lei Wenf8155a42011-02-28 10:32:11 +08001151 mtd->ecc_stats.failed++;
1152 }
1153
Ezequiel Garcia87f53362013-11-14 18:25:39 -03001154 return info->max_bitflips;
Lei Wenf8155a42011-02-28 10:32:11 +08001155}
1156
eric miaofe69af02008-02-14 15:48:23 +08001157static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd)
1158{
Lei Wend4568822011-07-14 20:44:32 -07001159 struct pxa3xx_nand_host *host = mtd->priv;
1160 struct pxa3xx_nand_info *info = host->info_data;
eric miaofe69af02008-02-14 15:48:23 +08001161 char retval = 0xFF;
1162
1163 if (info->buf_start < info->buf_count)
1164 /* Has just send a new command? */
1165 retval = info->data_buff[info->buf_start++];
1166
1167 return retval;
1168}
1169
1170static u16 pxa3xx_nand_read_word(struct mtd_info *mtd)
1171{
Lei Wend4568822011-07-14 20:44:32 -07001172 struct pxa3xx_nand_host *host = mtd->priv;
1173 struct pxa3xx_nand_info *info = host->info_data;
eric miaofe69af02008-02-14 15:48:23 +08001174 u16 retval = 0xFFFF;
1175
1176 if (!(info->buf_start & 0x01) && info->buf_start < info->buf_count) {
1177 retval = *((u16 *)(info->data_buff+info->buf_start));
1178 info->buf_start += 2;
1179 }
1180 return retval;
1181}
1182
1183static void pxa3xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1184{
Lei Wend4568822011-07-14 20:44:32 -07001185 struct pxa3xx_nand_host *host = mtd->priv;
1186 struct pxa3xx_nand_info *info = host->info_data;
eric miaofe69af02008-02-14 15:48:23 +08001187 int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
1188
1189 memcpy(buf, info->data_buff + info->buf_start, real_len);
1190 info->buf_start += real_len;
1191}
1192
1193static void pxa3xx_nand_write_buf(struct mtd_info *mtd,
1194 const uint8_t *buf, int len)
1195{
Lei Wend4568822011-07-14 20:44:32 -07001196 struct pxa3xx_nand_host *host = mtd->priv;
1197 struct pxa3xx_nand_info *info = host->info_data;
eric miaofe69af02008-02-14 15:48:23 +08001198 int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
1199
1200 memcpy(info->data_buff + info->buf_start, buf, real_len);
1201 info->buf_start += real_len;
1202}
1203
eric miaofe69af02008-02-14 15:48:23 +08001204static void pxa3xx_nand_select_chip(struct mtd_info *mtd, int chip)
1205{
1206 return;
1207}
1208
1209static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
1210{
Lei Wend4568822011-07-14 20:44:32 -07001211 struct pxa3xx_nand_host *host = mtd->priv;
1212 struct pxa3xx_nand_info *info = host->info_data;
Ezequiel Garcia55d9fd62013-11-14 18:25:26 -03001213
1214 if (info->need_wait) {
Ezequiel Garcia55d9fd62013-11-14 18:25:26 -03001215 info->need_wait = 0;
Nicholas Mc Guiree5860c12015-02-01 11:55:37 -05001216 if (!wait_for_completion_timeout(&info->dev_ready,
1217 CHIP_DELAY_TIMEOUT)) {
Ezequiel Garcia55d9fd62013-11-14 18:25:26 -03001218 dev_err(&info->pdev->dev, "Ready time out!!!\n");
1219 return NAND_STATUS_FAIL;
1220 }
1221 }
eric miaofe69af02008-02-14 15:48:23 +08001222
1223 /* pxa3xx_nand_send_command has waited for command complete */
1224 if (this->state == FL_WRITING || this->state == FL_ERASING) {
1225 if (info->retcode == ERR_NONE)
1226 return 0;
Ezequiel Garcia55d9fd62013-11-14 18:25:26 -03001227 else
1228 return NAND_STATUS_FAIL;
eric miaofe69af02008-02-14 15:48:23 +08001229 }
1230
Ezequiel Garcia55d9fd62013-11-14 18:25:26 -03001231 return NAND_STATUS_READY;
eric miaofe69af02008-02-14 15:48:23 +08001232}
1233
eric miaofe69af02008-02-14 15:48:23 +08001234static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info,
Enrico Scholzc8c17c82008-08-29 12:59:51 +02001235 const struct pxa3xx_nand_flash *f)
eric miaofe69af02008-02-14 15:48:23 +08001236{
1237 struct platform_device *pdev = info->pdev;
Jingoo Han453810b2013-07-30 17:18:33 +09001238 struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
Lei Wenf3c8cfc2011-07-14 20:44:33 -07001239 struct pxa3xx_nand_host *host = info->host[info->cs];
Lei Wenf8155a42011-02-28 10:32:11 +08001240 uint32_t ndcr = 0x0; /* enable all interrupts */
eric miaofe69af02008-02-14 15:48:23 +08001241
Lei Wenda675b42011-07-14 20:44:31 -07001242 if (f->page_size != 2048 && f->page_size != 512) {
1243 dev_err(&pdev->dev, "Current only support 2048 and 512 size\n");
eric miaofe69af02008-02-14 15:48:23 +08001244 return -EINVAL;
Lei Wenda675b42011-07-14 20:44:31 -07001245 }
eric miaofe69af02008-02-14 15:48:23 +08001246
Lei Wenda675b42011-07-14 20:44:31 -07001247 if (f->flash_width != 16 && f->flash_width != 8) {
1248 dev_err(&pdev->dev, "Only support 8bit and 16 bit!\n");
eric miaofe69af02008-02-14 15:48:23 +08001249 return -EINVAL;
Lei Wenda675b42011-07-14 20:44:31 -07001250 }
eric miaofe69af02008-02-14 15:48:23 +08001251
1252 /* calculate flash information */
Lei Wend4568822011-07-14 20:44:32 -07001253 host->read_id_bytes = (f->page_size == 2048) ? 4 : 2;
eric miaofe69af02008-02-14 15:48:23 +08001254
1255 /* calculate addressing information */
Lei Wend4568822011-07-14 20:44:32 -07001256 host->col_addr_cycles = (f->page_size == 2048) ? 2 : 1;
eric miaofe69af02008-02-14 15:48:23 +08001257
1258 if (f->num_blocks * f->page_per_block > 65536)
Lei Wend4568822011-07-14 20:44:32 -07001259 host->row_addr_cycles = 3;
eric miaofe69af02008-02-14 15:48:23 +08001260 else
Lei Wend4568822011-07-14 20:44:32 -07001261 host->row_addr_cycles = 2;
eric miaofe69af02008-02-14 15:48:23 +08001262
1263 ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
Lei Wend4568822011-07-14 20:44:32 -07001264 ndcr |= (host->col_addr_cycles == 2) ? NDCR_RA_START : 0;
eric miaofe69af02008-02-14 15:48:23 +08001265 ndcr |= (f->page_per_block == 64) ? NDCR_PG_PER_BLK : 0;
1266 ndcr |= (f->page_size == 2048) ? NDCR_PAGE_SZ : 0;
1267 ndcr |= (f->flash_width == 16) ? NDCR_DWIDTH_M : 0;
1268 ndcr |= (f->dfc_width == 16) ? NDCR_DWIDTH_C : 0;
1269
Lei Wend4568822011-07-14 20:44:32 -07001270 ndcr |= NDCR_RD_ID_CNT(host->read_id_bytes);
eric miaofe69af02008-02-14 15:48:23 +08001271 ndcr |= NDCR_SPARE_EN; /* enable spare by default */
1272
Ezequiel Garcia48cf7ef2013-08-12 14:14:55 -03001273 info->reg_ndcr = ndcr;
eric miaofe69af02008-02-14 15:48:23 +08001274
Lei Wend4568822011-07-14 20:44:32 -07001275 pxa3xx_nand_set_timing(host, f->timing);
eric miaofe69af02008-02-14 15:48:23 +08001276 return 0;
1277}
1278
Mike Rapoportf2710492009-02-17 13:54:47 +02001279static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
1280{
Lei Wenf3c8cfc2011-07-14 20:44:33 -07001281 /*
1282 * We set 0 by hard coding here, for we don't support keep_config
1283 * when there is more than one chip attached to the controller
1284 */
1285 struct pxa3xx_nand_host *host = info->host[0];
Mike Rapoportf2710492009-02-17 13:54:47 +02001286 uint32_t ndcr = nand_readl(info, NDCR);
Mike Rapoportf2710492009-02-17 13:54:47 +02001287
Lei Wend4568822011-07-14 20:44:32 -07001288 if (ndcr & NDCR_PAGE_SZ) {
Ezequiel Garcia2128b082013-11-07 12:17:16 -03001289 /* Controller's FIFO size */
Ezequiel Garcia70ed8522013-11-14 18:25:37 -03001290 info->chunk_size = 2048;
Lei Wend4568822011-07-14 20:44:32 -07001291 host->read_id_bytes = 4;
1292 } else {
Ezequiel Garcia70ed8522013-11-14 18:25:37 -03001293 info->chunk_size = 512;
Lei Wend4568822011-07-14 20:44:32 -07001294 host->read_id_bytes = 2;
1295 }
1296
Ezequiel Garcia70ed8522013-11-14 18:25:37 -03001297 /* Set an initial chunk size */
Ezequiel Garcia48cf7ef2013-08-12 14:14:55 -03001298 info->reg_ndcr = ndcr & ~NDCR_INT_MASK;
1299 info->ndtr0cs0 = nand_readl(info, NDTR0CS0);
1300 info->ndtr1cs0 = nand_readl(info, NDTR1CS0);
Mike Rapoportf2710492009-02-17 13:54:47 +02001301 return 0;
1302}
1303
Ezequiel Garciaf4db2e32013-08-12 14:14:56 -03001304#ifdef ARCH_HAS_DMA
eric miaofe69af02008-02-14 15:48:23 +08001305static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info)
1306{
1307 struct platform_device *pdev = info->pdev;
Ezequiel Garcia62e8b852013-10-04 15:30:38 -03001308 int data_desc_offset = info->buf_size - sizeof(struct pxa_dma_desc);
eric miaofe69af02008-02-14 15:48:23 +08001309
1310 if (use_dma == 0) {
Ezequiel Garcia62e8b852013-10-04 15:30:38 -03001311 info->data_buff = kmalloc(info->buf_size, GFP_KERNEL);
eric miaofe69af02008-02-14 15:48:23 +08001312 if (info->data_buff == NULL)
1313 return -ENOMEM;
1314 return 0;
1315 }
1316
Ezequiel Garcia62e8b852013-10-04 15:30:38 -03001317 info->data_buff = dma_alloc_coherent(&pdev->dev, info->buf_size,
eric miaofe69af02008-02-14 15:48:23 +08001318 &info->data_buff_phys, GFP_KERNEL);
1319 if (info->data_buff == NULL) {
1320 dev_err(&pdev->dev, "failed to allocate dma buffer\n");
1321 return -ENOMEM;
1322 }
1323
eric miaofe69af02008-02-14 15:48:23 +08001324 info->data_desc = (void *)info->data_buff + data_desc_offset;
1325 info->data_desc_addr = info->data_buff_phys + data_desc_offset;
1326
1327 info->data_dma_ch = pxa_request_dma("nand-data", DMA_PRIO_LOW,
1328 pxa3xx_nand_data_dma_irq, info);
1329 if (info->data_dma_ch < 0) {
1330 dev_err(&pdev->dev, "failed to request data dma\n");
Ezequiel Garcia62e8b852013-10-04 15:30:38 -03001331 dma_free_coherent(&pdev->dev, info->buf_size,
eric miaofe69af02008-02-14 15:48:23 +08001332 info->data_buff, info->data_buff_phys);
1333 return info->data_dma_ch;
1334 }
1335
Ezequiel Garcia95b26562013-10-04 15:30:37 -03001336 /*
1337 * Now that DMA buffers are allocated we turn on
1338 * DMA proper for I/O operations.
1339 */
1340 info->use_dma = 1;
eric miaofe69af02008-02-14 15:48:23 +08001341 return 0;
1342}
1343
Ezequiel Garcia498b6142013-04-17 13:38:14 -03001344static void pxa3xx_nand_free_buff(struct pxa3xx_nand_info *info)
1345{
1346 struct platform_device *pdev = info->pdev;
Ezequiel Garcia15b540c2013-12-10 09:57:15 -03001347 if (info->use_dma) {
Ezequiel Garcia498b6142013-04-17 13:38:14 -03001348 pxa_free_dma(info->data_dma_ch);
Ezequiel Garcia62e8b852013-10-04 15:30:38 -03001349 dma_free_coherent(&pdev->dev, info->buf_size,
Ezequiel Garcia498b6142013-04-17 13:38:14 -03001350 info->data_buff, info->data_buff_phys);
1351 } else {
1352 kfree(info->data_buff);
1353 }
1354}
Ezequiel Garciaf4db2e32013-08-12 14:14:56 -03001355#else
1356static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info)
1357{
Ezequiel Garcia62e8b852013-10-04 15:30:38 -03001358 info->data_buff = kmalloc(info->buf_size, GFP_KERNEL);
Ezequiel Garciaf4db2e32013-08-12 14:14:56 -03001359 if (info->data_buff == NULL)
1360 return -ENOMEM;
1361 return 0;
1362}
1363
1364static void pxa3xx_nand_free_buff(struct pxa3xx_nand_info *info)
1365{
1366 kfree(info->data_buff);
1367}
1368#endif
Ezequiel Garcia498b6142013-04-17 13:38:14 -03001369
Lei Wen401e67e2011-02-28 10:32:14 +08001370static int pxa3xx_nand_sensing(struct pxa3xx_nand_info *info)
eric miaofe69af02008-02-14 15:48:23 +08001371{
Lei Wenf3c8cfc2011-07-14 20:44:33 -07001372 struct mtd_info *mtd;
Ezequiel Garcia2d79ab12013-11-07 12:17:15 -03001373 struct nand_chip *chip;
Lei Wend4568822011-07-14 20:44:32 -07001374 int ret;
Ezequiel Garcia2d79ab12013-11-07 12:17:15 -03001375
Lei Wenf3c8cfc2011-07-14 20:44:33 -07001376 mtd = info->host[info->cs]->mtd;
Ezequiel Garcia2d79ab12013-11-07 12:17:15 -03001377 chip = mtd->priv;
1378
Lei Wen401e67e2011-02-28 10:32:14 +08001379 /* use the common timing to make a try */
Lei Wend4568822011-07-14 20:44:32 -07001380 ret = pxa3xx_nand_config_flash(info, &builtin_flash_types[0]);
1381 if (ret)
1382 return ret;
1383
Ezequiel Garcia2d79ab12013-11-07 12:17:15 -03001384 chip->cmdfunc(mtd, NAND_CMD_RESET, 0, 0);
Ezequiel Garcia56704d82013-11-14 18:25:27 -03001385 ret = chip->waitfunc(mtd, chip);
1386 if (ret & NAND_STATUS_FAIL)
1387 return -ENODEV;
Lei Wend4568822011-07-14 20:44:32 -07001388
Ezequiel Garcia56704d82013-11-14 18:25:27 -03001389 return 0;
Lei Wen401e67e2011-02-28 10:32:14 +08001390}
eric miaofe69af02008-02-14 15:48:23 +08001391
Ezequiel Garcia43bcfd22013-11-14 18:25:29 -03001392static int pxa_ecc_init(struct pxa3xx_nand_info *info,
1393 struct nand_ecc_ctrl *ecc,
Ezequiel Garcia30b2afc2013-12-18 18:44:10 -03001394 int strength, int ecc_stepsize, int page_size)
Ezequiel Garcia43bcfd22013-11-14 18:25:29 -03001395{
Ezequiel Garcia30b2afc2013-12-18 18:44:10 -03001396 if (strength == 1 && ecc_stepsize == 512 && page_size == 2048) {
Ezequiel Garcia70ed8522013-11-14 18:25:37 -03001397 info->chunk_size = 2048;
Ezequiel Garcia43bcfd22013-11-14 18:25:29 -03001398 info->spare_size = 40;
1399 info->ecc_size = 24;
1400 ecc->mode = NAND_ECC_HW;
1401 ecc->size = 512;
1402 ecc->strength = 1;
Ezequiel Garcia43bcfd22013-11-14 18:25:29 -03001403
Ezequiel Garcia30b2afc2013-12-18 18:44:10 -03001404 } else if (strength == 1 && ecc_stepsize == 512 && page_size == 512) {
Ezequiel Garcia70ed8522013-11-14 18:25:37 -03001405 info->chunk_size = 512;
Ezequiel Garcia43bcfd22013-11-14 18:25:29 -03001406 info->spare_size = 8;
1407 info->ecc_size = 8;
1408 ecc->mode = NAND_ECC_HW;
1409 ecc->size = 512;
1410 ecc->strength = 1;
Ezequiel Garcia43bcfd22013-11-14 18:25:29 -03001411
Brian Norris6033a942013-11-14 14:41:32 -08001412 /*
1413 * Required ECC: 4-bit correction per 512 bytes
1414 * Select: 16-bit correction per 2048 bytes
1415 */
Rodolfo Giometti3db227b2014-01-13 15:35:38 +01001416 } else if (strength == 4 && ecc_stepsize == 512 && page_size == 2048) {
1417 info->ecc_bch = 1;
1418 info->chunk_size = 2048;
1419 info->spare_size = 32;
1420 info->ecc_size = 32;
1421 ecc->mode = NAND_ECC_HW;
1422 ecc->size = info->chunk_size;
1423 ecc->layout = &ecc_layout_2KB_bch4bit;
1424 ecc->strength = 16;
Rodolfo Giometti3db227b2014-01-13 15:35:38 +01001425
Ezequiel Garcia30b2afc2013-12-18 18:44:10 -03001426 } else if (strength == 4 && ecc_stepsize == 512 && page_size == 4096) {
Ezequiel Garcia70ed8522013-11-14 18:25:37 -03001427 info->ecc_bch = 1;
1428 info->chunk_size = 2048;
1429 info->spare_size = 32;
1430 info->ecc_size = 32;
1431 ecc->mode = NAND_ECC_HW;
1432 ecc->size = info->chunk_size;
1433 ecc->layout = &ecc_layout_4KB_bch4bit;
1434 ecc->strength = 16;
Ezequiel Garcia70ed8522013-11-14 18:25:37 -03001435
Brian Norris6033a942013-11-14 14:41:32 -08001436 /*
1437 * Required ECC: 8-bit correction per 512 bytes
1438 * Select: 16-bit correction per 1024 bytes
1439 */
1440 } else if (strength == 8 && ecc_stepsize == 512 && page_size == 4096) {
Ezequiel Garcia70ed8522013-11-14 18:25:37 -03001441 info->ecc_bch = 1;
1442 info->chunk_size = 1024;
1443 info->spare_size = 0;
1444 info->ecc_size = 32;
1445 ecc->mode = NAND_ECC_HW;
1446 ecc->size = info->chunk_size;
1447 ecc->layout = &ecc_layout_4KB_bch8bit;
1448 ecc->strength = 16;
Ezequiel Garciaeee01662014-05-14 14:58:07 -03001449 } else {
1450 dev_err(&info->pdev->dev,
1451 "ECC strength %d at page size %d is not supported\n",
1452 strength, page_size);
1453 return -ENODEV;
Ezequiel Garcia70ed8522013-11-14 18:25:37 -03001454 }
Ezequiel Garciaeee01662014-05-14 14:58:07 -03001455
1456 dev_info(&info->pdev->dev, "ECC strength %d, ECC step size %d\n",
1457 ecc->strength, ecc->size);
Ezequiel Garcia43bcfd22013-11-14 18:25:29 -03001458 return 0;
1459}
1460
Lei Wen401e67e2011-02-28 10:32:14 +08001461static int pxa3xx_nand_scan(struct mtd_info *mtd)
1462{
Lei Wend4568822011-07-14 20:44:32 -07001463 struct pxa3xx_nand_host *host = mtd->priv;
1464 struct pxa3xx_nand_info *info = host->info_data;
Lei Wen401e67e2011-02-28 10:32:14 +08001465 struct platform_device *pdev = info->pdev;
Jingoo Han453810b2013-07-30 17:18:33 +09001466 struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
Lei Wen0fab0282011-06-07 03:01:06 -07001467 struct nand_flash_dev pxa3xx_flash_ids[2], *def = NULL;
Lei Wen401e67e2011-02-28 10:32:14 +08001468 const struct pxa3xx_nand_flash *f = NULL;
1469 struct nand_chip *chip = mtd->priv;
1470 uint32_t id = -1;
Lei Wen4332c112011-03-03 11:27:01 +08001471 uint64_t chipsize;
Lei Wen401e67e2011-02-28 10:32:14 +08001472 int i, ret, num;
Ezequiel Garcia30b2afc2013-12-18 18:44:10 -03001473 uint16_t ecc_strength, ecc_step;
Lei Wen401e67e2011-02-28 10:32:14 +08001474
1475 if (pdata->keep_config && !pxa3xx_nand_detect_config(info))
Lei Wen4332c112011-03-03 11:27:01 +08001476 goto KEEP_CONFIG;
Lei Wen401e67e2011-02-28 10:32:14 +08001477
1478 ret = pxa3xx_nand_sensing(info);
Lei Wend4568822011-07-14 20:44:32 -07001479 if (ret) {
Lei Wenf3c8cfc2011-07-14 20:44:33 -07001480 dev_info(&info->pdev->dev, "There is no chip on cs %d!\n",
1481 info->cs);
Lei Wen401e67e2011-02-28 10:32:14 +08001482
Lei Wend4568822011-07-14 20:44:32 -07001483 return ret;
Lei Wen401e67e2011-02-28 10:32:14 +08001484 }
1485
1486 chip->cmdfunc(mtd, NAND_CMD_READID, 0, 0);
1487 id = *((uint16_t *)(info->data_buff));
1488 if (id != 0)
Lei Wenda675b42011-07-14 20:44:31 -07001489 dev_info(&info->pdev->dev, "Detect a flash id %x\n", id);
Lei Wen401e67e2011-02-28 10:32:14 +08001490 else {
Lei Wenda675b42011-07-14 20:44:31 -07001491 dev_warn(&info->pdev->dev,
1492 "Read out ID 0, potential timing set wrong!!\n");
Lei Wen401e67e2011-02-28 10:32:14 +08001493
1494 return -EINVAL;
1495 }
1496
1497 num = ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1;
1498 for (i = 0; i < num; i++) {
1499 if (i < pdata->num_flash)
1500 f = pdata->flash + i;
1501 else
1502 f = &builtin_flash_types[i - pdata->num_flash + 1];
1503
1504 /* find the chip in default list */
Lei Wen4332c112011-03-03 11:27:01 +08001505 if (f->chip_id == id)
Lei Wen401e67e2011-02-28 10:32:14 +08001506 break;
Lei Wen401e67e2011-02-28 10:32:14 +08001507 }
1508
Lei Wen4332c112011-03-03 11:27:01 +08001509 if (i >= (ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1)) {
Lei Wenda675b42011-07-14 20:44:31 -07001510 dev_err(&info->pdev->dev, "ERROR!! flash not defined!!!\n");
Lei Wen401e67e2011-02-28 10:32:14 +08001511
1512 return -EINVAL;
1513 }
1514
Lei Wend4568822011-07-14 20:44:32 -07001515 ret = pxa3xx_nand_config_flash(info, f);
1516 if (ret) {
1517 dev_err(&info->pdev->dev, "ERROR! Configure failed\n");
1518 return ret;
1519 }
1520
Antoine Ténart7c2f7172015-02-12 15:53:27 +01001521 memset(pxa3xx_flash_ids, 0, sizeof(pxa3xx_flash_ids));
1522
Lei Wen4332c112011-03-03 11:27:01 +08001523 pxa3xx_flash_ids[0].name = f->name;
Artem Bityutskiy68aa352de2013-03-04 16:05:00 +02001524 pxa3xx_flash_ids[0].dev_id = (f->chip_id >> 8) & 0xffff;
Lei Wen4332c112011-03-03 11:27:01 +08001525 pxa3xx_flash_ids[0].pagesize = f->page_size;
1526 chipsize = (uint64_t)f->num_blocks * f->page_per_block * f->page_size;
1527 pxa3xx_flash_ids[0].chipsize = chipsize >> 20;
1528 pxa3xx_flash_ids[0].erasesize = f->page_size * f->page_per_block;
1529 if (f->flash_width == 16)
1530 pxa3xx_flash_ids[0].options = NAND_BUSWIDTH_16;
Lei Wen0fab0282011-06-07 03:01:06 -07001531 pxa3xx_flash_ids[1].name = NULL;
1532 def = pxa3xx_flash_ids;
Lei Wen4332c112011-03-03 11:27:01 +08001533KEEP_CONFIG:
Ezequiel Garcia48cf7ef2013-08-12 14:14:55 -03001534 if (info->reg_ndcr & NDCR_DWIDTH_M)
Lei Wend4568822011-07-14 20:44:32 -07001535 chip->options |= NAND_BUSWIDTH_16;
1536
Ezequiel Garcia43bcfd22013-11-14 18:25:29 -03001537 /* Device detection must be done with ECC disabled */
1538 if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)
1539 nand_writel(info, NDECCCTRL, 0x0);
1540
Lei Wen0fab0282011-06-07 03:01:06 -07001541 if (nand_scan_ident(mtd, 1, def))
Lei Wen4332c112011-03-03 11:27:01 +08001542 return -ENODEV;
Ezequiel Garcia776f2652013-11-14 18:25:28 -03001543
1544 if (pdata->flash_bbt) {
1545 /*
1546 * We'll use a bad block table stored in-flash and don't
1547 * allow writing the bad block marker to the flash.
1548 */
1549 chip->bbt_options |= NAND_BBT_USE_FLASH |
1550 NAND_BBT_NO_OOB_BBM;
1551 chip->bbt_td = &bbt_main_descr;
1552 chip->bbt_md = &bbt_mirror_descr;
1553 }
1554
Ezequiel Garcia5cbbdc62013-12-18 18:44:09 -03001555 /*
1556 * If the page size is bigger than the FIFO size, let's check
1557 * we are given the right variant and then switch to the extended
1558 * (aka splitted) command handling,
1559 */
1560 if (mtd->writesize > PAGE_CHUNK_SIZE) {
1561 if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370) {
1562 chip->cmdfunc = nand_cmdfunc_extended;
1563 } else {
1564 dev_err(&info->pdev->dev,
1565 "unsupported page size on this variant\n");
1566 return -ENODEV;
1567 }
1568 }
1569
Ezequiel Garcia5b3e5072014-05-14 14:58:08 -03001570 if (pdata->ecc_strength && pdata->ecc_step_size) {
1571 ecc_strength = pdata->ecc_strength;
1572 ecc_step = pdata->ecc_step_size;
1573 } else {
1574 ecc_strength = chip->ecc_strength_ds;
1575 ecc_step = chip->ecc_step_ds;
1576 }
Ezequiel Garcia30b2afc2013-12-18 18:44:10 -03001577
1578 /* Set default ECC strength requirements on non-ONFI devices */
1579 if (ecc_strength < 1 && ecc_step < 1) {
1580 ecc_strength = 1;
1581 ecc_step = 512;
1582 }
1583
1584 ret = pxa_ecc_init(info, &chip->ecc, ecc_strength,
1585 ecc_step, mtd->writesize);
Ezequiel Garciaeee01662014-05-14 14:58:07 -03001586 if (ret)
1587 return ret;
Ezequiel Garcia43bcfd22013-11-14 18:25:29 -03001588
Lei Wen4332c112011-03-03 11:27:01 +08001589 /* calculate addressing information */
Lei Wend4568822011-07-14 20:44:32 -07001590 if (mtd->writesize >= 2048)
1591 host->col_addr_cycles = 2;
1592 else
1593 host->col_addr_cycles = 1;
1594
Ezequiel Garcia62e8b852013-10-04 15:30:38 -03001595 /* release the initial buffer */
1596 kfree(info->data_buff);
1597
1598 /* allocate the real data + oob buffer */
1599 info->buf_size = mtd->writesize + mtd->oobsize;
1600 ret = pxa3xx_nand_init_buff(info);
1601 if (ret)
1602 return ret;
Lei Wen4332c112011-03-03 11:27:01 +08001603 info->oob_buff = info->data_buff + mtd->writesize;
Ezequiel Garcia62e8b852013-10-04 15:30:38 -03001604
Lei Wen4332c112011-03-03 11:27:01 +08001605 if ((mtd->size >> chip->page_shift) > 65536)
Lei Wend4568822011-07-14 20:44:32 -07001606 host->row_addr_cycles = 3;
Lei Wen4332c112011-03-03 11:27:01 +08001607 else
Lei Wend4568822011-07-14 20:44:32 -07001608 host->row_addr_cycles = 2;
Lei Wen401e67e2011-02-28 10:32:14 +08001609 return nand_scan_tail(mtd);
eric miaofe69af02008-02-14 15:48:23 +08001610}
1611
Lei Wend4568822011-07-14 20:44:32 -07001612static int alloc_nand_resource(struct platform_device *pdev)
eric miaofe69af02008-02-14 15:48:23 +08001613{
Lei Wenf3c8cfc2011-07-14 20:44:33 -07001614 struct pxa3xx_nand_platform_data *pdata;
eric miaofe69af02008-02-14 15:48:23 +08001615 struct pxa3xx_nand_info *info;
Lei Wend4568822011-07-14 20:44:32 -07001616 struct pxa3xx_nand_host *host;
Haojian Zhuang6e308f82012-08-20 13:40:31 +08001617 struct nand_chip *chip = NULL;
eric miaofe69af02008-02-14 15:48:23 +08001618 struct mtd_info *mtd;
1619 struct resource *r;
Lei Wenf3c8cfc2011-07-14 20:44:33 -07001620 int ret, irq, cs;
eric miaofe69af02008-02-14 15:48:23 +08001621
Jingoo Han453810b2013-07-30 17:18:33 +09001622 pdata = dev_get_platdata(&pdev->dev);
Robert Jarzmike423c902015-02-08 21:02:09 +01001623 if (pdata->num_cs <= 0)
1624 return -ENODEV;
Ezequiel Garcia4c073cd2013-04-17 13:38:09 -03001625 info = devm_kzalloc(&pdev->dev, sizeof(*info) + (sizeof(*mtd) +
1626 sizeof(*host)) * pdata->num_cs, GFP_KERNEL);
1627 if (!info)
Lei Wend4568822011-07-14 20:44:32 -07001628 return -ENOMEM;
eric miaofe69af02008-02-14 15:48:23 +08001629
eric miaofe69af02008-02-14 15:48:23 +08001630 info->pdev = pdev;
Ezequiel Garciac7e9c7e2013-11-07 12:17:14 -03001631 info->variant = pxa3xx_nand_get_variant(pdev);
Lei Wenf3c8cfc2011-07-14 20:44:33 -07001632 for (cs = 0; cs < pdata->num_cs; cs++) {
1633 mtd = (struct mtd_info *)((unsigned int)&info[1] +
1634 (sizeof(*mtd) + sizeof(*host)) * cs);
1635 chip = (struct nand_chip *)(&mtd[1]);
1636 host = (struct pxa3xx_nand_host *)chip;
1637 info->host[cs] = host;
1638 host->mtd = mtd;
1639 host->cs = cs;
1640 host->info_data = info;
1641 mtd->priv = host;
1642 mtd->owner = THIS_MODULE;
eric miaofe69af02008-02-14 15:48:23 +08001643
Lei Wenf3c8cfc2011-07-14 20:44:33 -07001644 chip->ecc.read_page = pxa3xx_nand_read_page_hwecc;
1645 chip->ecc.write_page = pxa3xx_nand_write_page_hwecc;
1646 chip->controller = &info->controller;
1647 chip->waitfunc = pxa3xx_nand_waitfunc;
1648 chip->select_chip = pxa3xx_nand_select_chip;
Lei Wenf3c8cfc2011-07-14 20:44:33 -07001649 chip->read_word = pxa3xx_nand_read_word;
1650 chip->read_byte = pxa3xx_nand_read_byte;
1651 chip->read_buf = pxa3xx_nand_read_buf;
1652 chip->write_buf = pxa3xx_nand_write_buf;
Ezequiel Garcia664c7f52013-11-07 12:17:12 -03001653 chip->options |= NAND_NO_SUBPAGE_WRITE;
Ezequiel Garcia5cbbdc62013-12-18 18:44:09 -03001654 chip->cmdfunc = nand_cmdfunc;
Lei Wenf3c8cfc2011-07-14 20:44:33 -07001655 }
Lei Wen401e67e2011-02-28 10:32:14 +08001656
1657 spin_lock_init(&chip->controller->lock);
1658 init_waitqueue_head(&chip->controller->wq);
Ezequiel Garcia9ca79442013-04-17 13:38:11 -03001659 info->clk = devm_clk_get(&pdev->dev, NULL);
eric miaofe69af02008-02-14 15:48:23 +08001660 if (IS_ERR(info->clk)) {
1661 dev_err(&pdev->dev, "failed to get nand clock\n");
Ezequiel Garcia4c073cd2013-04-17 13:38:09 -03001662 return PTR_ERR(info->clk);
eric miaofe69af02008-02-14 15:48:23 +08001663 }
Ezequiel Garcia1f8eaff2013-04-17 13:38:13 -03001664 ret = clk_prepare_enable(info->clk);
1665 if (ret < 0)
1666 return ret;
eric miaofe69af02008-02-14 15:48:23 +08001667
Ezequiel Garcia6b45c1e2013-08-12 14:14:58 -03001668 if (use_dma) {
1669 /*
1670 * This is a dirty hack to make this driver work from
1671 * devicetree bindings. It can be removed once we have
1672 * a prober DMA controller framework for DT.
1673 */
1674 if (pdev->dev.of_node &&
1675 of_machine_is_compatible("marvell,pxa3xx")) {
1676 info->drcmr_dat = 97;
1677 info->drcmr_cmd = 99;
1678 } else {
1679 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1680 if (r == NULL) {
1681 dev_err(&pdev->dev,
1682 "no resource defined for data DMA\n");
1683 ret = -ENXIO;
1684 goto fail_disable_clk;
1685 }
1686 info->drcmr_dat = r->start;
eric miaofe69af02008-02-14 15:48:23 +08001687
Ezequiel Garcia6b45c1e2013-08-12 14:14:58 -03001688 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1689 if (r == NULL) {
1690 dev_err(&pdev->dev,
1691 "no resource defined for cmd DMA\n");
1692 ret = -ENXIO;
1693 goto fail_disable_clk;
1694 }
1695 info->drcmr_cmd = r->start;
Daniel Mack1e7ba632012-07-22 19:51:02 +02001696 }
eric miaofe69af02008-02-14 15:48:23 +08001697 }
eric miaofe69af02008-02-14 15:48:23 +08001698
1699 irq = platform_get_irq(pdev, 0);
1700 if (irq < 0) {
1701 dev_err(&pdev->dev, "no IRQ resource defined\n");
1702 ret = -ENXIO;
Ezequiel Garcia9ca79442013-04-17 13:38:11 -03001703 goto fail_disable_clk;
eric miaofe69af02008-02-14 15:48:23 +08001704 }
1705
1706 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Ezequiel Garcia0ddd8462013-04-17 13:38:10 -03001707 info->mmio_base = devm_ioremap_resource(&pdev->dev, r);
1708 if (IS_ERR(info->mmio_base)) {
1709 ret = PTR_ERR(info->mmio_base);
Ezequiel Garcia9ca79442013-04-17 13:38:11 -03001710 goto fail_disable_clk;
eric miaofe69af02008-02-14 15:48:23 +08001711 }
Haojian Zhuang8638fac2009-09-10 14:11:44 +08001712 info->mmio_phys = r->start;
eric miaofe69af02008-02-14 15:48:23 +08001713
Ezequiel Garcia62e8b852013-10-04 15:30:38 -03001714 /* Allocate a buffer to allow flash detection */
1715 info->buf_size = INIT_BUFFER_SIZE;
1716 info->data_buff = kmalloc(info->buf_size, GFP_KERNEL);
1717 if (info->data_buff == NULL) {
1718 ret = -ENOMEM;
Ezequiel Garcia9ca79442013-04-17 13:38:11 -03001719 goto fail_disable_clk;
Ezequiel Garcia62e8b852013-10-04 15:30:38 -03001720 }
eric miaofe69af02008-02-14 15:48:23 +08001721
Haojian Zhuang346e1252009-09-10 14:27:23 +08001722 /* initialize all interrupts to be disabled */
1723 disable_int(info, NDSR_MASK);
1724
Robert Jarzmik24542252015-02-20 19:36:43 +01001725 ret = request_threaded_irq(irq, pxa3xx_nand_irq,
1726 pxa3xx_nand_irq_thread, IRQF_ONESHOT,
1727 pdev->name, info);
eric miaofe69af02008-02-14 15:48:23 +08001728 if (ret < 0) {
1729 dev_err(&pdev->dev, "failed to request IRQ\n");
1730 goto fail_free_buf;
1731 }
1732
Lei Wene353a202011-03-03 11:08:30 +08001733 platform_set_drvdata(pdev, info);
eric miaofe69af02008-02-14 15:48:23 +08001734
Lei Wend4568822011-07-14 20:44:32 -07001735 return 0;
eric miaofe69af02008-02-14 15:48:23 +08001736
eric miaofe69af02008-02-14 15:48:23 +08001737fail_free_buf:
Lei Wen401e67e2011-02-28 10:32:14 +08001738 free_irq(irq, info);
Ezequiel Garcia62e8b852013-10-04 15:30:38 -03001739 kfree(info->data_buff);
Ezequiel Garcia9ca79442013-04-17 13:38:11 -03001740fail_disable_clk:
Ezequiel Garciafb320612013-04-17 13:38:12 -03001741 clk_disable_unprepare(info->clk);
Lei Wend4568822011-07-14 20:44:32 -07001742 return ret;
eric miaofe69af02008-02-14 15:48:23 +08001743}
1744
1745static int pxa3xx_nand_remove(struct platform_device *pdev)
1746{
Lei Wene353a202011-03-03 11:08:30 +08001747 struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
Lei Wenf3c8cfc2011-07-14 20:44:33 -07001748 struct pxa3xx_nand_platform_data *pdata;
Lei Wenf3c8cfc2011-07-14 20:44:33 -07001749 int irq, cs;
eric miaofe69af02008-02-14 15:48:23 +08001750
Lei Wend4568822011-07-14 20:44:32 -07001751 if (!info)
1752 return 0;
1753
Jingoo Han453810b2013-07-30 17:18:33 +09001754 pdata = dev_get_platdata(&pdev->dev);
eric miaofe69af02008-02-14 15:48:23 +08001755
Haojian Zhuangdbf59862009-09-10 14:22:55 +08001756 irq = platform_get_irq(pdev, 0);
1757 if (irq >= 0)
1758 free_irq(irq, info);
Ezequiel Garcia498b6142013-04-17 13:38:14 -03001759 pxa3xx_nand_free_buff(info);
Mike Rapoport82a72d12009-02-17 13:54:46 +02001760
Ezequiel Garciafb320612013-04-17 13:38:12 -03001761 clk_disable_unprepare(info->clk);
Mike Rapoport82a72d12009-02-17 13:54:46 +02001762
Lei Wenf3c8cfc2011-07-14 20:44:33 -07001763 for (cs = 0; cs < pdata->num_cs; cs++)
1764 nand_release(info->host[cs]->mtd);
eric miaofe69af02008-02-14 15:48:23 +08001765 return 0;
1766}
1767
Daniel Mack1e7ba632012-07-22 19:51:02 +02001768static int pxa3xx_nand_probe_dt(struct platform_device *pdev)
1769{
1770 struct pxa3xx_nand_platform_data *pdata;
1771 struct device_node *np = pdev->dev.of_node;
1772 const struct of_device_id *of_id =
1773 of_match_device(pxa3xx_nand_dt_ids, &pdev->dev);
1774
1775 if (!of_id)
1776 return 0;
1777
1778 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1779 if (!pdata)
1780 return -ENOMEM;
1781
1782 if (of_get_property(np, "marvell,nand-enable-arbiter", NULL))
1783 pdata->enable_arbiter = 1;
1784 if (of_get_property(np, "marvell,nand-keep-config", NULL))
1785 pdata->keep_config = 1;
1786 of_property_read_u32(np, "num-cs", &pdata->num_cs);
Ezequiel Garcia776f2652013-11-14 18:25:28 -03001787 pdata->flash_bbt = of_get_nand_on_flash_bbt(np);
Daniel Mack1e7ba632012-07-22 19:51:02 +02001788
Ezequiel Garcia5b3e5072014-05-14 14:58:08 -03001789 pdata->ecc_strength = of_get_nand_ecc_strength(np);
1790 if (pdata->ecc_strength < 0)
1791 pdata->ecc_strength = 0;
1792
1793 pdata->ecc_step_size = of_get_nand_ecc_step_size(np);
1794 if (pdata->ecc_step_size < 0)
1795 pdata->ecc_step_size = 0;
1796
Daniel Mack1e7ba632012-07-22 19:51:02 +02001797 pdev->dev.platform_data = pdata;
1798
1799 return 0;
1800}
Daniel Mack1e7ba632012-07-22 19:51:02 +02001801
Lei Wene353a202011-03-03 11:08:30 +08001802static int pxa3xx_nand_probe(struct platform_device *pdev)
1803{
1804 struct pxa3xx_nand_platform_data *pdata;
Daniel Mack1e7ba632012-07-22 19:51:02 +02001805 struct mtd_part_parser_data ppdata = {};
Lei Wene353a202011-03-03 11:08:30 +08001806 struct pxa3xx_nand_info *info;
Lei Wenf3c8cfc2011-07-14 20:44:33 -07001807 int ret, cs, probe_success;
Lei Wene353a202011-03-03 11:08:30 +08001808
Ezequiel Garciaf4db2e32013-08-12 14:14:56 -03001809#ifndef ARCH_HAS_DMA
1810 if (use_dma) {
1811 use_dma = 0;
1812 dev_warn(&pdev->dev,
1813 "This platform can't do DMA on this device\n");
1814 }
1815#endif
Daniel Mack1e7ba632012-07-22 19:51:02 +02001816 ret = pxa3xx_nand_probe_dt(pdev);
1817 if (ret)
1818 return ret;
1819
Jingoo Han453810b2013-07-30 17:18:33 +09001820 pdata = dev_get_platdata(&pdev->dev);
Lei Wene353a202011-03-03 11:08:30 +08001821 if (!pdata) {
1822 dev_err(&pdev->dev, "no platform data defined\n");
1823 return -ENODEV;
1824 }
1825
Lei Wend4568822011-07-14 20:44:32 -07001826 ret = alloc_nand_resource(pdev);
1827 if (ret) {
1828 dev_err(&pdev->dev, "alloc nand resource failed\n");
1829 return ret;
1830 }
Lei Wene353a202011-03-03 11:08:30 +08001831
Lei Wend4568822011-07-14 20:44:32 -07001832 info = platform_get_drvdata(pdev);
Lei Wenf3c8cfc2011-07-14 20:44:33 -07001833 probe_success = 0;
1834 for (cs = 0; cs < pdata->num_cs; cs++) {
Ezequiel Garciab7655bc2013-08-12 14:14:52 -03001835 struct mtd_info *mtd = info->host[cs]->mtd;
Ezequiel Garciaf4555782013-08-12 14:14:53 -03001836
Ezequiel Garcia18a84e92013-10-19 18:19:25 -03001837 /*
1838 * The mtd name matches the one used in 'mtdparts' kernel
1839 * parameter. This name cannot be changed or otherwise
1840 * user's mtd partitions configuration would get broken.
1841 */
1842 mtd->name = "pxa3xx_nand-0";
Lei Wenf3c8cfc2011-07-14 20:44:33 -07001843 info->cs = cs;
Ezequiel Garciab7655bc2013-08-12 14:14:52 -03001844 ret = pxa3xx_nand_scan(mtd);
Lei Wenf3c8cfc2011-07-14 20:44:33 -07001845 if (ret) {
1846 dev_warn(&pdev->dev, "failed to scan nand at cs %d\n",
1847 cs);
1848 continue;
1849 }
1850
Daniel Mack1e7ba632012-07-22 19:51:02 +02001851 ppdata.of_node = pdev->dev.of_node;
Ezequiel Garciab7655bc2013-08-12 14:14:52 -03001852 ret = mtd_device_parse_register(mtd, NULL,
Daniel Mack1e7ba632012-07-22 19:51:02 +02001853 &ppdata, pdata->parts[cs],
Artem Bityutskiy42d7fbe2012-03-09 19:24:26 +02001854 pdata->nr_parts[cs]);
Lei Wenf3c8cfc2011-07-14 20:44:33 -07001855 if (!ret)
1856 probe_success = 1;
1857 }
1858
1859 if (!probe_success) {
Lei Wene353a202011-03-03 11:08:30 +08001860 pxa3xx_nand_remove(pdev);
1861 return -ENODEV;
1862 }
1863
Lei Wenf3c8cfc2011-07-14 20:44:33 -07001864 return 0;
Lei Wene353a202011-03-03 11:08:30 +08001865}
1866
eric miaofe69af02008-02-14 15:48:23 +08001867#ifdef CONFIG_PM
1868static int pxa3xx_nand_suspend(struct platform_device *pdev, pm_message_t state)
1869{
Lei Wene353a202011-03-03 11:08:30 +08001870 struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
Lei Wenf3c8cfc2011-07-14 20:44:33 -07001871 struct pxa3xx_nand_platform_data *pdata;
1872 struct mtd_info *mtd;
1873 int cs;
eric miaofe69af02008-02-14 15:48:23 +08001874
Jingoo Han453810b2013-07-30 17:18:33 +09001875 pdata = dev_get_platdata(&pdev->dev);
Lei Wenf8155a42011-02-28 10:32:11 +08001876 if (info->state) {
eric miaofe69af02008-02-14 15:48:23 +08001877 dev_err(&pdev->dev, "driver busy, state = %d\n", info->state);
1878 return -EAGAIN;
1879 }
1880
Lei Wenf3c8cfc2011-07-14 20:44:33 -07001881 for (cs = 0; cs < pdata->num_cs; cs++) {
1882 mtd = info->host[cs]->mtd;
Artem Bityutskiy3fe4bae2011-12-23 19:25:16 +02001883 mtd_suspend(mtd);
Lei Wenf3c8cfc2011-07-14 20:44:33 -07001884 }
1885
eric miaofe69af02008-02-14 15:48:23 +08001886 return 0;
1887}
1888
1889static int pxa3xx_nand_resume(struct platform_device *pdev)
1890{
Lei Wene353a202011-03-03 11:08:30 +08001891 struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
Lei Wenf3c8cfc2011-07-14 20:44:33 -07001892 struct pxa3xx_nand_platform_data *pdata;
1893 struct mtd_info *mtd;
1894 int cs;
Lei Wen051fc412011-07-14 20:44:30 -07001895
Jingoo Han453810b2013-07-30 17:18:33 +09001896 pdata = dev_get_platdata(&pdev->dev);
Lei Wen051fc412011-07-14 20:44:30 -07001897 /* We don't want to handle interrupt without calling mtd routine */
1898 disable_int(info, NDCR_INT_MASK);
eric miaofe69af02008-02-14 15:48:23 +08001899
Lei Wenf3c8cfc2011-07-14 20:44:33 -07001900 /*
1901 * Directly set the chip select to a invalid value,
1902 * then the driver would reset the timing according
1903 * to current chip select at the beginning of cmdfunc
1904 */
1905 info->cs = 0xff;
eric miaofe69af02008-02-14 15:48:23 +08001906
Lei Wen051fc412011-07-14 20:44:30 -07001907 /*
1908 * As the spec says, the NDSR would be updated to 0x1800 when
1909 * doing the nand_clk disable/enable.
1910 * To prevent it damaging state machine of the driver, clear
1911 * all status before resume
1912 */
1913 nand_writel(info, NDSR, NDSR_MASK);
Lei Wenf3c8cfc2011-07-14 20:44:33 -07001914 for (cs = 0; cs < pdata->num_cs; cs++) {
1915 mtd = info->host[cs]->mtd;
Artem Bityutskiyead995f2011-12-23 19:31:25 +02001916 mtd_resume(mtd);
Lei Wenf3c8cfc2011-07-14 20:44:33 -07001917 }
1918
Lei Wen18c81b12010-08-17 17:25:57 +08001919 return 0;
eric miaofe69af02008-02-14 15:48:23 +08001920}
1921#else
1922#define pxa3xx_nand_suspend NULL
1923#define pxa3xx_nand_resume NULL
1924#endif
1925
1926static struct platform_driver pxa3xx_nand_driver = {
1927 .driver = {
1928 .name = "pxa3xx-nand",
Sachin Kamat5576bc72013-09-30 15:10:24 +05301929 .of_match_table = pxa3xx_nand_dt_ids,
eric miaofe69af02008-02-14 15:48:23 +08001930 },
1931 .probe = pxa3xx_nand_probe,
1932 .remove = pxa3xx_nand_remove,
1933 .suspend = pxa3xx_nand_suspend,
1934 .resume = pxa3xx_nand_resume,
1935};
1936
Axel Linf99640d2011-11-27 20:45:03 +08001937module_platform_driver(pxa3xx_nand_driver);
eric miaofe69af02008-02-14 15:48:23 +08001938
1939MODULE_LICENSE("GPL");
1940MODULE_DESCRIPTION("PXA3xx NAND controller driver");