blob: 867bf8bf556159ffcb12584d6d1bb8788ab7b821 [file] [log] [blame]
Colin Crossd8611962010-01-28 16:40:29 -08001/*
2 *
3 * Copyright (C) 2010 Google, Inc.
Prashant Gaikwad96a1bd12012-08-06 11:57:42 +05304 * Copyright (c) 2012 NVIDIA CORPORATION. All rights reserved.
Colin Crossd8611962010-01-28 16:40:29 -08005 *
6 * Author:
7 * Colin Cross <ccross@google.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20#include <linux/kernel.h>
21#include <linux/clk.h>
Jean-Christop PLAGNIOL-VILLARD6d803ba2010-11-17 10:04:33 +010022#include <linux/clkdev.h>
Colin Cross4729fd72011-02-12 16:43:05 -080023#include <linux/init.h>
24#include <linux/list.h>
25#include <linux/module.h>
26#include <linux/sched.h>
27#include <linux/seq_file.h>
28#include <linux/slab.h>
29
Colin Cross71fc84c2010-06-07 20:49:46 -070030#include "board.h"
Colin Cross41cfe362011-02-12 15:52:04 -080031#include "clock.h"
Joseph Lodab403e2012-08-16 17:31:48 +080032#include "tegra_cpu_car.h"
33
34/* Global data of Tegra CPU CAR ops */
35struct tegra_cpu_car_ops *tegra_cpu_car_ops;
Colin Crossd8611962010-01-28 16:40:29 -080036
Colin Cross4729fd72011-02-12 16:43:05 -080037/*
38 * Locking:
39 *
Colin Cross4729fd72011-02-12 16:43:05 -080040 * An additional mutex, clock_list_lock, is used to protect the list of all
41 * clocks.
42 *
Colin Cross4729fd72011-02-12 16:43:05 -080043 */
44static DEFINE_MUTEX(clock_list_lock);
Colin Crossd8611962010-01-28 16:40:29 -080045static LIST_HEAD(clocks);
46
Prashant Gaikwad96a1bd12012-08-06 11:57:42 +053047void tegra_clk_add(struct clk *clk)
48{
49 struct clk_tegra *c = to_clk_tegra(__clk_get_hw(clk));
50
51 mutex_lock(&clock_list_lock);
52 list_add(&c->node, &clocks);
53 mutex_unlock(&clock_list_lock);
54}
55
56struct clk *tegra_get_clock_by_name(const char *name)
57{
58 struct clk_tegra *c;
59 struct clk *ret = NULL;
60 mutex_lock(&clock_list_lock);
61 list_for_each_entry(c, &clocks, node) {
62 if (strcmp(__clk_get_name(c->hw.clk), name) == 0) {
63 ret = c->hw.clk;
64 break;
65 }
66 }
67 mutex_unlock(&clock_list_lock);
68 return ret;
69}
70
71static int tegra_clk_init_one_from_table(struct tegra_clk_init_table *table)
72{
73 struct clk *c;
74 struct clk *p;
75 struct clk *parent;
76
77 int ret = 0;
78
79 c = tegra_get_clock_by_name(table->name);
80
81 if (!c) {
82 pr_warn("Unable to initialize clock %s\n",
83 table->name);
84 return -ENODEV;
85 }
86
87 parent = clk_get_parent(c);
88
89 if (table->parent) {
90 p = tegra_get_clock_by_name(table->parent);
91 if (!p) {
92 pr_warn("Unable to find parent %s of clock %s\n",
93 table->parent, table->name);
94 return -ENODEV;
95 }
96
97 if (parent != p) {
98 ret = clk_set_parent(c, p);
99 if (ret) {
100 pr_warn("Unable to set parent %s of clock %s: %d\n",
101 table->parent, table->name, ret);
102 return -EINVAL;
103 }
104 }
105 }
106
107 if (table->rate && table->rate != clk_get_rate(c)) {
108 ret = clk_set_rate(c, table->rate);
109 if (ret) {
110 pr_warn("Unable to set clock %s to rate %lu: %d\n",
111 table->name, table->rate, ret);
112 return -EINVAL;
113 }
114 }
115
116 if (table->enabled) {
117 ret = clk_prepare_enable(c);
118 if (ret) {
119 pr_warn("Unable to enable clock %s: %d\n",
120 table->name, ret);
121 return -EINVAL;
122 }
123 }
124
125 return 0;
126}
127
128void tegra_clk_init_from_table(struct tegra_clk_init_table *table)
129{
130 for (; table->name; table++)
131 tegra_clk_init_one_from_table(table);
132}
133
134void tegra_periph_reset_deassert(struct clk *c)
135{
136 struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c));
137 BUG_ON(!clk->reset);
138 clk->reset(__clk_get_hw(c), false);
139}
140EXPORT_SYMBOL(tegra_periph_reset_deassert);
141
142void tegra_periph_reset_assert(struct clk *c)
143{
144 struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c));
145 BUG_ON(!clk->reset);
146 clk->reset(__clk_get_hw(c), true);
147}
148EXPORT_SYMBOL(tegra_periph_reset_assert);
149
150/* Several extended clock configuration bits (e.g., clock routing, clock
151 * phase control) are included in PLL and peripheral clock source
152 * registers. */
153int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
154{
155 int ret = 0;
156 struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c));
157
158 if (!clk->clk_cfg_ex) {
159 ret = -ENOSYS;
160 goto out;
161 }
162 ret = clk->clk_cfg_ex(__clk_get_hw(c), p, setting);
163
164out:
165 return ret;
166}